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Adiabatic quantum-flux-parametron (AQFP) logic can achieve high energy-efficiency. The bit energy and bit-error-rate (BER) of AQFP gates with under-damped Josephson junctions were simulated. The results indicate that the bit energy reaches 12 yJ, which is only 20% of the thermal energy at 4.2 K, using unshunted 50-μA junctions and excitation currents with a rise/fall time of 2000 ps. Although the bit energy is extremely small, the bias margin, where the BER is less than 10-23, is approximately ±22%. These results indicate there is no minimum energy limitation for the operation of AQFP gates unless the entropy of the system decreases. [ABSTRACT FROM AUTHOR]

Novel reconfigurable superconductive single flux quantum (SFQ) logic devices, the functions of which can be dynamically reconfigured by inputting control signals, have been investigated. The characteristics of single flux quantum circuits can be easily modulated by applying currents or magnetic fields because of the high sensitivity of superconductive circuits. We investigated several design approaches for the realization of dynamically reconfigurable SFQ logic devices. We employed direct current injection to the logic gate using a non-destructive read-out flip-flop. By changing the internal state of the non-destructive read-out flip-flop, the logic function can be dynamically reconfigured. We have designed and tested a dynamically reconfigurable Josephson transmission line (JTL)/delay flip-flop (DFF) circuit. The measured dc bias margin was 72.5–107.2%. Furthermore, we have demonstrated the operation of a variable bit-length shift register, composed of the dynamically reconfigurable JTL/DFF circuits. The investigated design approach can be applied to more sophisticated dynamically reconfigurable single flux quantum logic gates. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we propose the development of superconductive combinational logic circuits. One of the difficulties in designing superconductive single-flux-quantum (SFQ) digital circuits can be attributed to the fundamental nature of the SFQ circuits, in which all logic gates have latching functions and are based on sequential logic. The design of ultralow-power superconductive digital circuits can be facilitated by the development of superconductive combinational logic circuits in which the output is a function of only the present input. This is because superconductive combinational logic circuits do not require determination of the timing adjustment and clocking scheme. Moreover, semiconductor design tools can be used to design digital circuits because CMOS logic gates are based on combinational logic. The proposed superconductive combinational logic circuits comprise a magnetically coupled SQUID array. By adjusting the circuit parameters and coupling strengths between neighboring SQUIDs, fundamental combinational logic gates, including the AND, OR, and NOT gates, can be built. We have verified the accuracy of the operations of the fundamental logic gates by analog circuit simulations. [ABSTRACT FROM AUTHOR]

Abstract: High-frequency microwave applications, such as filters, delay lines, and resonators, are quite important for superconducting electronic devices. In order to design the superconducting microwave devices, circuit parameters should be precisely extracted from the physical structure of the devices. A 3-dimentional electromagnetic-field simulator is very useful for designing microwave devices. However, designing of superconducting microwave devices using a conventional 3D electromagnetic-field simulator is difficult because most of commercially available 3D electromagnetic-field simulators can not exactly characterize electromagnetic phenomena of superconductors. In this study, a novel calculation method of superconducting microwave devices, which can be applicable to a conventional 3D electromagnetic-field simulator, has been proposed. Calculation results of characteristic impedance of superconducting microstrip lines show very good agreements with the theoretically calculated vales. The frequency response of a superconducting Nb microwave filter designed by the proposed calculation method agrees well with the experimental results. This calculation method enables us to precisely estimate microwave characteristics of superconducting devices. [Copyright &y& Elsevier]

Abstract: Ultra-fast operation with ultra-low power consumption and ballistic transmission of signals are attractive features of single-flux-quantum (SFQ) circuits for building large-scale digital systems. We have been designing SFQ circuits based on the bit-serial architecture, which can reduce the circuit area and timing error induced by clocking skew. In the bit-serial circuits, a serial–parallel converter, which is one of key circuits, is used for I/O interfaces, address decoders, multipliers and so on. In this paper, we propose a novel architecture for the SFQ serial–parallel converter whose latency is very small compared with conventional one. And, we have designed some SFQ circuits suitable for the proposed circuit. As an example, we have implemented and tested SFQ 4-bit multifunctional buffers using the SRL 2.5kA/cm2 niobium standard process. We have successfully confirmed all functions of the multifunctional buffer at low speed. [Copyright &y& Elsevier]

A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1β, was designed and tested. The CORE1β has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1β8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1β8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1β8 microprocessors by on-chip high-speed tests. [ABSTRACT FROM AUTHOR]

Abstract: A new on-chip microwave generator for manipulating superconductive quantum bits (qubits) have been proposed. To perform practical quantum computation, on-chip microwave generators, which can be controlled by single flux quantum (SFQ) circuits, are desirable because multiple qubits can be driven simultaneously with high accuracy by an SFQ control circuit and the number of wires between qubits and room-temperature electronics can be reduced. The proposed on-chip microwave generator is composed of an SFQ clock generator, which generates a periodic SFQ pulse train, and a band-pass filter. A sinusoidal microwave can be obtained by filtering an output of the SFQ clock generator. Simulation results indicate that the generated microwave has a sharp spectrum, which can be chopped by controlling the SFQ clock generator. Moreover, a phase of the generated microwave can be accurately controlled by adding a phase control circuit, which is composed of cascaded toggle flip-flops, between the SFQ clock generator and the filter. The results indicate that we can perform fast and accurate quantum gate operations using the proposed on-chip microwave generator. [Copyright &y& Elsevier]

Abstract: In this paper we have considered how to perform logic synthesis of the single-flux-quantum (SFQ) logic circuits by using logic synthesis tools for semiconductor logic circuits. Fundamental difference of the SFQ logic gates from the semiconductor logic gates in terms of logic synthesis is that typical SFQ gates are clocked gate, where gates have to be clocked by SFQ pulses. In our approach, we divided the procedure into two steps; logic synthesis and clock distribution. In the logic synthesis step, the logic function is optimized using a logic synthesis tool without considering the clock network. The Design Analyzer provided from Synopsys is used in this study. We have developed an SFQ cell library for the logic synthesis. In the clock distribution step, clock networks for every clocked SFQ gates are designed taking account of timing. We used a clock-followed-data clocking scheme in this study. We have classified every clocked gate into stages, where the clocked gates in the same stage are clocked simultaneously. To demonstrate the validity of our approach, we have designed a controller of an 8-bit SFQ microprocessor. [Copyright &y& Elsevier]

A single flux quantum (SFQ) circuit has been designed to demonstrate an energy levels quantization in a Josephson Junction. The high-speed operation of SFQ circuits realizes applying a high-speed ramped bias current to a Josephson junction, which allows the noiseless experiment at higher temperature. A high-speed ramped bias current (dI/dt=2000 A/s) is applied to a Josephson junction using the proposed circuit. Although the energy levels quantization has not been observed yet, the obtained escape rate was high enough to observe the energy levels quantization. The proposed circuit indicates the effectiveness of SFQ circuits as experimental apparatuses. [Copyright &y& Elsevier]

Glycophosphatidylinositol (GPI-linked Thy-1 molecules, well known cell surface markers of murine T cells., are present on the glomerular mesangial cells of the rat kidney. The administration of anti-Thy-1.1 MoAbs 1-22-3 and OX-7 to rats induces severe and mild complement-dependent mesangial proliferutive glomerulonephritis, respectively. In order lo determine whether proteintyrosine kinase (PTK) activity is associated with Thy-1 molecules on rat mesangial cell surface, we performed an immune complex kinase assay, using anti-Thy-1 MoAbs 1-22-3 and OX-7, followed by reimmunoprecipitation with anti-phosphotyrosine, anti-fyn, anti-lck and anti-lyn antibodies, Physical association of PTK, p59fyn and p56/53lyn with Thy-1 molecules was demonstated in cultured rat mesangial cells. The activities of these kinases detected in MoAb 1-22-3 precipitates were higher than those in MoAb OX-7 precipitates. These results suggest that Thy-1 molecule transduces some signals also in rat mesangial cells. [ABSTRACT FROM AUTHOR]

Adiabatic quantum-flux-parametron (AQFP) logic has the potential to operate with an ultimately small bit energy of several zeptojoules; however, this is too small to measure by conventional techniques. We measure such a small energy dissipation by coupling a superconducting resonator with an AQFP gate, where the insertion loss is sensitively varied with the small dissipation due to the very high Q factor of the resonator. We designed and implemented a 5 GHz superconducting resonator coupled with an AQFP gate. Measurement results show that the bit energy of the gate is ∼10 zJ at 5 GHz operation. [ABSTRACT FROM AUTHOR]

Investigates antibodies to the protein tyronsine kinase Lyn. Suggests that the Lyn protein is physically associated with mIgM in B cells and functions in mIgM-mediated signalling.

We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach. [ABSTRACT FROM AUTHOR]

We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than \pm 30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates. [ABSTRACT FROM PUBLISHER]

Highlights: [•] Balanced Josephson comparator decisions depend on previous decisions at high frequencies. [•] The maximum effective data rate is lower than the clock frequency. [•] Tradeoff between maximum effective data rate and minimum comparator gray-zone. [ABSTRACT FROM AUTHOR]

Abstract: We have been studying a superconducting quantum-computing system where superconducting Josephson-junction quantum bits (qubits) are controlled and read out by rapid single-flux-quantum (RSFQ) circuits. In this study, we designed and fabricated an on-chip RSFQ microwave pulse generator (MPG), which generates microwave pulses with the time resolution of sub-ns for precise control of qubit states. The output microwave amplitude of the MPG can be amplified to more than 350μV using a multi-flux-quantum (MFQ) driver, which increases the number of the propagating single-flux-quantum (SFQ) pulses. Fundamental properties of the MFQ driver and the RSFQ MPG were measured at 4.2K. It was confirmed that the MFQ driver can amplify an SFQ pulse up to six MFQ pulses and the irradiation time and the amplitude of the output microwave of the RSFQ MPG can be controlled adequately. [ABSTRACT FROM AUTHOR]

Chronic kidney disease (CKD) patients accumulate uremic toxins in the body, potentially require dialysis, and can eventually develop cardiovascular disease. CKD incidence has increased worldwide, and preventing CKD progression is one of the most important goals in clinical treatment. In this study, we conducted a series of in vitro and in vivo experiments and employed a metabolomics approach to investigate CKD. Our results demonstrated that ATP-binding cassette transporter subfamily G member 2 (ABCG2) is a major transporter of the uremic toxin indoxyl sulfate. ABCG2 regulates the pathophysiological excretion of indoxyl sulfate and strongly affects CKD survival rates. Our study is the first to report ABCG2 as a physiological exporter of indoxyl sulfate and identify ABCG2 as a crucial factor influencing CKD progression, consistent with the observed association between ABCG2 function and age of dialysis onset in humans. The above findings provided valuable knowledge on the complex regulatory mechanisms that regulate the transport of uremic toxins in our body and serve as a basis for preventive and individualized treatment of CKD. [ABSTRACT FROM AUTHOR]

We performed yield analysis of large-scale adiabatic-quantum-flux-parametron (AQFP) circuits using circuit simulations based on the Monte Carlo method assuming the distribution of the critical current of Josephson junctions. Based on the simulation results, we also made an analytical model for the circuit yield of large-scale AQFP circuits. The yield analysis indicates that AQFP integrated circuits containing 1 million gates can be realized when the interconnect inductance is about 40 pH and the normalized standard deviation of the critical current is less than 1%. [ABSTRACT FROM AUTHOR]

Abstract: We present design of single flux quantum (SFQ) cells for a 10-Nb-layer process which has been developed to fabricate SFQ VLSI circuits. The device fabricated by the process has a structure of an active layer on the top, two passive transmission line (PTL) layers in the middle, and a DC power (DCP) layer at the bottom. We have determined a unit cell size of 30μm×30μm and a unit cell structure by taking accounts of the design rules and the experimental data on the PTLs. This cell size enables us to draw two PTLs of each PTL layer. PTL driver and receiver cells have a unit cell size, whereas a half unit cell with a size of 15μm×15μm is used for PTL segments and vias. On the active layer, circuit parameters in analog simulation level are based on those of CONNECT cells, except for junction parameters with McCumber parameter β c of 2.0. Major cells including logic cells and PTL driver/receiver cells have been developed. We have designed a 2×2 switch on-chip test circuit using the cells and successfully tested them at high speed. [Copyright &y& Elsevier]

Abstract: We have demonstrated the components of datapath toward single-flux-quantum microprocessors based on our new architecture called the forwarding architecture. In the forwarding architecture, we improve the performance by utilizing multiple ALUs to conceal the inefficiency of bit-serial processing. The key components of the datapath are a register file and cascaded ALUs. We have designed the register file to hold four bit-serial data with two read ports and one write port. In each ALU, we have implemented six functionalities: addition, subtraction, logical AND, OR and Exclusive OR operations, and comparison with zero. We have tested the register file and the ALU using high-speed on-chip testing, and confirmed the correct operations up to 18GHz and 23GHz, respectively. [Copyright &y& Elsevier]

We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology, in the microprocessor designed here, called CORE1α6, a simple bit-serial architecture with seven instructions was employed. In the CORE1α6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1α6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1Ξ6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS). [ABSTRACT FROM AUTHOR]