127 results on '"Yang, Tahone"'
Search Results
2. PMOS junction optimization for 3D NAND FLASH memory with CMOS under array
3. A Case of Plasma-Induced Film Breakdown in 3D NAND BEOL Dielectric Etch
4. The Constraint Artificial-Intelligence Assisted Method for Etching Structure Optimization
5. Improvement of cell reliability by floating gate implantation on 1Xnm NAND flash memory
6. Post-Etch Yield Killer Defects in 3D NAND High Aspect Ratio Etching Process
7. Common Source Line-to-Word Line Short Improvement by Eliminating SLT Sidewall Notch in 3D NAND Deep Trench Patterning
8. Properties of N-rich Silicon Nitride Film Deposited by Plasma-Enhanced Atomic Layer Deposition
9. Machine learning Assists on High Aspect Ratio Slit Trench Etching in 3D NAND
10. Improvement of Twisting and Line-Edge Roughness of 3D NAND Deep Trench Etching on Yield Enhancement : AEPM: Advanced Equipment Processes and Materials
11. Study of charge trapping characteristics of SONOS with various trapping layers using gate-sensing and channel-sensing (GSCS) method
12. Improvement of Multi-Lines Bridge Defect Classification by Hierarchical Architecture in Artificial Intelligence Automatic Defect Classification
13. CMP Process Optimization Engineering by Machine Learning
14. Study of Plasma Ash Rate Enhancement by Machine Learning Models for TAT Improvement
15. Width Walk Control in 3D NAND Staircase Structure Etching
16. CMP Process Optimization Engineering by Machine Learning
17. Improvement of Multi-lines bridge Defect Classification by Hierarchical Architecture in Artificial Intelligence Automatic Defect Classification
18. Impact of Asymmetric Memory Hole Profile on Silicon Selective Epitaxial Growth in 3D NAND Memory : AEPM: Advanced Equipment Processes and Materials
19. Oval-Shaped OP-Layer Hole Etching: Shape Deformation, Local Arcing, and Hole Bridging Improvements
20. Process Optimization of Contact Module in NOR Flash Using High Resolution e-Beam Inspection
21. Verification of Systematic Defects Using e-Beam Defect Review System
22. Tungsten Gate Replacement Process Optimization in 3D NAND Memory
23. Pre-Epitaxial Plasma Etch Treatment for the Selective Epitaxial Growth of Silicon in High Aspect Ratio 3D NAND Memory
24. Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching
25. A Discussion of Dielectric Film Deformation by E-Beam Energy
26. Asymmetric etching profile control during high aspect ratio Plasma etch
27. Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization
28. A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability
29. ANYSYS chip-level and wafer-level simulation on semiconductor process development — Yu-Chih Chang
30. Reduction of wafer arcing during high aspect ratio etching
31. Tungsten corrosion and recess improvement by feasible slurry and clean chemical in WCMP process
32. Investigation of Floating Gate Implantation Effect on 1Xnm NAND FLASH
33. Thermal Stability of Cobalt Silicide on Polysilicon Implanted with Germanium
34. Pattern dependent plasma charging effect in high aspect ratio 3D NAND architecture
35. Novel hybrid 3D NAND flash memory containing vertical-gate and gate-all-around structures
36. A case study on severe yield loss caused by wafer arcing in BEOL manufacturing
37. Wafer topology effect on the etching saturation behaviors in NF3/NH3 remote plasmas
38. The new methodology of contact process window vericification
39. Capacity simulation by cellular automation in endura platform.
40. Trapping-free string select transistors and ground select transistors for Vg-type 3D NAND Flash memory
41. Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout — Kuang-Wei Chen.
42. Capacitance density and breakdown voltage improvement by optimizing the PECVD dielectric film characteristics in metal insulator metal capacitors-Chin-Tsan Yeh.
43. Advanced high accuracy scanning electron microscopy review methodology by virtual defect — Yiting Kuo.
44. Increasing VG-type 3D NAND flash cell density by using ultra-thin poly-silicon channels
45. Etched Profile Control of the Multi-Layer Oxide/Poly-Si Stack Using Pulsed Plasma for 3D VG NAND Application
46. A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts
47. Advanced process control of effective field height in a single wafer spin cleaning tool.
48. Dark field inspection technique on poly-silicon CMP process
49. The application of e beam inspection on 3D NAND flash
50. Sensitivities improvement by utilizing dark mode of bright filed inspection
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.