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In this paper, on the basis of analysing existing schedule message passing mechanism of Belief Propagation (BP) iterative algorithm, we propose a Belief Propagation iterative algorithm based on Dynamic Schedule Row Message Passing (DS-RMP). This algorithm optimizes the update mode of the check node message in the iteration, reduce the imbalance of check nodes' confidence degree in the original algorithm, and promote the efficiency of message passing. The simulation results indicate that, compared with the existing Belief Propagation algorithm, the Belief Propagation iterative algorithm not only reduces the average number of iterations, but also improves the bit error rate performance effectively.

This paper proposes a new belief propagation algorithm to reduce the computational complexity of Low Density Parity Check codes. In the iterative process of the proposed algorithm, an exponential model is adopted to segmental approximate the hyperbolic tangent function. In addition, two kinds of nonlinear operations are simplified into one nonlinear operation. Simulations reveal that this proposed decoding algorithm can reduce the computational complexity of decoding algorithm with a minimal loss of performance.

This paper introduces an IP core generator software use to generate ROM compressed DDS circuit block for wireless communication system based on linear interpolation DDS architecture. The generated DDS core circuit can effectively reduced waveform ROM size with various output data and frequency turning word bit width configuration. The synthesis result of generated cores on low cost FPGA platform can also support high-speed working clock frequency.

A general folded encoding structure for multi-rate quasi-cyclic LDPC codes is proposed in this paper to implement LDPC encoder with the advantages of few resources consumption, adjustable parallelism and high coding rate. For the quasi-cyclic LDPC codes mentioned in this paper, folded encoding structure can provide high coding rate and save 66% of the resources compared with the traditional encoding structure.

Raptor was valued and welcome in the field of broadcast and internet application, because it possesses properties of rateless, linear time with encoding and decoding, and applicability to erasure channel especially. For the most part of the applications, real time was generally required. Hereby, delay should be taken into consideration in the design and realization of a system. Channel encoding and decoding speed will also influence the size of delay finally, so the speed of Raptor encoding and decoding is worth to study and improve. This paper adopts several methods to optimize Raptor encoding and decoding in software realization, and we get a satisfactory result with improved speed of encoding and decoding.

This paper presents a symbol-by-symbol decoding algorithm of 3GPP MBMS Raptor. We redefine the initial matrix of 3GPP MBMS Raptor, and add some ancillary information to help make up for destruction of linear relationship in matrix caused by advanced Gauss elimination in 3GPP MBMS Raptor. So we can realize a correct decoding by symbolby- symbol, while 3GPP can not. The proposed algorithm is adapted to an erasure channel with large symbols, low code rate, big time delay or high error probability , and it can greatly improve decoding efficiency.

This paper presents an improved decoding algorithm for raptor codes in 3GPP MBMS. The algorithm has linear time decoding performance and solves the problem that the existing technology can not realize incremental decoding with the receiving symbols. In scheme of 3GPP MBMS, once the decoding fails, it must restart the decoding process. The algorithm we proposed can continue decoding until it reaches a successful decoding. And it avoids the most complex and time-consuming processing in the course of decoding, therefore it improves the efficiency of decoding.

This paper proposes a FPGA design of variable parameter interleaver based on the time-domain convolutional interleaver. Synchronous Dynamic Random Access Memory (SDRAM) is adopted in the design. According to different interleave-depth and configuration parameters, the memory of SDRAM is assigned dynamically. The result of the simulation is shown at the end of the paper.