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Entering the 5G era, the hardware design of low-density parity-check (LDPC) codes under the new standard has increasingly higher requirements on throughput. According to the geometric characteristics of the check matrices of the quasi-cyclicQC) LDCP codes under the CCSDS standard, this paper designs a layered dynamic normalized minimum sum algorithm(LDNMSA) under the pre-termination decoding based on de-layering scheme. The check matrix structure of this code is easy for hardware design and the storage resource consumption is low. The approximate replacement of the minimum sum algorithm(MSA) reduces the computational complexity of the check node update process. The determination of correction factors and inter-layer deletion thresholds through computer simulation improves the decoding performance and the speed of a single iteration, and adopt the layered scheduling scheme with optimized update order reduces the number of iterations required for decoding. Experimental results show that when the bit error rate(BER) is 10-5, the designed algorithm has a gain of approximately 0.5 dB compared to the MSA. The speed and calculation amounts to a single iteration are much lower than the log-likelihood-ratio(LLR) belief propagation(BP) algorithm and the performance is only less than 0.1dB.

In order to improve the accuracy of general target detection by the surveillance camera in the monitoring area, an improved SSD model named DC-SSD that integrates the deformable convolution network was proposed. This model is based on the SSD convolutional neural network model, and the idea of deformable convolution is used for reference. The deformable convolution module is added into the three high level convolution modules of SSD to make the sampling point position of the high level convolution kernel adaptively change according to the image content, so as to adapt to the geometric deformation of different objects such as shape and size. In the open source neural network framework Caffe, DC-SSD was tested with PASCAL VOC 2007 (train+val) as the training set and PASCAL VOC 2007 (test) as the test set. Under the same training and test conditions, the mAP of DC-SSD reached 72.0%, 4.0% higher than the original SSD model, and the detection frame rate reached 39fps. Experimental results show that DC-SSD model can effectively improve the accuracy of universal target detection and meet the real-time requirements.

The flow noise is produced due to fluid structure interaction and gas-liquid interaction, Flow noise signal contains a lot of information of the two-phase flow, such as flow type, phase holdup, velocity and so on, The detection and analysis of flow noise are mostly in the study of gas-solid two-phase flow, It has not been reported in gas-liquid two-phase flow research, In this paper, acoustic emission measurement technique combined with fast Fourier transform (FFT) is used to detect the acoustic signal of the gas liquid two phase flow, a new designed porous plate is installed in the vertical flow pipeline, A large number of experiments were carried out in the multiphase flow experimental facility at Hebei University. The approximate relationship between the peak frequency distribution of noise signal and the gas flow rate is obtained by measuring the peak position of the different gas flow rates under the slug flow condition. A preliminary method for estimating gas flow is proposed, which provides a new idea for the analysis of gas-liquid two-phase flow noise signal extraction of characteristic parameters of two-phase flow.

This paper presents the design and fabrication of an etched implant junction termination extension (JTE) for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.