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Hard drives featuring sliders with active flying-height (FH) control using thermal expansion of a heating element have been recently introduced in products. This approach allows to actively compensate for static FH variations and achieves sub-3-nm clearance during read/write operation. This paper describes a nonlinear numerical model of a perpendicular magnetic recording head for accurate simulation of pole-tip protrusions and their effect on FH change under various conditions, such as at an elevated drive temperature, with the heater activated or during write operation. The model integrates an electrical-thermomechanical finite-element model of slider and a full air-bearing solver, and includes lapped pole-tip recession and slider/disk deformation due to air-bearing pressure. We are able to predict key parameters that are not easily measurable (e.g., minimum/reader/writer FH, different protrusion profiles for ambient temperature, heater actuation, and during writing). We also present novel experimental methods for measuring protrusion and clearance delta profiles with angstrom-level resolution. The modeling results are compared to experimental data under various test conditions showing excellent agreement. From this method, we are able to quickly evaluate and optimize different heater, head, and ABS designs.

Perpendicular recording technology has become the main stream for 130 Gb/in2 HDD products. In this paper, challenges in perpendicular write head are discussed. Design tradeoffs and concerns of narrow-track single-pole heads, trailing shield heads, floating TS heads, and wrapped-around-shield (WAS) heads are discussed. Experimental data show that WAS heads provide good narrow track and high linear density performance. An areal density of 343 Gb/in2 has been achieved at a very aggressive magnetic spacing condition

Leakage current is of great concern for designs in nanometer technologies. In 90- and 65-nm technologies, subthreshold leakage current dominates total leakage current. For a typical ASIC circuit running at several hundred megahertz frequencies, the subthreshold leakage power can be as high as 60% of total power. An important method for minimizing power in ASIC libraries is reducing leakage current. In this article, a complete automated leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed. Optimization results show that there is ~30% leakage current reduction with a few percent active area and delay increase. There is increase in dynamic power, but the net total power reduction is significant. A uniform increase of 10% in gate length results in ~35% leakage reduction at the cost of ~12% delay degradation. The total cell area changes are minimal in both cases. The optimization flow begins with SPICE net lists from an existing library, optimizes leakage currents subject to performance metrics and active area increase constraints, and finishes with new layout generation and characterization. Investigations indicate that the leakage optimization has little impact on cell noise margin and layout parasitic modifications do not affect optimization results. The efficient automatic layout-to-layout cell leakage optimization flow is most suitable for leakage minimization and library migration for 90- and 65-nm ASIC libraries. Future work includes applying the flow to situations where layout-dependent DFM and process variation objective functions are also optimized

Two hydrodynamic models for a non-parabolic band structure are proposed in order to obtain closed sets of the first four moment equations derived from the Boltzmann transport equation. Instead of using the Fourier-law heat flux to determine the energy flux and to close the first three moment equations as applied to the conventional hydrodynamic model, the energy flux is solved directly from the third-order moment equation. The physical quantities introduced in the third-order moment equation are expressed in terms of the lower-order moments and the average parameters associated with the random velocity. To close the third-order moment equation, the average parameters related to the random velocity are assumed to be energy dependent. Transport results for a submicrometre silicon -n- diode obtained from the proposed four-moment hydrodynamic models, compared with those from Monte Carlo simulations and from three-moment hydrodynamic models, are studied in detail.

The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (~ 10% pushout versus RC delay) and noise (~2timesRC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add ~ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales

The common assumptions for closure of the first three moment equations with non-parabolic band structure have led to many inconsistencies associated with the electron temperature, effective mass and heat flux. The assumptions are involved in the heat flux based on the Fourier law and in the electron temperature determined from the average kinetic and drift energies. The inconsistencies resulting from these assumptions are studied and illustrated for electrons in silicon with a non-parabolic energy band. A simple alternative by means of which to avoid the inconsistent assumptions and to truncate the hierarchy of the hydrodynamic equations with non-parabolic band structure is proposed. Instead of using the Fourier-law heat flux to close the hydrodynamic equations, the energy flux is separated into fluxes carried by average and random velocities. The proposed model and a Fourier-law-based hydrodynamic model, together with the Monte Carlo method, are applied to a silicon sub-micrometre - n - diode with a non-parabolic band at various applied voltages. Effects on electron transport in the sub-micrometre device resulting from the assumptions of the Fourier-law heat flux and the electron temperature determined from the average kinetic and drift energies are investigated.

An experimental technique has been developed for studying the write bubble created by the thin film recording heads. From the measurements of the write bubble size, we can estimate the write field magnitude and the write field gradient at the write bubble boundaries. Using the same experimental setup, we can also study the write field high frequency characteristics.

This paper presents a simulation framework for reliability analysis of circuits in the SPICE environment. The framework incorporates the degradation of physical parameters such as threshold voltage (Vtp) into circuit simulation and enables the design of highly reliable circuits. The parameter degradation is based on the numerical solution for the reaction-diffusion (R-D) mechanism, which is a general model applicable to various reliability effects such as NBTI, HCI, NCS, and SEE. In particular, the accuracy and efficiency of this method was verified for NBTI degradation with 130nm experimental and simulation data over a wide range of stress voltages and temperature. The model also accurately captures the dependence of NBTI on multiple diffusion species (H/H2), key process (Vth, tox) and environmental parameters (VDD, temperature). The circuit level performance of this method is verified with silicon data from ring-oscillator circuit. We also investigated the predicted impact of NBTI on representative digital circuits

Quantitative interpretation of a magnetic force microscopy (MFM) image usually requires detailed knowledge of the magnetization configuration of the sensing tip. Here, we demonstrated a technique that converts the obtained raw MFM image into the magnetic pole density distribution without explicitly knowing the tip magnetization orientation. By creating an approximate point source of magnetic poles in the same sample imaged, the impulse response function of the MFM tip is obtained for deconvolution of a raw image in the Fourier space. Experimental demonstrations with various tip magnetization orientations were performed on recorded magnetic transitions in a thin film longitudinal medium.

Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include inter-and intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various RC structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.

On-chip inductance impact on signal integrity, complicated by process variations, becomes challenging for global interconnects in nanometer designs. Simulation and analysis of on-chip buses are presented for the impact of inductance in the presence of process variations. Results show that in 90nm technology there is significant inductive impact on max-timing (/spl sim/9% push-out vs. RC delay) and noise (/spl sim/2/spl times/ RC noise). Device and interconnect variations add /spl sim/4% into RLC max-timing impact, while their impact on RLC signal noise is nonappreciable.

Dummy fills are being extensively used to enhance CMP planarity. However presence of these fills can have a significant impact on the values of interconnect capacitances. Accurate capacitance extraction accounting for these dummies is CPU intensive and cumbersome. For one, there are typically hundreds to thousands of dummy fills in a small layout region, which stress the general purpose capacitance extractor. Second, since these dummy fills are not introduced by the designers, it is of no interest for them to see the capacitances to dummy fills in the extraction reports; they are interested in equivalent capacitances associated with signal power and ground nets. Hence extracting equivalent capacitances across nets of interest in the presence of large number of dummy fills is an important and challenging problem. We present a novel extension to the widely popular Monte-Carlo capacitance extraction technique. Our extension handles the dummy fills efficiently. We demonstrate the accuracy and scalability of our approach by two methods: (i) classical and golden technique of finding equivalent interconnect capacitances by eliminating dummy fills through the network reduction method and (ii) comparing extracted capacitances with measurement data from a test chip.

The on-chip inductance impact on signal integrity has been a problem for designs in deep-submicron technologies. The impact increases clock skew, max-timing and noise levels of bus signals. In this paper, circuit macro-models are bench-marked against test chip measurement in a 90 nm technology. Circuit simulations show the inductive impact on clock skew (e.g., 1lps in 2GHz clock frequency), signal delay (e.g., 11% max-timing push-out) and noise levels (e.g., 13% VDD). In addition, the inductive impact on signal integrity in the presence of process variations is evaluated. Finally, inductive impact in 65nm and 45 nm technologies is simulated, which indicates that the inductance impact will not diminish as technology scales.

The erase band resulting from edge overwrite has been studied using magnetic force microscopy. Utilizing image processing techniques, we developed a method to accurately measure the width of the edge erase band. In this paper, we focus on the study of MR/thin film head recording. Our experimental results show the erase band width is strongly dependent on the relative phase of the transitions in the old and new tracks at low bit densities. As the recording density is increased, the erase band width increases and becomes independent of the phase change. The erase band width observed ranges from 0 to 0.7 /spl mu/m for a typical MR/thin film head with 4 /spl mu/m wide trailing pole.

This paper presents a magnetic force microscopy (MFM) study on recording and edge overwrite in a keepered perpendicular thin film medium with a pole-tip head which is in-contact with the disk surface during the recording. The MFM image of a single recorded track shows that the edge of the recorded track is well defined by transition overshoot at track edges. The images of edge overwrite patterns show that at track edges, there is no separation between the newly recorded and residual previous tracks. It is argued that the sharp track edges and lack of edge erase band in perpendicular single pole head recording can be advantageous as well as disadvantageous depending on system and track serving designs. >

In this paper, track edge overwrite characteristics in planar isotropic longitudinal thin film media were studied by direct magnetic force microscopy imaging of the edge overwrite patterns. It is found that edge erasure strongly depends on the phase difference between the transitions in the overwriting and overwritten tracks at track edges. If the transitions in the adjacent tracks are in-phase, there exists no edge erase band and transitions in the adjacent tracks area connected in the side written band. Edge erasure occurs when there exist sufficient large phase differences between the transitions in the adjacent tracks. This new understanding of phase dependence of edge overwrite could have strong impact to the system design in terms of consideration for both PES and recording off-track performance. >

The switching fields of individual iron particles used in magnetic recording have been measured using a Magnetic Force Microscopy (MFM) technique. It is found that as the particle diameters increase from 20 nm to 70 nm, the easy axis switching fields decrease from 2850 Oe to 1800 Oe. As the field angle increases, the switching fields increase monotonically and approach 5000 Oe at particle hard axis. A head-on multidomain state was observed after a particle had been magnetized by a 10K Oe field along hard axis. Micromagnetic calculations based on a chain of spheres model have been performed to simulate the switching mode which gives good agreement with experimental data. It is concluded that the switching process is best described by a fanning-like mode at small field angles. >

An in situ method of measuring the magnetoresistive (MR) head transfer curves directly on a spin-stand tester is presented. We define the MR head transfer curve as the MR output voltage amplitude versus the magnitude of magnetic flux arising from transitions. To obtain adjustable transition flux magnitude on a spin stand tester, isolated transitions are recorded with write current level varied from zero to saturation. Adjusting the write current level varies the magnetization level difference across a recorded transition, thereby varying the magnetic flux generated by the transitions. At each write current level, the magnitude of the magnetic flux arising from the recorded transitions is measured by the thin film (TF) writer whose response is linear with respect to magnetic flux. At the same time, the MR head output is also measured. By plotting the MR head output as a function of the TF head output, a transfer curve is obtained. The experiments were performed using a film disk (Disk A) of MrT=2 memu/cm2,...

Nonlinear partial erasure and the supralinear noise enhancement at high recording densities are the two critical factors limiting linear recording density in longitudinal thin‐film disk media. In this paper, via spin stand measurements, nonlinear partial erasure was studied in terms of medium magnetic parameters, such as MrT, Hc and orientation ratio, and recording conditions, such as fly height and write current optimization. It is found that the nonlinear partial erasure and the supralinear noise increase always occur at the same recording density, independent of media magnetic properties and recording condition.

The magnetic force microscopy (MFM) technique is used to investigate the writing properties of a set of thin‐film heads with track widths ranging from 2 to 0.5 μm. MFM images show that track edge percolation occurs at lower densities than on‐track intertransition percolation. Track edge percolation results in track edge fluctuations and effective track width reduction. As the head track width is reduced to the near‐micron or submicron ranges, the track edges become dominant portions of the track and consequently cause severe degradation of the recording tracks. Track edge percolation is caused by a poor edge field gradient and is possibly enhanced by pole tip corner saturation. In order to achieve high‐density narrow track recording, high moment writing heads become necessary.