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Approximate computing is tentatively applied in some digital signal processing applications which have an inherent tolerance for erroneous computing results. The approximate arithmetic blocks are utilized in them to improve the electrical performance of these circuits. Multiplier is one of the fundamental units in computer arithmetic blocks. Moreover, the 4–2 compressors are widely employed in the parallel multipliers to accelerate the compression process of partial products. In this brief, three novel approximate 4–2 compressors are proposed and utilized in 8-bit multipliers. Meanwhile, an error-correcting module (ECM) is presented to promote the error performance of approximate multiplier with the proposed 4–2 compressors. In this brief, the number of the approximate 4–2 compressor’s outputs is innovatively reduced to one, which brings further improvements in the energy-efficiency. Compared with the exact 4–2 compressors, the simulation results indicate that the proposed approximate compressors UCAC1, UCAC2, UCAC3 achieve 24.76%, 51.43%, and 66.67% reduction in delay, 71.76%, 83.06%, and 93.28% reduction in power and 54.02%, 79.32%, and 93.10% reduction in area, respectively. And the utilization of these proposed compressors in 8-bit multipliers brings 49.29% reduction of power consumption on average.

In order to gain substantial circuit performance improvement in terms of power, speed and area cost, approximate computing is ideally applied in many error-resilient DSP and multimedia applications by relaxing the requirements of exact computation. Fixed-width multipliers are intensively used in those applications, which makes them a good demonstration for approximation through dynamic range reduction. In this paper, a probabilistic prediction based fixed-width Booth multiplier has been proposed. The error compensation function is derived from the probabilistic analysis on the partial products obtained from Booth encoding. By slightly modifying the partial product array with dedicated partitioning, a simple compensation circuit is thus formulated. Compared with the previous works, the proposed design exhibits the best performance-accuracy tradeoff. It achieves at least 27% reduction on the area-energy-delay-error product compared with the other multipliers among various operand lengths. Additionally, the evaluation on 2-Dimensional discrete cosine transform (DCT) circuits indicates that our proposed fixed-width Booth multiplier is applicable for lossy applications with a considerable reduction on hardware expenses and power dissipation while maintaining decent output quality.

This paper presents a novel 10T static random access memory (SRAM) cell for ultra-low voltage operations. A built-in read assist scheme is proposed to eliminate the read disturb issue. It significantly improves the read stability. In addition, a data-aware write assist technique is also proposed to enhance the write ability of the SRAM cell. Simulations are performed in a 40-nm standard CMOS technology at a 0.4V supply voltage. The experimental results indicate that the proposed 10T SRAM cell exhibits the best write margin and large read static noise margin. When compared with the conventional 6T SRAM cell, it achieves 2.95× larger read static noise margin and 1.93× higher write margin.

Digital Multiplier is a fundamental component in many digital signal processing (DSP) systems, which takes up the most part of the computational resources. As many DSP applications have an inherent tolerance for inexact computations, approximate multiplication is considered as an appropriate substitution to obtain energy-performance-accuracy tradeoffs, especially in those applications that require high energy-efficiency in computing. Meanwhile, reducing the supply voltage is proved to be an efficient way to further lower the total energy consumption. In this paper, a novel approximate 4-2 compressor and its circuit implementation is proposed for error-resilient multiplication with a low supply voltage. Simulation results indicate that the approximate multiplier with our proposed approximate 4-2 compressor consumes the least energy per operation with the same computational accuracy when compared with other multipliers for the operand length of 8 bits. It achieves 26.7% reduction on energy-delay product (EDP) when compared with the exact multiplication.

Fixed-width multipliers are widely used in multimedia and digital signal processing systems which are desirable to utilize a fixed operand length. In order to maintain the required computation accuracy, the truncation error has to be well compensated with minimum overhead. Recently, modified Booth algorithm has been increasingly employed in the fixed-width multiplier design so as to contribute further to the speedup and logic reduction. In this paper, a probabilistic prediction formula is proposed by taking the expected value of truncated partial products into account, which makes a zero mean error compensation. A simple compensation circuit is derived accordingly and plugged in to a fixed-width Booth multiplier design. Simulation results show that our proposed multiplier exhibits the best mean error and maximum absolute error when compared with existing designs. It achieves at least 20.82% energy reduction with 22.14% less silicon area with operand lengths of 8, 12, and 16 bits.

In recent years, approximate computing has been widely used in low power digital circuits design. As it incurs error in computation, there are always tradeoffs between hardware performances and computational accuracy. Thus, the circuit implementation can vary from applications to applications and even in the same application, which makes difficult to evaluate the design efficiency in terms of delay, power and computational accuracy. In this paper, approximate efficiency (AE) is proposed as a new design metric dedicated in energy-efficient approximate computation. An automatic pruning approach is presented based on quickly estimated AE, which leads to an efficient approximate circuit design and a significant reduction on energy dissipation. A 32-bit adder is demonstrated using proposed method and compared with other approximation methods, including direct truncation and significance-activity pruning method. For legitimate comparisons, same computational accuracy is obtained for all imprecise adders. The simulation results show that assessed on mean absolute error, the proposed adder outperforms the others. With given error threshold, it can reach 31.15% energy-delay-product reduction compared with the most competitive contender.