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In this paper, we present a descriptive analysis of a performance index, ΔVDIBLSS/(Ion/Ioff), used for performance monitoring. Scaled nand p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified ΔVDIBL/(Ion/Ioff) for monitoring the electrical characteristics of MOSFET devices is proposed due to the “quick measurements” required in the last step of the semiconductor manufacturing process. ΔVDIBL/(Ion/Ioff) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for ΔVDIBL/(Ion/Ioff) is much quicker than for ΔVDIBLSS/(Ion/Ioff), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as Ion/Ioff and intrinsic gain, gm × ro, are reported using ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff). ΔVDIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since Ion/Ioff is a sensitive function of threshold voltage, the estimates of the ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are hard to achieve. However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure.

This paper aims to investigate the recently proposed figure of merit, $\Delta V_{\mathrm{ DIBLSS}} /(I_{\mathrm{ on}} /I_{\mathrm{ off}})$ , in detail. Experimental results show that $\Delta V_{\mathrm{ DIBLSS}} /(I_{\mathrm{ on}} /I_{\mathrm{ off}})$ represents the index of device immunity to short-channel effects in bulk FinFETs. The value of its numerator, $\Delta V_{\mathrm{ DIBLSS}}$ , accounts for the drain-induced barrier lowering and subthreshold swing. The value of its denominator, $I_{\mathrm{ on}} /I_{\mathrm{ off}}$ , accounts for the transistor performance in transitioning between on and off states. Small $\Delta V_{\mathrm{ DIBLSS}}$ and large $I_{\mathrm{ on}} /I_{\mathrm{ off}}$ are desirable, representing the improved gate control over the channel potential. We found that both $\Delta V_{\mathrm{ DIBL}}$ and $\Delta V_{\mathrm{ SS}}$ values are more correlated with the drain off-state current, $I_{\mathrm{ off}}$ , than they are with the drain on-state current, $I_{\mathrm{ on}}$ . A high-performance FinFET device exhibits $\Delta V_{\mathrm{ DIBLSS}}$ of about 100 mV and $I_{\mathrm{ on}}/I_{\mathrm{ off}}$ of about ${\mathrm{ 1}}\times {\mathrm{ 10}}^{\mathrm{ 6}}$ . Thus, $\Delta V_{\mathrm{ DIBLSS}} /(I_{\mathrm{ on}} /I_{\mathrm{ off}})$ in a high-performance FinFET device is expected to be around ${\mathrm{ 1}}\times {\mathrm{ 10}}^{-{\mathrm{ 4}}}$ mV. Using this figure of merit, along with the verification using conventional parameters such as $\Delta V_{\mathrm{ DIBLSS}}$ and $I_{\mathrm{ on}} /I_{\mathrm{ off}}$ , the proposed device shows better electrical characteristics than that in our previous work due to the optimized process conditions implemented.

This paper aims to investigate the device parameters, including drain-induced barrier lowering (DIBL), subthreshold swing (SS), and saturation drive current, $I_{\rm d,{\mathrm{ sat}}} $ , of bulk-Si n-channel FinFET devices (bulk n-FinFETs). The impact of lightly doped drain (LDD) process on the performance of bulk n-FinFETs is also examined in this paper. According to our measured data, excluding LDD in bulk n-FinFETs not only reduces mask costs but it also enables slightly better short-channel control compared to the inclusion of LDD. A new figure of merit, $\Delta V_{\mathrm{ DIBLSS}} /(I_{\rm d,{\mathrm{ sat}}} /I_{\rm sd,{\mathrm{ leak}}} )$ , is introduced for monitoring short-channel performance of bulk n-FinFETs, where $\Delta V_{\mathrm{ DIBLSS}} $ accounts for the DIBL and SS, and $I_{\rm sd,{\mathrm{ leak}}} $ is the source/drain subthreshold off-state leakage current.

In this paper, we for the first time demonstrate the analog performance of a block-oxide structure in polycrystalline silicon thin-film transistor with source/drain-tie and additional poly-Si body (BO-SDT-APSB TFT) experimentally and compared with the similar device with zero block-oxide structure (SDT-APSB TFT). The block-oxide in BOSDT-SDT-APSB TFT is fabricated to reduce the drain-induced barrier lowering and channel-length modulation. The source-drain tie and additional poly-silicon body region are fabricated in both devices to improve the device performance and reduce the self-heating effect. Experimental results show that the block-oxide structure can offer enhanced gate controllability over the channel, and the transconductance ( $g _{\rm m}$ ) of the BO-SDT-APSB TFT is therefore improved. In addition, although a higher drain conductance ( $g _{\rm d}$ ), implying a lower output resistance $r _{\rm o}$ , is observed for a BO-SDT-APSB TFT, the enhanced gm still helps to achieve the desired intrinsic voltage gain ( $A _{\rm v} = g _{\rm m} / g _{\rm d}$ ) behavior.

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

This paper presents an experimental comparison of the block-oxide (BO) source/drain-tied (SDT) (BOSDT) polycrystalline-silicon (poly-Si) thin-film transistor (poly-Si TFT) with additional poly-Si body (APSB) against the zero-BO (ZBO) SDT (ZBOSDT) poly-Si TFT with APSB. The APSB scheme is created when the isolation process takes place after annealing of the source/drain regions. The experimental results show the superior electrical characteristics of the BOSDT-APSB poly-Si TFT over the ZBOSDT-APSB poly-Si TFT. The BO scheme is indeed useful in reducing the source and drain charge sharing. Although the ZBOSDT-APSB poly-Si TFT exhibits worse electrical properties, the combination of a ZBO (a buried oxide layer only under the poly-Si body) with an APSB can still be used to keep diminishing the charge-sharing effect. Furthermore, both devices can increase the cooling capability through their source/drain-tied structure.

In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel STI-type body-connected FinFET with 45 nm gate length, for which the DC behaviour exhibits better ION-IOFF current ratio and improved gm performance when compared with a planar FinFET. The RF characteristics are carried out as functions of gate voltage (VG) and drain current (IDS) as well as the overdrive voltage (VOV). In addition, the total gate capacitance (Cgg) is also reported.

In this paper, we numerically explore electrical characteristics of a simple device called the π-shaped source/drain (π-S/D) MOS transistor. Some techniques such as Si/SiGe epitaxial growth and selective SiGe etch process are implemented for the fabrication of quasi-SOI devices with an S/D tie. More importantly, a new method presented here for fabricating π-S/D MOSFETs does not require any additional mask step due to self-alignment process being exploited. The isolation technique is carried out only after S/D annealing, resulting in only four extra process steps introduced in this new quasi-SOI technology. According to numerical simulations, the new π-S/D structure has better control on the short-channel and thermal effects compared with the conventional (conv.) π-S/D structure. Despite Miller capacitance sacrifice behaviour owing to the absence of the conv. isolation approach before gate definition, which causes an increase in the body area under the gate, NMOSFET intrinsic delay τ and cutoff frequency f...

In this work, we propose a novel transistor called dual-channel source/drain-tied (DCSDT) MOSFET. The process for producing the device employs the multiple epitaxial growths of SiGe/Si layers and selective SiGe removal to form the block oxide island (BOI) in this work. Due to the source/drain-tied scheme giving more pass way to dissipate generated heat, the both DC and RF/analog performance of the device are not seriously affected according to the numerical simulation results.

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

In this paper, we analyze the radio frequency (RF) performance for novel junctionless vertical MOSFETs (JLVMOS) with different thicknesses of silicon pillar (T Si = 5, 10 nm). In addition, a junctionless planar SOI MOSFET is also designed for the comparison in this work. According to the numerical simulations, the JLVMOS of T Si = 5 nm gets the highest in g m and g m/I DS, but the T Si = 10 nm one gets the highest in A VI. Moreover, due to the double-gate (DG) structure of the VMOS, it can increase the gate controllability over the channel region.

A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gate's ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., DIBL ang 90 mV/V and SS ang 100 mV/dec), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.

In this paper, the influence of block oxide width (WBO) variations on a newly designed 40-nm gate-length silicon-on-partial-insulator field-effect transistor with block oxide (bSPIFET) was demonstrated and characterized. By utilizing the block oxide (BO) enclosing the sidewall of the Si body, the charge sharing from the source/drain (S/D) regions for a bSPIFET can be significantly reduced. Essentially, because the BO is adopted for a bSPIFET, its ultrashort-channel characteristics are similar to an ultrathin-body silicon-on-insulator (UTBSOI), although it possesses a thicker S/D region than a UTBSOI. From the simulation tests, it was also found that although the wider BO can suppress the ultrashort-channel effects (USCEs), the drain ON-state current ION slightly decreases because certain areas of the S/D are occupied by BO. Despite this problem, the bSPIFET still exhibits a good USCE control and a high-drive current. In addition, the self-heating effects are also ameliorated as a result of the natural body-tied scheme.

One-transistor dynamic random access memory (1T-DRAM) thin-film transistor (TFT) could lead the revolution of system-on-panel application. However, no useful 1T-DRAM is fabricated on the polysilicon (poly-Si) thin film up to now. In this letter, we present a novel method to fabricate a smiling poly-Si TFT for 1T-DRAM applications. The experimental results show that the short-channel effects can be reduced because the smiling scheme is used to suppress the charge sharing and the source/drain-tied scheme can help to overcome the self-heating. Moreover, the device fabrication is fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology.

A novel single junction thin film solar cell structure ITO/p- a-Si:H /i1- a-Si:H/i2- μc-Si:H/n- μc-Si:H/ITO is studied with Silvaco TCAD tool in this paper. The simulation data predicts that the thickness of the maximum conversion efficiency is between 250–500nm. For the best efficiency, the intrinsic μc-Si:H layer is predicted between 1500–2500nm. The results indicate the conversion efficiency is higher than that of the conventional amorphous silicon solar cell 7.53% and 8.14% for the conventional microcrystalline solar cells. To compare with the nanocrystalline (nc-Si:H) heterojunction thin film solar cell, the conversion efficiency of the proposed structure is increased more than 21.92%.

In this work, we made a CIGS thin film solar cell with dual absorber layers which added an InGaP layer between buffer layer and CIGS layer. That is, the conventional structure of ZnO/CdS/CIGS/Mo becomes the structure of ZnO/CdS/InGaP/CIGS/Mo. And we translate the thickness and doping concentration of the additional InGaP absorber layer to find out critical parameter. Due to the presence of the additional 0.06 μm thick InGaP layer with acceptor concentration 2 × 1016 cm−3, the increased efficiency is observed. According to simulations, the wavelength of EQE in 0.3 μm ∼ 0.5 μm for our proposed CIGS solar cell is improved when compared with the conventional CIGS solar cell. And the conversion efficiency increased from 9.27% to 11.18%.

In this paper, we propose a new block-oxide source/drain-tied (BOSDT) poly-Si TFT in which the additional poly-Si body (APSB) is created when the device isolation process is done after the source/drain implantation and dopant activation. For the first time, according to our results, the APSB is confirmed to have the ability to circumvent the SCEs and leakage current. Furthermore, the output characteristics of a poly-Si TFT with APSB demonstrate that the self-heating is absent because the SDT structure is presented. Although the excellent performance expected theoretically (SCEs, leakage current, self-heating) cannot be achieved well, the intrinsic functions are still present. And, more importantly, the APSB scheme can be realized through the simple isolation-last process. It is believed that after the process and the structure geometry are optimized, the values of the BOSDT-APSB could be obtained.

In this paper we present for the first time a new GaP/a-Si:H/bulkSi solar cell. According to Silvaco TACD simulations, the GaP/a-Si:H/bulkSi solar cell has a high short-circuit current due to the downward bandgap bending. Moreover, a high doping a-Si:H can lead to a upward bandgap bending, resulting in a high open-circuit voltage. Although the GaP/a-Si:H/bulkSi solar cell has a low short-circuit current, a compensation can be achieved by the cell area or texture techniques. Furthermore, an optimized open-circuit voltage of 0.758V is also achieved.

In this paper, we focus on the electrical characteristics of the partially insulating oxide (PiOX) junctionless vertical MOSFET (JLVFET) and PiOX junction vertical MOSFET (JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, in whereas the PiOX JVFET needs an S/D implant. But, according to simulation results, we find out that the PiOX JVFET exhibits desired characteristics which are similar to those of the PiOX JLVFET. This means that the subthreshold swing and drain-induced barrier lowering, can be almost the same for both devices. Additionally, the high S/D doping presented in the PiOX JVFET helps reduce the parasitic S/D resistance, resulting in an enhanced current drive. In other words, it is believed that the PiOX JVFET is still considered as a candidate for future CMOS scaling.

In this letter, we focus on the electrical characteristics of the Partially insulating oxide Junctionless Vertical MOSFET (Piox JLVFET) and Partially insulating oxide Junction Vertical MOSFET (Piox JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, whereas the PiOX JVFET needs an S/D implant. But, according to simulation results, we find out that the PiOX JVFET exhibits desired characteristics which are similar to those of the PiOX JLVFET. This means that the analog properties, such as gate transconductance (G m ), drain conductance (G d ) and intrinsic gain (A v ), can be almost the same for both devices. Additionally, the high S/D doping presented in the PiOX JVFET helps reduce the parasitic S/D resistance, resulting in an enhanced current drive. In other words, it is believed that based on the design requirements, the PiOX JVFET can still be considered as a candidate for future CMOS scaling.

In this paper, we present a simulation study of short-channel characteristics of self-aligned dual-channel source/drain-tied (SA-DCSDT) MOSFETs. Two compared devices are designed, namely, the normal SA-DCSDT MOSFET and the ultimate SA-DCSDT MOSFET. According to simulation results, the DC is used to obtain a high drain saturation current, the SDT is used to get improved thermal stability, and the BOX under S/D regions is used to reduce the drain off-state current. A physical explanation for these results is also presented.

In this paper, we propose a new fabrication method to form a polysilicon thin-film transistor with a smiling SiO 2 layer. The experimental results suggest that the short-channel effects can be significantly reduced because the trench oxide is utilized to block the drain electric field. Furthermore, the so-called S/D tie can help to overcome the self-hating for enhancing the thermal reliability. And the device fabrication process is fully compatible with current conventional CMOS technology.

In this paper, we investigate the important device characteristics of block oxide (BO) MOSFETs (bMOS), which are the BO length (L bo ) and the height (H bo ). According to the simulation results, the variation of L bo and H bo strongly affects the device characteristics, such as the sub-threshold swing, threshold voltage, on-state drain current (I on ), and the off-state drain current (I off ). This is because the variation of L bo and H bo changes both the areas of BO and source/drain (S/D) regions, resulting in a variation of increase or decrease in the p-n junction area between the S/D regions and silicon substrate.

In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both g m and g D of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed I DS . Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior than its counterpart. Thus, it can be proved that a junctionless poly-Si TFT is a good option for AMLCD and AMOLED Applications.

This paper presents a novel NMOS structure called two-embedded oxide (2EO) to replace the conventional PMOS transistor in a CMOS inverter. According to TCAD simulations, the 2EO is used to control the punch-through current to achieve the desired characteristics for a CMOS inverter. More importantly, compared with the conventional CMOS layout, due to the presence of two NMOS transistors to share the output contact, a reduction in mask-layout area (improved 59%) is observed. Compared with the EO, our proposed 2EO can reduce the static power consumption by 33%, for achieving a requirement of reduced static power consumption in a non-conventional CMOS.

In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better I ON -I OFF current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (V G ) and drain current (I D ) as well as the overdrive voltage (V OV ). In addition, the total gate capacitance (C gg ) is also reported.

In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the t PLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.

This study presents a new vertical MOSFET with recessed gate (RG). Based on the TCAD simulation results, our proposed VMOS structure can gain reduced parasitic capacitance (compared to the conventional VMOS, both C gd and C gs can be reduced about 12% and 38.78%, respectively at V Ds =1.0 V), improved drain saturation current, and free kink characteristics, in comparison to a conventional VMOS structure. Moreover, the short-channel characteristics of RGVMOS which is modified from the EGVMOS are still acceptable. Most importantly, the manipulation of fabricating this newly proposed structure is enhanced mainly owing to the semicircle gate scheme.

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same V ov as compared with the JTFT, its short-channel characteristics are worse and degraded. These results can be attributed to the fact that the major carriers in channel region for a JTFT make itself a barrier to carrier scattering, whereas, the JTFT does not have this problem, leading to get a high current drive. On the other hand, it may be owing to the grain boundary effects for a JLTFT to degrade its short-channel behavior. Fortunately, these results are still acceptable for scaled dimensions of TFTs.

A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR) is exhibited under the gate region thereby improving the device electrical characteristics and the subthreshold properties. Its DIBL and subthreshold swing becomes better compared with its counterpart because the lower source/drain resistance and the wider device effective-width can be obtained. For the same reason, this new device shows a higher transconductance (G M ) behavior. And its drain conductance (G D ) also maintains a good electrical performance with no kink effect compared with the planar-type single top-gate FinFET. With ABR under the gate layer, the lattice temperature is decreased and the thermal instability is alleviated compared with its counterpart.

In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (g m ), high cut-off frequency (ƒ T ), and high transconductance generation factor (g m /I d ) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.

This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel effects significantly. More importantly, the single-crystal Si source/drain is achieved by the incorporation of the existing partially-insulating techniques into a NBO technology. The simulation results show that using the additional body regions which are the product of the ILP can help NBO MOSFETs achieve the ITRS roadmap requirements for high-performance applications.

In this paper, a novel non-classical CMOS inverter with simple process and high integration density is proposed, which is composed of a junctionless NMOSFET and a gated N−-N-N+ transistor for driver and load, respectively. Also, the gated N−-N-N+ transistor performance is also investigated. Based on the numerical simulations, we find out that the carrier mobility of the gated N−-N-N+ transistor is enhanced significantly. Besides, the layout area of the novel CMOS inverter are reduced more than 46.1% because of its unique shared contacting for output node, when compared with the conventional layout area.

We present a reliability analysis of a new vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM applications. The proposed 1T-DRAM device can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved by about 95% when compared to the planer bMPI 1T-DRAM. Owing to the double-gate structure, vertical bMPI has great gate controllability over the channel region; hence, it can reduce the short-channel effects (SCEs) and enhance the current drive. And the VbMPI 1T-DRAM cell can keep holes in nature body region, which leads to an increase in data retention time.

In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ∼ 60mV/dec, I on /I off ∼ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for JPTGV fabrication and it can be employed for use in deca-nanometer regime.

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed CLTFET compared with the conventional CTFET to verify its feasibility. The delay time is improved more than 29.5%. Additionally, due to its unique structure and the output node being shared by the load and the driver, the integration density of it can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout.