654 results on '"Yici Cai"'
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2. Static Probability Analysis Guided RTL Hardware Trojan Test Generation.
3. TransMarker: A Pure Vision Transformer for Facial Landmark Detection.
4. SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data.
5. McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.
6. An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network.
7. A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model.
8. Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks.
9. Look at Boundary: A Boundary-Aware Face Alignment Algorithm.
10. Electromigration Design Rule aware Global and Detailed Routing Algorithm.
11. A conflict-free approach for parallelizing SAT-based de-camouflaging attacks.
12. ASAX: Automatic security assertion extraction for detecting Hardware Trojans.
13. HLIFT: A high-level information flow tracking method for detecting hardware Trojans.
14. Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks.
15. An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack.
16. LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips.
17. Cell spreading optimization for force-directed global placers.
18. Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack.
19. Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans.
20. Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
21. Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks.
22. An Effective Power Grid Optimization Approach for the Electromigration Reliability.
23. TeenRead: An Adolescents Reading Recommendation System Towards Online Bibliotherapy.
24. McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework
25. Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.
26. MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.
27. Is the Secure IC camouflaging really secure?
28. An efficient framework for configurable RO PUF.
29. Sequence-pair-based placement and routing for flow-based microfluidic biochips.
30. Intelligent and kernelized placement: A survey
31. A survey on machine learning-based routing for VLSI physical design
32. SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.
33. Early stage real-time SoC power estimation using RTL instrumentation.
34. Fast synthesis of low power clock trees based on register clustering.
35. PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips.
36. RSMT construction algorithm based on Congestion-Oriented Flexibility.
37. Power supply noise aware evaluation framework for side channel attacks and countermeasures.
38. MCFRoute: a detailed router based on multi-commodity flow method.
39. A register clustering algorithm for low power clock tree synthesis.
40. Accurate prediction of detailed routing congestion using supervised data learning.
41. VFGR: A very fast parallel global router with accurate congestion modeling.
42. Time-domain performance bound analysis for analog and interconnect circuits considering process variations.
43. Fast vectorless power grid verification using maximum voltage drop location estimation.
44. Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips.
45. Analog routing considering min-area constraint.
46. A new splitting graph construction algorithm for SIAR router.
47. Selected inversion for vectorless power grid verification by exploiting locality.
48. A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification.
49. Performance bound and yield analysis for analog circuits under process variations.
50. Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.
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