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Generally, computer-science-oriented artificial neural networks (ANNs) and neuroscience-oriented spiking neural networks (SNNs) are two main approaches to develop brain-spired non von Neumann computing systems. The goal of exploring complex artificial intelligence (AI) systems demands general neuromorphic hardware platforms compatible with both of them. However, as a result of the obvious differences in their fundamental mathematical expression and coding scheme, many neuromorphic platforms or deep neural network (DNN) accelerators accommodate only one of them. This brief presents a reconfigurable scalable neuromorphic chip based on digital leaky integrate-and-fire (LIF) neuron model targeting low-cost large-scale systems. By unifying ANN and SNN paradigms within a LIF neuron framework with point-to-point (P2P) communication, the chip can accommodate most popular neural networks. The chip adopts distributed on-chip memory architecture with a capacity of 64K neurons and 64M synapses. It achieves a peak throughput of 12.29 GSOP/s at 1.2 V, 192MHz and peak energy efficiency of 2.64 pJ/SOP at 890 mV, 24MHz. The results of implementations of a spike-based spatio-temporal memory model and ternary-weight event-based convolutional neural networks (CNNs) demonstrate outstanding compatibility of the chip.

Event-based spiking neural network (SNN) has displayed a promising prospect to realize real-time, efficient and intelligent hardware platforms. Whereas great efforts are still being appealed to explore the possibility of introducing online learning abilities to neuromorphic systems. In this paper, a 28-nm CMOS neuromorphic processor is presented, fulfilling online learning by adopting counter and lookup table (LUT) based spike-timing-dependent plasticity (STDP) rule. Designed to work at high-precision scenarios, the presented processor integrates up to 1024 neurons and 256K signed 9-bit synapses. It also ensures chip array interconnection to fit large neural networks. Moreover, by utilizing the sparse property of spike events to minimize activity rate, the typical power consumption is further reduced to 3.348mW for training MNIST dataset.

Neuromorphic hardware platforms inspired by human brain have emerged as novel non von Neumann computing architectures. They were proved excellent platforms for spiking neural network (SNN) implementations. However, implementing artificial neural networks (ANNs) on existing neuromorphic hardware platforms is still a daunting task because of critical limitations on coding scheme, maximum of fan-in, and highest weight precision in them. In this paper, we introduce a neuromorphic processor developed for various neural networks implementations including ANNs and SNNs. We employ spatio-temporal coding scheme based on spike events. By combining low-precision dendrites, the chip can implement weight precision between 1 bit and 8 bits and scalable fan-in. The 3.66-mm2 chip fabricated in 28-nm CMOS with a maximum fan-in of 72 K per neuron demonstrates unprecedented compatibility with ANN applications compared to previously-proposed neuromorphic chips.

Recent years, spike-based neuron computing on scalable and event-based neuromorphic hardware has demonstrated impressive energy efficiency. In this paper, we propose a novel spiking scheme for 1-bit and 8-bit convolutional neural networks and a systematic mapping algorithm for their deployments on a digital neuromorphic ASIC, with which we can automatically partition input and output feature maps for a 1152*1024 crossbar computing element for a excellent resource efficiency. Experimental results on MNIST dataset show that we can achieve about 98.5% and 99.4% test accuracy for these two kinds of bitwidth networks respectively, while the chip can achieve nearly 863 and 174 images/sec real-time inference speed at 0.9 V, 252 MHz.

Binary neural networks (BNNs) - neural networks with binary {-1, +1} weights and activations at run-time, have attracted much attention in recent years, which drastically reduce resource requirement and power consumption with tolerable accuracy loss. While, spiking neural networks (SNNs) are designed as a brain-inspired computing model, which can be deployed on large-scale distributed and event-based neuromorphic hardware efficiently. To enable a conversion of above two, we develop a variant of BNNs which employ binary-valued {0, +1} activations and ternary-valued {-1, 0, +1} weights and achieve start-of-the-art classification accuracy across two standard vision datasets, even better than the previous proposals using BNNs or SNNs. Furtherly, we propose an effective configuration method for network deployment on our designed programmable neuro-synaptic system with only one timestep and milliwatt level power consumption.

The neuromorphic hardware with a non-von Neumann architecture has the advantage of highly-parallel and low-power. In this paper, a digital neuromorphic core with 1024 neurons, 1024 axons and a $1024\times 1024$ synaptic crossbar is designed, and the scalable network could be implemented based on the 2D mesh network on chip (NOC) architecture. The transformed deep spiking neural network (SNN) models can be mapped to our hardware directly, and show good application results. At the case of the full firing rate, the average power of a spike is 2.76E-08J, and for some image recognition tasks, the hardware power consumption is at the milliwatt level.