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This article suggests an increased, minimal 4-bit scaling factor based on FinFET. The HSPICE instrument is used to evaluate the multipliers premised on FinFETs. FinFETs are observed to consume 97% less strength than MOSFETs. Numerous condensers are proposed and built at 180nm innovation in this document, including 5:3, 10:4, 15:4, as well as 20:5 compressors. Further on, FinFET technology had been used to make the compressor There is also a comparison between delay and average power of 4-bit FINFET and 4-bit MOSFET. The delay and Power consumption for 4-bit Fin-FET by using AND gate and EX-OR gate are 0.139 ns, 0.54 μW, and 0.245ns, 1.975μW respectively. Both technologies’ concepts were simulated and their functionality compared. Thus, according to simulations, the compressors built in FinFET technology would work on less power than the conventional CMOS technology.

Sense amplifier is a key element of memory and a CMOS-based spin hybrid circuit. Magnetic tunnel junction (MTJ) is a key spintronic device used in spin-based memory and hybrid circuits. This paper presents a design of a voltage-controlled magnetic anisotropy MTJ-based sense amplifier (VCMA-SA) that offers better reliability, power efficiency and high-speed performance. MTJ switching between different resistive states in this paper takes place through the faster and energy-efficient voltage-controlled magnetic anisotropy (VCMA) scheme rather than the traditional spin-transfer torque (STT)-based magnetization switching. This paper demonstrates that SA based on VCMA-MTJ switching is faster, reliable and more energy-efficient compared with iPMA-based STT switching.

The comparator is the basic block for data converter circuits, designing modern analog and mixed-signal systems, for example, telecommunications that interface with sensing circuits. Several analog to digital converters (ADCs) require low-power, high-speed comparators through less area of chip. The spin device-based self-calibrated comparators are accustomed to design high-speed, low-offset and power ADCs. This paper presents two spin devices based on self-calibrated comparator, which is an area and power efficient compared with other comparators. Our proposed self-calibrated comparator consumes 1.3 µW power and 0.0272 fJ energy at a supply voltage of 0.75 V. The spin devices (MTJ and a Strip), SPICE compatible model-based Verilog-A language and PTM CMOS 45 nm model are used to simulate its performance, like the power and delay, and compared it with dynamic comparators.

Orthogonal Frequency Division Multiplexing (OFDM) is a spectrally efficient multicarrier modulation technique for high-speed data transmission over multipath fading channels. One the major issues in OFDM is a large ratio between peak and average power, which affects Power Amplifiers in terms of complexity. A lot of techniques have proposed to reduce the power ratio but transmitted power, bit error rate (BER), etc. are so high. In this paper, combined SLM and proposed Tone Reservation methods are performed to reduce for power ratio between peak and average. Proposed Tone Reservation is the best suitable technique, based on BER and CCDF performance of the system.

The pre-charge sense amplifier is essential for the design of hybrid circuits based on the combination of CMOS and spin devices like magnetic tunnel junction (MTJ). The double tail sense amplifier (DTSA) offers better reliability, power efficiency and good performance. This paper offered a novel modified double-tail sense amplifier' (MDTSA) and compared its performance in terms of delay, power and sensing error with the existing DTSA.

Unintentional shutdown of power in CMOS circuitry leads to loss of data. The usage of non-volatile elements along with CMOS to improve its performance in terms of power consumption, area, and delay is very attractive. Non-volatile elements act as a backup data source for CMOS circuitry. Current-induced domain-wall (DW) motion is a prominent switching mechanism promising low-power, high-density, and high-speed circuits. This paper presents a novel DW motion and pre-charge sense amplifier-based magnetic flash analog-to-digital converter (ADC), which is faster, and power and area efficient compared with other CMOS ADCs. By using a DW motion in a magnetic stripe SPICE compatible Verilog-A model and CMOS 45 nm design kit, its performance, such as power and delay, has been simulated and compared with CMOS-based ADCs.

The pre-charge sense amplifier (PCSA) offers good trade-off between reliability, efficiency and performance. The hybrid combination in PCSA gives better result due to non-volatile nature of Magnetic Tunnel Junction. In this paper, performance of proposed Sense Amplifier (SA) has been evaluated in terms of delay and power and compared with another Sense amplifier (SA). The proposed double tail sense amplifier (DTSA) consumes 11.162 µW and 0.3405 fJ energy at the supply voltage of 0.75V. This proposed comparator can operate at high frequency. The simulations is produced to investigate its process variation with help of Monte Carlo method.

Magnetic tunnel junction (MTJ) and current induced domain wall motion in magnetic strip are used as a comparator of a flash ADC. This flash ADC has good performance in terms of power consumption and area because it uses spintronic devices in conjunction with CMOS. Motion of domain-wall (DW) in magnetic strip is a promising technique to save area and power without degrading speed. This paper proposes an energy and area efficient flash ADC based on a comparator constructed using Domain wall motion in a magnetic strip and MTJ. It has less area and power consumption than other ADCs. This 5-bit Flash ADC can operate at 250MS/s with power consumption of 1.15mW. Verilog-A Compact model is used for the domain wall and MTJ and simulation has been carried out with Cadence design tools using PDK CMOS 45nm design Kit. The results are then compared with conventional ADCs.