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A 10/30 MHz voltage-mode controlled buck converter with a wide duty-cycle range is presented. A high-accuracy delay-compensated ramp generator using only low-speed comparators but can work up to 70 MHz is proposed. By using a differential difference amplifier (DDA), a new Type-III compensator is proposed to reduce the chip area of the compensator by 60%. Moreover, based on the unique structure of the proposed compensator, an end-point prediction (EPP) scheme is also implemented to achieve fast reference-tracking responses. The converter was fabricated in a 0.13 μm standard CMOS process. It achieves wide duty-cycle ranges of 0.75 and 0.59 when switching at 10 MHz and 30 MHz with peak efficiencies of 91.8% and 86.6%, respectively. The measured maximum output power is 3.6 W with 2.4 V output voltage and 1.5 A load current. With a constant load current of 500 mA, the up-tracking speeds for switching frequencies of 10 MHz and 30 MHz are 1.67 μs/V and 0.67 μs/V, respectively. The down-tracking speeds for 10 MHz and 30 MHz are 4.44 μs/V and 1.56 μs/V, respectively.

Uniform oil-soluble anatase nanoparticles (NPs) were obtained by a novel oil–water interface method, using tetra-n-butyl titanate (TnBT) of 0.25 mol/L and dodecylamine (DDA) of 0.10–0.60 mol/L in cyclohexane as the oil phase, and diluted NaOH or HClO4 solution as the water phase. The particle size was tuned by adjusting various reaction parameters, with the smaller grain size occurring at lower pH of the water phase, or relatively higher temperature (160 °C), shorter reaction time, and relatively higher DDA concentration. Additionally, the aspect ratio of the titania NPs increased with the decline of preparation temperature probably due to the anisotropic growth. More importantly, the formation process of the uniform oil-soluble titania NPs by this method was proposed based on the above results and the previous outstanding work for synthesis of monodispersed inorganic NPs. This work will conduce to the application of oil-soluble titania and the formation of other monodispersed inorganic NPs.

A low-dropout regulator (LDR) using a matching-enhanced error amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation capacitor or large ESR of the output capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2 of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.

This paper proposed a new high-order curvature compensation technique for a new bandgap voltage reference structure using the temperature characteristics of current gain β and emitter bandgap narrowing factor ΔE G of a lateral NPN bipolar transistor. The new structure can produce two voltage references, which are 1.209 and 2.418 V, respectively. The simulation results show that the temperature coefficients of the two output voltage are 0.52 ppm/°C, the PSRR is more than 60 dB for frequencies at 10 kHz, and the circuit dissipates 0.18 mW with 5-V supply.

A load-transient enhanced low-dropout regulator (LDR) based on a buffer stage with paralleled current and voltage paths is proposed. By using a 1.2V p-type source-follower with small bias current as the voltage path, the gate-swing of the power transistor is widened and load capability is enhanced significantly. Moreover, by adding an inverting amplifier with diode-connected load as the current path, the LDR has good loop stability and fast load transient response. The proposed LDR was designed in a 0.13um mixed-mode CMOS process. The dropout voltage is 0.2V, and the quiescent current is only 10uA. Simulation results show that the LDR is stable with zero-ESR compensation, and it achieves 11mV voltage dip for a load current step of 200mA with 1ns edge times.

A low-dropout regulator (LDR) using an ultra-fast error amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies is hence achieved. Moreover, transient-enhancement techniques employed by the EA and UGB enable very fast load transient responses. The proposed LDR was designed in a 0.13μm mixed-mode CMOS process. Simulation results show that the quiescent current is 4μA and it achieves 7mV voltage dip for a load current step of 400mA with 1ns edge times. The PSR for all load range are better than -28dB at 10MHz and -9dB at 50MHz, respectively.

Dynamic voltage scaling (DVS) is an effective strategy in reducing the power consumption of a processor through adjusting its supply voltage at runtime. The power converter that drives the processor should have a wide output voltage range and fast reference-tracking response while maintaining a high efficiency. For such applications, inductive switching converters are suitable candidates [1-4]. To enhance the transient response and to reduce the size of off-chip components, DC-DC converters switching in the 10MHz range are studied recently. When switching at a high frequency, efficiency is compromised as the switching loss becomes significant. Moreover, comparator delay of a few ns causes serious over-charging and over-discharging of the ramp capacitor and the delay also limits the maximum duty cycle of the converter. A current-mode control needs an on-chip current sensor that would consume too much power when running in the 10MHz range. In [5], a 5MHz converter employs auto-selectable peak- and valley-current control, but the duty cycle range is limited to 0.6. A higher switching frequency (fs) would further reduce this range and would not be applicable for DVS. Therefore, a voltage-mode control with Type-III compensation for loop bandwidth extension becomes an attractive solution. However, a conventional Type-III compensator needs large on-chip compensation capacitors and resistors. In [6], a pseudo Type-III compensator reduces the value and thus size of those components, however, it requires adding lowpass and bandpass functions that complicates the design, and furthermore it does not use any special technique for fast reference tracking.

In this paper, a 10/30MHz PWM buck converter with an accuracy-improved ramp generator is proposed. To extend the minimum duty ratio of the converter, the valley of the ramp signal is controlled to be larger than 0.2V by the threshold voltage of an NMOS transistor. To shorten the delay time of the comparator in the ramp generator, a high speed two-stage push-pull comparator is presented. Simulation results of the ramp generator with switching frequencies from 10MHz to 30MHz show that the error due to process variations for the ramp, clock and maximum duty ratio are not larger than 10%. To avoid the design of high speed current sensor and maximize the unity-gain frequency of the regulation loop, voltage mode control with type III compensation is adopted for the converter. Measurement results show that the proposed buck converter with 500mA of load range has good steady-state and transient performances for 10MHz and 30MHz of switching frequencies, respectively.

Continuous-time common-mode feedback (CMFB) detector circuits for a fully differential amplifier with improved common-mode voltage detection accuracy are proposed, designed and analyzed. Firstly, we analyzed the proposed N-type CMFB detector, showing that it has two turning points when the differential voltage increases and it achieves very small deviation from the detected common-mode voltage. By combining the N-type and the P-type components directly, the proposed complementary CMFB detector circuit has further improved detection accuracy, and the simulation results with 0.13µm IBM process show only 6mV variation for rail-to-rail differential input voltage. A fully differential high gain wide bandwidth amplifier with the proposed CMFB detector circuit is designed and the simulation results have verified the proposed CMFB detector circuits.

A chip-area-efficient CMOS low-dropout regulator (LDR) based on a wide-swing voltage buffer is proposed for battery-powered portable applications. By using a low-threshold PMOS with a novel parabolic adaptive biasing technique in the buffer, the voltage overhead is dramatically reduced, allowing a small-sized power transistor that works in the linear region at heavy load to be used while still maintaining a large load range and a tight regulation. The operation principle and the stability issues of using low-ESR output capacitor without any compensation capacitors are discussed. The proposed LDR has been fabricated in a standard 0.13-μm CMOS process, and highvoltage devices are used for the power transistor and in the error amplifier to accommodate for the Li-Ion battery voltage range. With 0.2V dropout voltage and 200 mA maximum load current, the measured load regulation is 85 μV/mA while the occupied active chip area is only 0.045mm2.

This paper presents a fast-transient-response hybrid buck converter (HBC) which consists of a voltage mode PWM switching converter with Type III compensation and two auxiliary linear regulators for portable applications. With techniques of hysteretic load transient detection and adaptive duty ratio compensation, the proposed HBC achieves automatic and nearly-seamless loop transition during load transient to achieve small voltage dip and short recovery time. The auxiliary linear regulators can be automatically deactivated in the steady state such that the power efficiency of the switching converter is not compromised. Experimental results of a 0.13-μm CMOS prototype with 10 MHz switching frequency show that, compared with the conventional design, the proposed HBC reduces the voltage dip from 145mV to 55mV and the recovery time from 7.0μs to 1.5μs for a 300mA load current step-up within 20ns.

In the title chalcone derivative, C20H22O6, the dihedral angle between the mean planes of the benzene rings is 15.77 (6)°. The H atoms of the central C=C double bond are in a trans configuration. There are a number of C—H...O interactions and a C—H...π interaction present in the crystal structure.

A novel super-bandwidth three-stage amplifier with a new stability method are proposed in this paper. It could produce two left-half-plane zeros to compensate the two non-dominant poles and the dominant pole, which makes the amplifier had very large bandwidth and good phase margin. Moreover, only one Miller capacitor is required, and consumes not large power consumption when driving a large load capacitor. The simulation results show that for 1.5V power supply, a GBW of 22MHz, DC gain of 100 dB, PM of 62° and power dissipation of 0.708mW can be achieved for a load capacitor of 120pF and 2pF Miller compensation capacitor in 0.5?m CMOS technology. Finally, corner analysis shows that the proposed amplifier is suitable for engineering applications.

This paper proposed a new curvature compensation approach for a kind of bandgap voltage reference using the temperature characteristics of the current gain beta and the bandgap narrowing factor DeltaEG of emitter of a bipolar transistor. This technique requires no additional circuits for the curvature compensation. This paper designed two bandgap references that the output voltages are 1.207 v and 2.419 v, respectively and the temperature coefficients are 0.73 ppm/degC and 0.65 ppm/degC, respectively. These circuits dissipate about 0.09 mW with a 3-V supply and 0.18 mW with a 5-V supply, respectively