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An automatic optimization methodology based on AI algorithm is proposed to achieve multi-targeting of various devices in 0.13 μm next BCD process development. The optimized process conditions are simultaneously provided with satisfying various ET-specs of the BCD devices from our method and TCAD analysis. The method has practically been applied to well ion implantation processes shared with seven different devices, and its targeting rate of 87% has been verified through silicon evaluation. Its turnaround time (TAT) is reduced by 90% compared to conventional procedure.

This paper presents a novel approach to enable real-time device simulation and optimization. State-of-the-art algorithms which can describe semiconductor domain are adopted to train deep learning models whose input and output are process condition and doping profile / electrical characteristic, respectively. Our framework enables to update automatically deep learning models by estimating the uncertainty of the model prediction. Our Real-Time TCAD framework is validated on 130nm processes for display driver integration circuit (DDI), and 1) prediction time was 530,000 times faster than conventional TCAD, and time spent for process optimization was reduced by 300,000 times compared to human expert, 2) the model achieved average accuracy of 99% compared to TCAD simulation results, and thus, 3) process development time for DDI was reduced by 8 weeks.

Table S1. Reference value (sex-height-specific 95th percentile of blood pressures) for adolescent hypertension. Table S2. Baseline characteristics of the participants according to follow-up. Table S3. Multivariable logistic regression analysis for cholesterol at adolescence with adult hypertension. Table S4. Multivariable logistic regression analysis for cholesterol at adolescence with adult hypertension. Table S5. Multivariable linear regression analysis between cholesterol and blood pressure. Table S6. Sensitivity analysis after excluding participants who were followed-up via online or mail surveys. (DOCX 26 kb)

In this work, we report the physics-based SPICE model of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and demonstrate the SPICE simulation of amorphous InGaZnO (a- IGZO) TFT inverter by using Verilog-A. As key physical parameter, subgap density-of-states (DOS) is extracted and used for calculating the electric potential, carrier density, and mobility along the depth direction of active thin-film. It is confirmed that the proposed DOS-based SPICE model can successfully reproduce the voltage transfer characteristic of a-IGZO inverter as well as the measured I-V characteristics of a-IGZO TFTs within the average error of 6% at VDD=20 V.

Analytical current and capacitance models for amorphous Indium-Gallium-Zinc-Oxide Thin film transistors (a-IGZO TFTs) are proposed for application to the simulation of a-IGZO TFT-based circuits. The accuracy of the proposed models are verified by comparing the measured I-V and C-V characteristics with calculated ones and the simulation result of a-IGZO TFT-based circuits. The proposed models are expected to be useful both for the optimization of fabrication process and for the prospective estimation of the effect of process conditions on the circuit performance.

The effect of the active layer thickness (TIGZO) on the constant current stress (CCS)-induced threshold voltage shift (ΔVT) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) for AMOLED drivers is investigated by using a subgap density-of-states (DOS) model and simulation. The CCS-induced positive ΔVT in a-IGZO TFT with a thicker TIGZO is larger than that in a-IGZO TFTs with a thinner TIGO. It is originated from more activated charge trapping (60∼80 % in total ΔVT) and DOS creation due to a higher surface electric field with a thicker TIGZO. Our results show that using thinner active layer in a-IGZO TFTs is desirable for high performance and highly stable AMOLEDs if the quality of thin-film bulk is guranteed irrespective of TIGZO.

The highly-doped buried layer (carrier concentration of ~ 1019 cm− 3) in an amorphous indium–gallium–zinc oxide (a-IGZO) channel layer of thin film transistor (TFT) led to dramatic improvements in the performance and prolonged bias-stability without any high temperature treatment. These improvements are associated with the enhancement in density-of-states and carrier transport. The channel layer is composed of Ga-doped ZnO (GZO) and a-IGZO layers. Measurements performed on GZO-buried a-IGZO (GB-IGZO) TFTs indicate enhanced n-channel active layer characteristics, such as Vth, μFE, Ioff, Ion/off ratio and S.S, which were enhanced to 1.2 V, 10.04 cm2/V·s, ~ 10−13A, ~ 107 and 0.93 V/decade, respectively. From the result of simulation, a current path was well defined through the surface of oxide active layer especially in GB-IGZO TFT case because the highly-doped buried layer plays the critical role of supplying sufficient negative charge density to compensate the amount of positive charge induced by the increasing gate voltage. The mechanism underlying the high performance and good stability is found to be the localization effect of a current path due to a highly-doped buried layer, which also effectively screens the oxide bulk and/or back interface trap-induced bias temperature instability.

Capacitance–voltage (C–V) characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) are comparatively investigated with two different measurement configurations. Normal gate-to-source/drain (S/D) C–V and quasi-static C–V curves are employed to characterize physical mechanisms with equivalent circuit models for a-IGZO TFTs. The difference between the normal C–V and the quasi-static C–V (QSCV) characteristics is investigated by the dependence on the gate voltage (VG), measurement configuration, and optical illumination. The discrepancy is analyzed to be due to a high hole barrier in the S/D contact region and a slow response of active bulk charges (Qloc and Qfree) in the a-IGZO active layer.

The amorphous oxide thin-film transistor (TFT)-oriented simulator [subgap Density of states (DOS)-based Amorphous Oxide TFT Simulator (DeAOTS)] is proposed, implemented, and demonstrated for amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs. It only consists of parameters having their physical meanings and is supplied with concrete techniques for parameter extraction. Among the physical parameters, the acceptor-like DOS gA(E) was experimentally extracted using the multifrequency C-V technique, whereas the donor-like DOS gD(E) and the doping concentration ND were extracted using numerical iterations. The simulation result reproduces the DOS and thin-film-thickness-dependence of dc I-V characteristics very well. Compared with the previously reported a-Si TFT models, the proposed DeAOTS model not only reflects the strong VGS dependence of the effective mobility (μeff) but also clarifies the relations between process-controlled DOS parameters and dc I- V characteristics based on experimentally extracted DOS parameters. Also, it sufficiently takes into account the peculiar situation of amorphous oxide TFTs where the free-carrier charge can be larger than the localized one out of the total induced charge. Moreover, it reproduces the measured electrical characteristics within the wide range of VGS/VDS with a single equation, not distinguishing the operation regions such as the subthreshold, linear, and saturation regimes.

We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler-Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole injection is used for erasing along the channel width direction. With separated paths for program and erase, improved device performance is obtained with sensing margin. In order to improve the immunity to second-bit effects, the gate-induced drain leakage current method, which is a charge detection method and highly sensitive to the locally stored charges, is employed for the reading of the stored data. In terms of the scalability, we confirmed by 2-D technology computer-aided design simulation that the proposed NVM cell with channel length L = 50 nm operates with enough sensing margin and high-density ( ~ 5 F2/bit) NVM by the crossed cell array architecture.

In this letter, we show that the physics-based equation that was derived for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) in our previous work can be successfully incorporated into the SPICE model via Verilog-A. The proposed model and extracted SPICE parameters successfully reproduce the measured current-voltage characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs and the load line diagram of a-IGZO TFT inverters. The main advantage of our model is that each parameter has its physical meaning and most of them can be related with the fabrication conditions of AOS TFTs. To show the advantage of the proposed models and extracted SPICE parameters more clearly, we investigate the effect of ionized donor concentration (ND+) on the inverter circuit operation and determine the optimum value of ND+ and device dimensions considering the tradeoff between the power consumption and the output swing in a-IGZO inverters. The proposed physics-based SPICE model via Verilog-A is expected to play a significant role in the process optimization and circuit design with AOS TFTs.

The effect of O2 flow rate (OFR) during channel deposition is investigated on the electrical instability of the amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under positive gate bias stresses. From the transfer curves measured before and after bias stresses, we can observe that the high OFR degrades the electrical stability and causes the large threshold voltage shift (ΔVT) in a-IGZO TFTs. To elucidate the origin of the observed phenomenon, we extract and compare the subgap density of states (DOS) in devices with various OFRs. The extracted DOS shows that the subgap states become higher with the increase of OFR in a wide range of bandgap, and the enhanced electron trapping due to the increased number of trap states is considered as the cause of larger ΔVT in higher OFR devices.

The effect of the active layer thickness (TIGZO) on the negative bias stress (NBS)-induced threshold voltage shift (ΔVT) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is investigated and explained by using a subgap density-of-states (DOS) model. The NBS-induced negative ΔVT in a-IGZO TFT with a thinner TIGZO is larger than that with a thicker TIGZO. Based on the simulation result with the subgap DOS model, it is concluded that the TIGZO-dependent ΔVT is originated from the accelerated creation of shallow donor states due to a higher surface electric field in a-IGZO TFTs with a thinner TIGZO.

The top-source noncoplanar diagonal electrode (TS-NDE) structure was fabricated and simulated with the oxide channel layer. The structure exhibits enhanced stability and low subthreshold swing with higher mobility than those of bottom-source electrode structure thin-film transistors (TFTs). Interestingly, in this highly stable TS-NDE, the current density was highly formed through the center of the active-channel region from top-source electrode to bottom-drain electrode in the thin-film layer due to the on-current state. In other words, the TS-NDE TFT is less affected by back-interface interferences, which are the main degradation factors in oxide TFTs due to the different current path.

An extraction technique for subgap density of states (DOS) in an n-channel amorphous InGaZnO thin-film transistor (TFT) by using multifrequency capacitance-voltage (C -V) characteristics is proposed and verified by comparing the measured I- V characteristics with the technology computer-aided design simulation results incorporating the extracted DOS as parameters. It takes on the superposition of exponential tail states and exponential deep states with characteristic parameters for N TA = 1.1 × 1017 cm-3 · eV-1, N DA = 4 × 1015 cm-3 · eV-1, kT TA = 0.09 eV, and kT DA = 0.4 eV. The proposed technique allows obtaining the frequency-independent C-V curve, which is very useful for oxide semiconductor TFT modeling and characterization, and considers the nonlinear relation between the energy level of DOS and the gate voltage V GS. In addition, it is a simple, fast, and accurate extraction method for DOS in amorphous InGaZnO TFTs without optical illumination, temperature dependence, and numerical iteration.

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T ) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency.

The relation between the low-frequency noise (LFN) and subgap density of states (DOS) of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is investigated by changing the postannealing temperature from 150°C to 300°C. It is found that the density of the tail states in the TFT annealed at 300°C (showing the lowest LFN) is prominently lower than those in the TFTs annealed at 250°C and 150°C. The densities of the tail states in the TFTs annealed at 250°C and 150°C (indicating similar LFN) are almost the same. In addition, it is clearly observed that the increased DOS of the a-IGZO TFT subjected to ac gate voltage stress results in a higher LFN compared with one without electrical stress. Hooge's parameters αH's are extracted to be ~4.5 × 10-3 (for the TFT annealed at 300°C) and ~1 × 10-2 (for the TFTs annealed at 25°C and 150°C as well as for the TFT annealed at 300°C after the application of electrical ac stress). Therefore, the role of an a-IGZO subgap DOS on a LFN characteristic seems to be originated from the generation-recombination noise-induced carrier number fluctuation (via trap centers in the DOS tail states) while its correlation with the carrier mobility fluctuation is not clear except for the slope close to -1 in the logarithmic curve with the normalized power spectral density versus the gate overdrive voltage.

We have demonstrated self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays. The processes such as source/drain and channel engineering have been developed to realize the self-aligned top gate structure. Ar plasma is exposed on the source/drain region of active layer to minimize the source/drain series resistances. To prevent the conductive channel, N 2 O plasma is also treated on the channel region of active layer. We obtain a field effect mobility of 5.5 cm2/V·s, a threshold voltage of 1.1 V, and a sub-threshold swing of 0.35 V/decade at sub-micron a-GIZO TFTs with the length of 0.67#x00B5;m. Furthermore, a-IZO TFTs fabricated for gate and data driver circuits on glass substrate exhibit excellent electrical properties such as a field effect mobility of 115 cm2/V·s, a threshold voltage of 0.2 V, a sub-threshold swing of 0.2 V/decade, and low threshold voltage shift less than 1 V under bias temperature stress for 3 hr.

ZnO-based photo-thin film transistors with enhanced photoresponse were developed using transparent conductive oxide contacts. Changing the electrode from opaque Mo to transparent In-Zn-O increases the photocurrent by five orders of magnitude. By changing the opacity of each source and drain electrode, we could observe how the photoresponse is affected. We deduce that the photocurrent generation mechanism is based on an energy band change due to the photon irradiation. More importantly, we reveal that the photocurrent is determined by the energy barrier of injected electrons at the interface between the source electrode and the active layer.

The temperature dependence of the photocurrent of amorphous GaInZnO/InZnO thin film transistors was investigated at various illumination wavelengths. The photocurrent is highly dependent on the irradiation conditions, even though the saturation characteristics were similar regardless of illumination. When the photon energy was greater than 2.82 eV, it was large enough to excite a bound electron independent of the thermal energy. When the irradiation photon energy was not large enough for direct excitation, it was observed that the states in the Urbach tail region, approximately 0.18–0.28 eV below the conduction band, acted as shallow traps that induced a thermally activated photocurrent.

Effect of trap-density of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were studied using different analysis of x-ray photoelectron spectroscopy (XPS) depth profile and density of states (DOSs). To change trap-densities systematically, rf-power was varied to cause different effect on the initial growth stage of a-IGZO layer grown on gate insulator. The interfacial trap-density was confirmed to be dominant effect on the performance and the threshold voltage shift of a-IGZO TFT by observing the variation of O1s binding energy from XPS. The relation between temperature stress induced and trap-density in deep level was investigated by analyzing DOSs.

We report on the origin of threshold voltage shift with the thickness of amorphous InGaZnO channel layer deposited by rf magnetron sputter at room temperature, using density of states extracted from multi frequency method and falling rates of activation energy, which of trends are entirely consistent each other in respect of the reduction of total traps with increasing the channel thickness. Furthermore, we shows that the behavior of ΔVth under the positive gate bias stress and thermal stress can be explained by charge trapping mechanism based on total trap variation.

Due to the inherent property of large contact and parasitic resistances in amorphous InGaZnO (a-IGZO) thin film transistors (TFTs), a metal-semiconductor-metal (MSM) structure is a key element in a-IGZO TFTs. Therefore, voltage drops across resistances and MSM structure should be fully considered in the modeling and characterization of a-IGZO TFTs. A physics-based semiempirical model for the current-voltage characteristics of the MSM structure for the source-channel-drain contact in a-IGZO TFTs is proposed and verified with experimental results. The proposed model for the current in a-IGZO MSM structures includes a thermionic field emission [JTFE∝exp(VR,Schottky/Vo)] and trap-assisted generation (Jgen∝VR,Schottky) in addition to the thermionic emission current (JS: Independent of the bias) under reverse bias. Experimental result suggests that electrical characteristics of the MSM structure depend not only on the Schottky barrier but also on the bulk property of the a-IGZO active layer.

As the oxide TFT-oriented simulator, the subgap density of states- based amorphous oxide TFT simulator (DAOTS) is proposed, implemented, and demonstrated for a-InGaZnO TFTs. It consists of the parameters having their physical meanings. Moreover, concrete techniques for parameter extraction are supplied. Most preferably, the quantitative self-consistency with experimental data is guaranteed in DAOTS.

The degradation mechanism of a-IGZO TFT-based inverter is investigated under the toggled AC biased input (VIN), with a direct evidence of subgap density of states (DOS). The AC stress-induced threshold voltage shift (ΔVT) of driver TFT is observed to be smaller than that of load TFT, which results in the VOH degradation during AC stress. The dominant mechanism of the toggled VIN stress-induced ΔVT of driver TFT in a-IGZO inverter is the increase of subgap DOS deep stats, whereas the ΔVT of load TFT during inverter operation is attributed to the electron trapping into the interface and/or a-IGZO thin film.

The extraction of acceptor-like subgap DOS (gA(E)) in a-InGaZnO and a-InHfZnO TFTs is demonstrated by using multi-frequency C- V technique. The DC performance and negative bias stress (NBS)- induced instability are compared in perspective of gA(E). The superior stability of a-InHfZnO TFT is deduced to be originated from donor-like DOS gD(E).