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This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

This article presents a 0.975-pJ/bit 56-Gb/s pulse amplitude modulation-4 (PAM-4) receiver using a time-based least significant bit (LSB) decoder in 28-nm CMOS technology. The proposed time-domain decision technique improves the robustness of comparator voltage variations by separating the data and reference paths. If the reference voltage difference is constant regardless of the common-mode voltage shift, the time-domain decoder achieves a low bit error rate (BER). To improve the timing margin of the LSB decoder from the data-dependent jitter, a sample-and-hold (S/H) structure is adopted in both the data and reference paths. The S/H circuits extend the timing margin by converting the input of the comparators to a constant voltage. The number of comparators for data decoding is reduced to two-thirds, and only eight comparators are required for a quarter-rate structure. The number of comparators in the data path, excluding the reference path, is 4, which reduces the loading capacitance. An adaptive threshold voltage calibration was implemented to generate the timing reference pulse. In addition to bathtub graphs, the BER, according to the $ {V_{CM}}$ change of the reference voltages, is plotted to show the sensitivity to the voltage variation.

This brief presents a low-power counter-based adaptive equalizer that does not require additional power-hungry comparators for an equalizer adaptation loop. A pulse generator in the proposed equalizer obviates the need for additional error sampling comparators. Instead, it allows the receiver to utilize an output of a data decision comparator for the equalizer adaptation by generating a pulse that indicates whether the comparator makes a firm decision for the incoming data. A single comparator is shared by the data recovery path and equalizer adaptation loop. Consequently, the proposed counter-based equalizer achieves a low power dissipation owing to the reduced number of comparators. Fabricated in a 28-nm CMOS technology, the prototype receiver occupies an active area of 0.004 mm2 and consumes only 0.99-pJ/b at 15-Gb/s.

A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the delay code sequentially. A bidirectional shift register enables this operation with low power, resulting in bang-bang jitter that is three times smaller than that of a conventional DDLL. Conventional delay control is replaced with sequential delay control after a DDLL lock to reduce the locking time. A DDLL with a wide operation range is achieved with a reconfigurable delay line. Unlike the conventional DDLL, the minimum delay difference is adjustable in the proposed structure. To achieve a wide frequency range, the minimum delay difference of the quadrature clock is increased or decreased in three operation modes. To compensate for local variations in the CMOS process, a skew calibration circuit is implemented with the DDLL. The hardware cost of skew calibration is minimized with the proposed DDLL because it shares the subblocks for sequential delay control. The average phase difference from the quadrature clocks becomes the reference for the 90° phase for skew correction. A duty-cycle corrector (DCC) is implemented by collecting the positive edges of the quadrature-phase clocks. The DDLL consumes 6.5 mW at the maximum clock frequency of 4 GHz. The peak-to-peak jitter is improved from 15.6 to 12.5 ps with sequential delay control.

A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin bit efficiency is achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 data using a low-power encoding logic and an output driver. The receiver achieves a bit error rate (BER) of less than 1E-12 over an 80-mm FR-4 printed circuit board (PCB) channel. At the maximum data rate, the bit efficiency of the transceiver is 1.11 pJ/bit, consuming 33.4 mW. In the receiver, the attenuated PAM-3 data are equalized by a continuous-time linear equalizer (CTLE) and a one-tap tri-level DFE, which has the same complexity as that of non-return-to-zero (NRZ) signaling. The tri-state buffers, which have a floating PMOS switch, convert the output of the comparator into NRZ data, resulting in reduced delay and power dissipation. Four channels of the transceivers operate at data rates of up to 30 $\times $ 4 Gb/s, and the horizontal eye margin of the measured PAM-3 data is achieved at a UI of 0.14 for the PRBS-7 pattern at the maximum data rate.

This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with −12 bit-error rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm2 in a 28-nm CMOS technology.

Input-data-independent clock and data recovery (CDR) employing bit-efficient braid clock signaling (BCS) for raw data transmission is presented for a point-to-point post-8K ultrahigh-definition (UHD) intrapanel interface at 24 Gb/s. The effect of input data pattern on CDR is analyzed, and the proposed bit-efficient BCS scheme for phase-locked loop (PLL)-based CDR eliminates the jitter-peaking dependency on the input data pattern. The removal of this dependency with the proposed BCS scheme decreases the loop filter size without jitter peaking and the bit error rate (BER). The prototype CDR has been fabricated using a 28-nm CMOS process and occupies an area of 0.024 mm2. The 24-Gb/s PLL-based CDR design with the BCS scheme consumes 13.4 mW. The CDR with BCS scheme achieves a recovered clock long-term jitter of 5.11 ps $_{\text{rms}}$ /37.5 ps $_{\text{p-p}}$ and a reduction in jitter peaking of 27 dB with a small-sized loop filter and six repeated consecutive identical digits in the stream of a PRBS7 pattern.

This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines.

A power reduction scheme that uses ac termination at receiver (RX) and a transmitter (TX) output driver with an active inductor part (AIP) is proposed for a point-to-point post-low-power mobile DRAM4 interface at 8 Gb/s. AC termination at the RX I/O can reduce the power consumption by preventing dc power loss. However, this causes inter symbol interference (ISI), owing to the difference in gain depending on the frequency. Thus, ac termination generates more jitter, which results in a smaller eye-opening than the conventional on-die termination. The AIP in the TX output driver reduces the low-frequency gain and the ISI caused by the ac termination. This reduces the jitter and improves the eye-opening. The proposed AIP allows changing the frequency range by adjusting the resistance ( ${R}_{\mathrm{AI}}$ ), capacitance ( ${C} _{\mathrm{AI}}$ ), and the size of the MOSFET according to the resistance ( ${R} _{\mathrm{ac}}$ ) and capacitance ( ${C} _{\mathrm{ac}}$ ) used in the ac termination at the RX. In this brief, the ac termination at the RX and the AIP in the TX were implemented in a 28-nm CMOS process and operated at 8 Gb/s with a 3-inch FR4 microstrip line including a board and a socket model. The proposed transceiver chip achieves a peak-to-peak jitterof 43.6 ps and power reduction of 31% compared with chips without ac termination and AIP.

A point-to-point interface with a clock embedded scheme (CES) in Fig. 29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery in RX without a reference clock channel is usually carried out using one of two type of data encoding schemes, embedded clock with dummy clock bits [1–2,5] or ensured transition density with data encoding such as 8B10B encoding [3]. However, these two schemes reduce the effective bandwidth because they require over 20% overhead in the data stream. Although highly efficient signaling schemes have been introduced recently in the literature [4] to cope with the physical limitations of the process and channel, it is difficult to adopt these multi-level signaling schemes in intra-panel interfaces where there is a highly resistive channel of Chip-On-Glass and a ground bouncing problem [5] due to different voltage domains (1V and 8V–30V) for serial link and source drivers. This paper introduces a braid clock signaling (BCS) scheme which has the following advantages: 1) clock information without redundant bits; 2) NRZ signal levels for high voltage margin; and 3) low EMI emission with a random data dependent encoding and a spread transition scheme.

Objective We performed this study to assess the effect of an antiplatelet agent on the progression of white matter hyperintensities (WMH). Methods From August 2003 to May 2005, we consecutively enrolled patients who underwent brain magnetic resonance imaging (MRI) for health check-up purposes and showed no significant findings other than WMH of any degree. Patients were divided into two groups based on whether or not they received antiplatelet therapy. All patients had a follow-up brain MRI after 5 years and WMH volume change was measured using imaging analysis software. To minimize selection bias potentially arising from antiplatelet treatment assignment, analyses were inverse probability weighted. Results Among the 93 patients who met the inclusion criteria, 54 patients (58.1%) were grouped as the antiplatelet group (AG), and the remaining 39 patients (41.9%) as the non-antiplatelet group (NAG). After inverse propensity weighting, all baseline characteristics were similar between the two groups, and antiplatelet treatment did not show any significant effect on the total WMH volume change (p = 0.957). Conclusion Antiplatelet medication may not alter the progression of WMH.

The syndrome of inappropriate antidiuretic hormone secretion (SIADH) can be caused by a variety of drugs. Dopaminergic drugs might enhance the secretion of the antidiuretic hormone arginine vasopressin by reducing γ-amino butyric acid release through the dopaminergic receptor in supraoptic nucleus. A 75-year-old woman with Parkinson’s disease developed asthenia, delirium, aggravated parkinsonian symptoms, and hypotonic hyponatremia along with the diagnostic criteria for SIADH during dose escalation of pramipexole. After pramipexole withdrawal, these symptoms disappeared, and sodium levels returned to normal values. The serum sodium levels of patients receiving pramipexole should be monitored, especially during dose escalation.