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This study proposes an optimization method for temperature modulation in chemiresistor-type gas sensors based on Bayesian optimization (BO), and its applicability was investigated. As voltage for a sensor heater, our previously proposed waveform was employed, and the parameters determining the voltage range were optimized. Employing the Bouldin–Davies index (DBI) as an objective function (OBJ), BO was utilized to minimize the DBI calculated from a feature matrix built from the collected data followed by pre-processing. The sensor responses were measured using five test gases with five concentrations, amounting to 2500 data points per parameter set. After seven trials with four initial parameter sets (ten parameter sets were tested in total), the DBI was successfully reduced from 2.1 to 1.5. The classification accuracy for the test gases based on the support vector machine tends to increase with decreasing the DBI, indicating that the DBI acts as a good OBJ. Additionally, the accuracy itself increased from 85.4% to 93.2% through optimization. The deviation from the tendency that the accuracy increases with decreasing the DBI for some parameter sets was also discussed. Consequently, it was demonstrated that the proposed optimization method based on BO is promising for temperature modulation. [ABSTRACT FROM AUTHOR]

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm² in 0.13-μm CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm². Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m. [ABSTRACT FROM AUTHOR]