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2. Vertical GaN Devices: Process and Reliability

3. A CMOS-Compatible Process for ≥3 kV GaN Power HEMTs on 6-inch Sapphire Using In Situ SiN as the Gate Dielectric.

8. Suppressing the Leakage of GaN HEMTs on Single-Crystalline AlN Templates by Buffer Optimization

10. Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization

12. 1700 V High-Performance GaN HEMTs on 6-inch Sapphire With 1.5 μm Thin Buffer

13. TCAD Simulation of the Effect of Buffer Layer Parameters on Single Event Burn-Out in p-GaN Gate HEMTs

14. Report of GaN HEMTs on 8-in Sapphire

15. Demonstration of >8-kV GaN HEMTs With CMOS-Compatible Manufacturing on 6-in Sapphire Substrates for Medium-Voltage Applications

21. Geochemical Behavior of Sedimentary Phosphorus Species in Northernmost Artificial Mangroves in China

24. Vertical GaN devices: Process and reliability

28. Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

29. Understanding the Leakage Mechanisms and Breakdown Limits of Vertical GaN-on-Si p+n−n Diodes: The Road to Reliable Vertical MOSFETs

32. Reliability of p-GaN Gate HEMTs in Reverse Conduction

34. Integration of 650 V GaN Power ICs on 200 mm Engineered Substrates

41. Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

43. Buffer Vertical Leakage Mechanism and Reliability of 200-mm GaN-on-SOI

44. GaN power IC design using the MIT virtual source GaNFET compact model with gate leakage and VT instability effect.

45. Observation of Dynamic VTH of p-GaN Gate HEMTs by Fast Sweeping Characterization.

50. Statistical Analysis of the Impact of Anode Recess on the Electrical Characteristics of AlGaN/GaN Schottky Diodes With Gated Edge Termination

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