Search

Owing to the high impedance transformation ratio, the Doherty power amplifier (DPA) with a large output power back-off generally has bandwidth limitations. This study proposes an asymmetric DPA with an impedance distribution and control circuit (IDCC) at the post-matching network to improve the bandwidth. The IDCC, based on a resonance circuit and a series transmission line, distributes and controls the load impedance according to the frequency so that the bandwidth of the DPA can be extended. To verify the proposed IDCC, an asymmetric DPA was designed using GaN HEMT with a power capacity of 6 W and 10 W for the carrier and peaking amplifiers, respectively. The implemented DPA was evaluated for the broad frequency band between 3.3 GHz and 3.8 GHz using a 5G new radio (NR) signal with a bandwidth of 100 MHz and a peak-to-average power ratio of 7.8 dB. A drain efficiency between 43.2% and 50.7% and an adjacent channel leakage power ratio between −23.4 dBc and −27.3 dBc were achieved at an average power level that ranged between 33.5 dBm and 34.3 dBm.

The article presents a differentially excited low temperature co-fired ceramics (LTCC) based miniaturized planar aperture antenna, distinguished for its high gain and narrow-beam wideband characteristics, tailored specifically for mm-Wave antenna-in-package (AiP) applications. The proposed antenna comprises a stepped-cut patch element excited differentially and enclosed within an open cavity formed by metallized vias. Four tuning stubs are symmetrically incorporated into the stepped-cut patch element, and two pairs of shorting vias are used to ground it, improving overall impedance and gain bandwidth. Rectangular-shaped parasitic strips, strategically positioned outside the open cavity in a symmetrical arrangement, significantly narrow the main beam along two principal cutting planes, thereby enhancing broadside gain across the entire frequency band of operation. To validate the proposed design, a miniaturized and low loss differential feeding network was designed using the same LTCC technology and seamlessly integrated into the underside of the prototype antenna. According to measured results, the fabricated prototype exhibit −10 dB impedance bandwidth of 20.97% (56.55–69.8 GHz), and the realized gain is higher than 10.01 dBi with a peak gain of 12.36 dBi at 63 GHz. Moreover, the radiation pattern of the proposed design is perfectly symmetrical, boasting a half-power beamwidth less than 40° along both the planes across the entire operating band.

This paper presents a Class-E/F3 switching power amplifier (SPA) with reduced second harmonic leakage using parallel resonant circuit in series for the second harmonics. The proposed Class-E/F3 SPA has a structure utilizing a series resonant circuit in shunt for the third harmonic, designed to function as a shunt capacitor for the fundamental, and an additional parallel resonant circuit for the second harmonic, designed to operate as a series inductor for the fundamental. Using the proposed scheme, a Class-E/F3 SPA was designed and implemented for 6.78 MHz, and was evaluated with various supply voltages. It exhibited output power levels ranging from 10.26 to 59.98 W (40.11 to 47.78 dBm) with supply voltages ranging from 10 to 24 V. The efficiency was maintained at over 89.25%. Additionally, it demonstrated very low second and third harmonic distortion levels, each not exceeding −49.98 dBc, while the total harmonic distortion (THD) ranged from 1.54% to 2.15%.

While an ideal Doherty power amplifier has a linear response, the load modulated balanced amplifier (LMBA) has a compressive response under ideal conditions. This inherent nonlinear characteristic is due to the lower power contribution of the single auxiliary device as the balanced amplifier transistors approach compression. This article presents an LMBA with a two-stage control signal amplifier in place of the single auxiliary device. The idea is to preserve a high and constant gain across the high- and low-power regions by tuning the two-stage gain control signal to match the balanced amplifier gain. An optimal load trajectory can be found for a high-efficiency design by appropriately terminating the second harmonic while ensuring an optimal impedance match in all devices. At the same time, by setting an optimal output power from the auxiliary device, sufficient power is provided to linearize the response of the main power amplifier beyond the output back-off power boundary. As proof of concept, a prototype is designed and implemented. The experimental measurements demonstrate a drain efficiency of 59%–64% at maximum output power and 46%–52% at 7.5 dB output back-off power over the target frequency range of 3.3–3.8 GHz.

In response to the increasing deployment of unmanned aerial vehicles (UAVs) across various sectors, the demand for efficient microwave power transmission (MPT) systems for UAVs has become paramount. This study introduces series-fed circularly polarized (CP) and passively beam-tilted patch array antennas designed to enhance MPT in UAV applications, with the intention of addressing the needs related to extending flight times and improving operational efficiency. The radiating element of the proposed antennas employs the conventional model of the patch with truncated corners for CP operation, with transmission line lengths optimized for beam tilt to ensure precise energy transfer. Additionally, an open stub is integrated into the broadside series-fed antenna to improve impedance matching, which is crucial for maintaining signal integrity. The proposed design achieves right-hand circular polarization (RHCP) with an axial ratio (AR) below 3 dB across the operating band, indicative of its effectiveness in diverse UAV operational contexts. Prototypes of each proposed antenna were fabricated and measured according to the beam tilting angle. The measured RHCP realized gains of the proposed antennas are 14.59, 13.09, 13.07, and 10.71 dBic at the tilted angles of 0°, 15°, 30°, and 45°, respectively, at 5.84 GHz.

The load networks of advanced Doherty power amplifiers (DPAs) have traditionally been designed according to the ABCD parameters. In this paper, design conditions as an impedance transformation condition and an effective electrical length were used to design the output matching networks (OMNs) for the carrier and peaking amplifiers of the virtual-stub DPAs (VS-DPAs). An optimization method for the effective electrical length was proposed that was specifically constructed for the load impedances of the carrier amplifier at the low power level to have broadband characteristics through the load-pull simulation. Using the optimized design conditions for broadband design, compact OMNs for the carrier and peaking amplifiers were designed using quasi-lumped components. Moreover, an asymmetric structure with an increased power capacity of the peaking amplifier for the VS-DPA was proposed to compensate for a relatively low peak fundamental current of the peaking amplifier due to its deep class-C operation as well as the extended output back-off (OBO) range of the VS-DPA. To verify the proposed load network, a broadband asymmetric VS-DPA for the 3.3 - 4.2 GHz band was designed and implemented using GaN HEMTs with power capacities of 6 and 10 W. Using a 5G new radio (5G NR) signal with a signal bandwidth of 100 MHz and a peak-to-average power ratio (PAPR) of 7.8 dB, power gain of 8.2 - 9.1 dB, DE of 46.0 - 57.0%, ACLR of better than −45 dBc after DPD linearization at an average power of 35.0 dBm were achieved at the broad frequency range of 3.3 - 4.2 GHz.

This paper presents a new compact load network for Doherty power amplifiers (DPAs) with only two matching networks, such as an output matching network of the carrier amplifier, and the post-matching network (PMN), even in the presence of parasitic circuits of the packaged transistor. The load network of the carrier amplifier can be configured using a simple L-section matching structure for the complex load impedance. No matching network is required between the peaking amplifier and the current combining junction. As a result, the proposed load network can have a very compact structure with only a short transmission line, and a shunt element for the carrier amplifier, in addition to the PMN. To verify the proposed circuit, a DPA based on two packaged GaN-HEMTs was designed and implemented to have a peak output power of more than 43 dBm for the 3.5-4.0 GHz band. By the measurement results using a 5G NR signal with a peak-to-average power ratio (PAPR) of 7.9 dB and a signal bandwidth of 100 MHz, a power gain of more than 10.5 dB, and a drain efficiency (DE) of 49.5-55.4% at an average power of 36.5 dBm in the frequency band was exhibited. After applying digital pre-distortion (DPD), an adjacent channel leakage power ratio (ACLR) of -51.0 dBc was achieved.

This paper presents a 2.8-3.8 GHz broadband 2-stage fully differential Doherty power amplifier using direct interstage power division based on a 2- $\mu \text{m}$ InGaP/GaAs HBT process for 5G new radio handset applications. A compact transformer-less interstage network is proposed for direct power division for carrier and peaking amplifiers. The power division ratio at the interstage is designed to dynamically vary according to the input power level to provide higher power gain and desired load impedance modulation. By utilizing the non-linear input reactance of the peaking amplifier, broadband dynamic power division circuits were designed for an operating frequency band of as broad as 1 GHz. In addition, active bias circuits for the peaking amplifier were optimized to have sufficient gain expansion, so that the overall AM-AM characteristics is as flat as possible. A broadband load modulation network using one transformer and two quarter-wave transmission lines is proposed. For the off-chip output transformer, impedance trajectory for the wide band impedance matching is presented using a T-equivalent circuit of the transformer. The self-inductance ratio of the transformer is optimized to maximize the bandwidth. Using the 5G new radio uplink signal with a signal bandwidth of 100 MHz, the implemented Doherty PA IC exhibited a power gain of 31.9 to 38.4 dB, PAE of 22.0 to 30.6%, and average output power of 26.0 to 27.8 dBm at a given ACLR of −33.0 dBc without pre-distortion.

A new load modulation combiner (LMC) having the capability of back-off control is proposed for a Doherty power amplifier (DPA). The proposed LMC consists of two transmission lines tied at the combining node, and a shunt element across the other ends of the transmission lines. The shunt element of the LMC becomes virtually open-circuited at the peak power level and allows the carrier amplifier to have an arbitrary load impedance at the low power level. The operating principle and circuit structure of the DPA based on the proposed LMC are presented in detail. The proposed DPA was implemented using GaN-HEMT for the 3.5 - 4.0 GHz band. Using a 5G NR signal with a peak-to-average power ratio (PAPR) of 7.9 dB and signal bandwidth of 100 MHz, the implemented DPA showed drain efficiency (DE) of 49.6 - 54.4% and power gain of 11.1 - 13.0 dB at an average output power of 34.5 dBm. An adjacent channel leakage power ratio (ACLR) was obtained as −50.4 - −45.0 dBc at the average power level with a digital pre-distortion (DPD) technique.

Microwave power transfer (MPT) has been widely studied, as sensors or mobile/wearable devices have been used, especially for IoT applications. A beamforming algorithm is essential and important for both the performance and the system complexity of MPT systems. In this paper, a beamforming algorithm that requires only 3 ${N}-2$ transmission sequences for the Tx array with ${N}$ elements to estimate the optimum set of the transmission phases is proposed. The proposed algorithm is simply based on trigonometric calculations, and can be directly applied to an MPT system without element calibration. Calculation of the optimum phase set of the Tx only requires the information of the received power level from the Rx. Since simultaneous phase shifting of the multiple elements is performed during the power transmission sequence, it can have a relatively high Rx SNR, compared to the methods based on phase shifting of only one element at each sequence. In addition, optimum transmission phase sets for multiple Rx’s can be obtained from a beamforming procedure using the proposed algorithm, if the received power levels from the multiple Rx’s are collected. For verification of the proposed algorithm, a 5.2 GHz $8\times 4$ Tx array having an output power of 0.5 W per Tx element was implemented. Beamforming experiment was performed using the proposed algorithm. A received power of 45 mW at 2 m distance was achieved, which is very close to the simulated value.

This paper presents a wide-band multi-level switched mode class-E/F23 Power Amplifier (PA) with a reconfigurable power stage core transistor and a load with reconfigurable reactance compensation part. An Automatic Calibration Scheme (ACS) is proposed to perform the core and load reconfiguration based on a proposed algorithm. The PA is formed by a class-D driver amplifier, the switched mode cascaded reconfigurable power stage, the reconfigurable class-E/F23 load, the ACS and its algorithm, and the matching network at the end of the load before the antenna. The proposed PA is implemented using a 130 nm CMOS technology. The wideband PA operates in the frequency range from 470 MHz to 690 MHz for a TV White Space (TVWS) application with 220 MHz bandwidth. Even though reaching a high maximum Power Added Efficiency (PAEmax) for the design with low output powers is challenging a PAEmax of 32% for a 10 dBm output power level from a low supply voltage of 2.2 V. The proposed ACS provides an output power with a flatness around 0.6 dB which shows 57% improvement in compare with the structure without the ACS. The PA achieved a selectable multi-level output power from 10 dBm to 14 dBm over the 220 MHz bandwidth.

This paper presents a generalized expression of the modified load networks (MLNs) for Doherty power amplifiers (DPAs) with an extended output power back-off (OBO) range. Based on the analysis using this new expression, a new circuit structure generally applicable to any combination of the multiple MLNs is proposed. The load network has a simple structure including impedance matching circuits and offset lines for the carrier and peaking amplifiers. A design procedure for the proposed load network is presented. A DPA using any optimized combination of the multiple MLNs can be easily designed using the proposed load network. For verification, a GaN-HEMT symmetrical DPA based on a combination of the virtual open-stub (VOS) and out-phased current combining (OCC) methods was designed and implemented for the frequency band of 3.4 - 3.7 GHz. The reversed uneven power splitting method is adopted in the design for higher power gain. Using the 5G New Radio (NR) signal with a peak-to average power ratio (PAPR) of 7.9 dB and a signal bandwidth of 100 MHz, the proposed DPA exhibited DE of 55.3 - 60.9% with a power gain of 11.9 - 12.7 dB at an average output power of 33.7 dBm. An adjacent channel leakage power ratio (ACLR) of −42.6 - −44.8 dBc was achieved at the average power level by using a digital predistortion (DPD) technique across the band.

This paper presents an active rectifier design with a gate charge recycling technique. Gate switching increases the switching losses of the active rectifier, therefore, as a way to reduce switching losses, the gate charge recycling technique is proposed. The output power of 15 W is achieved to enable rapid charging using the three standards for wireless charging mode, magnetic induction (WPC and PMA), and magnetic resonance (A4WP). Power-sharing is used to lower the amount of power consumed by each standard mode core. In WPC, and PMA mode zero current sensing (ZCS) technique has been used while in the A4WP mode, the digitally controlled delay adjustment (DCDA) technique has been employed. By using a gate charge recycling block, the efficiency has been considerably improved due to the lower power consumption. It aims to increase the overall efficiency by reusing switching loss using the gate charge recycling block, and it has effectiveness by allowing three standard modes to operate with one single chip. The proposed design combines charge-recycling with zero current sensing techniques to improve power efficiency. The layout size is $4.75~\mu \text{m}^{2}$ . The achieved efficiency is 98.6 % in the magnetic induction method (WPC/PMA) at 15 W, and 94.86 % in the magnetic resonance method (A4WP) with an output power level of 15 W. The chip is fabricated in the BCD $0.18~\mu \text{m}$ CMOS process.

This paper presents a 5.8 GHz highly sensitive, high-dynamic-range RF receiver front-end with Automatic-Gain Control (AGC) and a high image-rejection for a Dedicated Short-Range Communication (DSRC) application. It is formed by a transceiver common matching, a single to differential Low-Noise Amplifier (LNA), an active mixer with an Image Rejection Filter, and an AGC unit. The proposed AGC unit is composed of a power-detector over the intermediate-frequency signals of the downconverter mixer. The power detector produces a wide dynamic range response signal, which eases the controllability of the AGC unit. In addition, external components are minimized, and area occupation is optimized. The proposed RF-FE is fabricated and measured in a 130-nm RF CMOS process. Experimental results show an overall dynamic range of 77.6 dB while a high sensitivity performance to an input power level of −85 dBm is measured. An overall gain of 26.4 dB for the RF-FE is obtained. The input referred P1dB is measured to be around −28.3 dBm. The 2-stage RC poly-phase filter that is applied to reject the image signal results in a maximum image rejection ratio of 39 dB.

The load network of the carrier amplifier for the conventional Doherty power amplifier (DPA) consists of an impedance matching circuit, an offset line, and a $\lambda $ /4 transmission line (TL), so that the overall electrical length of the network can easily exceed the minimum value of 90°. Then for appropriate impedance modulation, it should be 270° with an additional 180°. This excessive electrical length of the load matching network limits the bandwidth at either the low-power or peak-power level. In this paper, a compact quasi-lumped $\lambda $ /4 impedance transformer (ITF) having simultaneous multiple functions of impedance matching and load impedance modulation with a controlled electrical length of 90° is presented. The proposed load network includes the internal components of the transistor, the simplest high-pass network using a shunt inductor, and a low-pass L-C network. Using the optimized value of the shunt inductor, the electrical length of the load network can be adjusted to 90°, while other components are accordingly changed to match the optimum load impedance. To verify the proposed load network, a DPA was designed and implemented using 10 W GaN-HEMTs for both carrier and peaking amplifiers. Using a 5G New Radio (NR) signal with signal bandwidth of 100 MHz and peak-to-average power ratio (PAPR) of 7.8 dB, a drain efficiency (DE) of 47 - 54.2%, and adjacent channel leakage power ratio (ACLR) of −27.9 - −23 dBc were achieved at an average output power level of 35.8 - 36.3 dBm for the frequency band of 3.4 - 3.8 GHz.

In this article, we present the design of a low-profile circularly polarized (CP) magneto-electric (ME) dipole antenna with enhanced CP bandwidth properties. The ME dipole antenna is excited by a simple microstrip line aperture-coupled feeding structure. The coupling aperture is composed of two crossed slots of unequal lengths to realize CP operation. Four identical inverted $L$ -shaped parasitic elements, each consisting of a horizontal patch and a vertical metallic plate, are vertically positioned around the ME dipole. It was found that such parasitic elements can remarkably improve the 3 dB axial ratio (AR) bandwidth while retaining the wide impedance bandwidth. A prototype with a low profile of only $0.134\lambda _{L}$ ( $\lambda _{L}$ is the wavelength in free space at the lowest operating frequency) is fabricated and tested to verify the proposed design. The experimental results show that the prototype has an overlapping impedance bandwidth ( $|S_{11}| \leq -10$ dB) and a 3 dB AR bandwidth of 3.16–5.36 GHz (51.35%) with a maximum broadside left-handed CP gain of 9.75 dBic. Additionally, nearly identical radiation patterns on two principle cutting planes are obtained over the operating band.

A double-layer element consisting of a spider-shaped structure on the top layer and a pair of concave arms with a circular ring on the middle layer is proposed for the wideband reflectarray with low cross-polarization characteristics. The unit cell offers a linear and wider phase range of 800∘. Based on the proposed unit cell, an offset-fed reflectarray with an octagonal aperture comprising 6769 unit cells is constructed at 11.725 GHz. The reflectarray offers 1 dB and 3 dB gain bandwidths of 25.2% and 32.3%, respectively, with an operating frequency range of 10–13.85 GHz. A peak gain of 31.2 dBi with an aperture efficiency of 42% is achieved. The cross-polarization levels are less than the co-polarization by 40 dB over the entire operating band.

This paper presents a high-efficiency wireless power transfer (WPT) system that can charge multiple receivers (Rx’s) of various types. For system analysis, the transmitted power and received power levels are derived using the parameters of the resonators based on electro-magnetic (EM) resonance. Using the analysis results, the power customized resonator (PCR) not only for deriving sufficient output power from the transmitter (Tx) but also for appropriately distributing the received power to the various and multiple Rx’s is proposed. In addition to the PCR, the Tx unit is designed to work as a load-dependent voltage source using a differential Class-E power amplifier (PA) through a wide range of load impedances. Therefore, the Tx can naturally adapt to the required Tx power levels with a high efficiency corresponding to various Rx configurations without additional tunable circuits or adaptive control schemes. The WPT system, including the load-dependent voltage source for the Tx, full-bridge rectifiers for the Rx’s, and the proposed PCR, was designed for the 6.78 MHz frequency band. The proposed system is validated for use with multiple mobile devices by conducting experiments with nine charging cases using three types of Rx’s. For all cases, high system efficiencies of 70.7–85.5% were maintained over received power levels of 8.6–45.7 W at a charging distance of 30 mm, and each of the three types of Rx’s were experimentally verified to receive sufficient power.

In this paper, a new technique for circular polarization in a slot coupled dielectric resonator antenna is proposed. The circular polarization is generated by inserting the two annular vias into dielectric resonator slightly off the diagonal position. In addition to the circular polarization, the proposed technique increases the total realized gain by 1.62 dB as compared to the via-less case on the account of increased directivity while maintaining the same aspect ratio of the DR. To validate the design, a prototype is fabricated and measured. The measured results show that the proposed circularly polarized dielectric resonator antenna has a −10 dB reflection bandwidth of 7.29% (3.3–3.55 GHz) and a 3 dB axial ratio bandwidth of 5.5% (3.28–3.465 GHz) with a measured RHCP gain of 6–7.1 dBic. The measured curves of the S11, axial ratio, and the RHCP gain results are in good agreement with the simulated results.

This paper presents a low-profile magneto-electric (ME) dipole antenna with an enhanced impedance bandwidth realized by the loading of shorting parasitic elements. The antenna contains a horizontal planar electric dipole antenna, a $\Gamma $ -shaped shorted patch antenna, a pair of parasitic L-shaped shorted patches, and a direct feed. By loading of the parasitic L-shaped patches such that they are shorted to the ground, the proposed antenna attains a significant bandwidth enhancement while maintaining excellent broadside radiation characteristics. An antenna prototype with a low profile of only $0.11\lambda _{0}$ was fabricated and tested ( $\lambda _{0}$ is the free-space wavelength referring to the center frequency). The antenna achieves a measured impedance bandwidth of 75.64% (1.34–2.97 GHz) for a voltage standing wave ratio (VSWR) of less than 2. Within the operating band, the measured gain ranges from 6.23 to 8.49 dBi. Additionally, stable radiation patterns on both E- and H-planes with a high front-to-back ratio of more than 20.5 dB are achieved.

In this paper, a method for calculating the received power in a radio-frequency wireless power transfer system with array antennas is proposed. The received power is derived based on the superposition of the electric fields that radiate from individual transmitter (Tx) elements and are captured by each receiver (Rx) element. That is expressed in a finite series form with the radiation patterns of an element considering mutual coupling in the array and corresponding distances between the elements of Tx and Rx. Unlike conventional methods (such as the Friis and Goubau formulas), this approach is able to calculate the received power precisely in both Fresnel and far-field regions. It is also efficiently applicable to various cases, such as those involving beamforming and with varying positions of Rx. The calculated results using this method are applied to a 5.2 GHz WPT system with array antennas and verified through comparisons with both simulation and experimental results.

The microwave power transfer (MPT) system requires a massive Tx array for building a focused radio wave to efficiently transfer power to the Rx. Beamforming IC is one of the core elements for the massive Tx array. This paper presents a 5.8 GHz 4-channel beamforming Tx IC based on a CMOS process. The beamforming Tx IC includes a resistive 4-way power splitter, 5-bit differential phase shifters, drive amplifiers, and power amplifiers. Each channel is designed to transmit a power of no less than 100 mW. To verify the Tx IC, a 16-channel beamforming Tx module based on 16 patch antennas and four 4-channel Tx ICs was designed. The module also includes a PLL, a frequency doubler, and a 4-way Wilkinson power divider. MPT experiments to verify the beamforming IC and module were carried out using the implemented 16-channel Tx module at 5.8 GHz. Received power levels of 13 dBm and 2.1 dBm were achieved at distances of 0.4 and 1.4 m, respectively. The results are almost similar to the values acquired from the calculation using the Friis equation.

In this study, a rectenna is adopted in a microwave-based wireless power transfer system to rectify the received radio frequency (RF) to DC power. Each rectenna comprises a DC-DC converter at the DC output port to ensure a stable power supply and a Schottky diode for the DC-combining network. The results indicate that the RF-DC conversion efficiencies of the rectifier circuit and $4\times 1$ rectenna were 71% and 71.2% when the unit-cell RF input levels were 19 dBm and 19.6 dBm, respectively. Furthermore, the DC output levels of a $4\times8$ rectenna with and without the DC-DC converter were 28 V and 30 V, respectively, when the unit-cell RF input level was 20.2 dBm. Additionally, the RF-DC conversion efficiencies were 52.6% and 59.9% with and without the DC-DC converter, respectively. Thus, we experimentally verified that the Schottky diode combined with the DC-DC converter at the DC output port can increase the DC power combining level, making it suitable as an extendable array rectenna system.

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC’s channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator’s offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.

This article presents a hybrid envelope tracking (ET) supply modulator (SM) integrated circuit (IC) based on a Class-AB linear amplifier (LA) with supply voltage and temperature insensitive quiescent current. For ET mode, to further improve efficiency of the ET-SM, the supply voltage of the LA can be modulated using an additional dc-dc converter according to the average output power. An adaptive quiescent current controller for the LA of the ET-SM is proposed to maintain its quiescent current for large variations in voltage and temperature. Due to the insensitive quiescent current over the voltage of the LA, the supply voltage to the LA can be controlled in a wider range for the average output power, which allows the power amplifier (PA) in the ET mode to have a greater improvement in efficiency. The size of the output stage of the LA is also discretely reconfigured using 3-bit digital control to reduce the power consumption of the LA according to the output power level. For the low average output power levels, the operation mode is changed to APT mode, which supplies a reduced dc voltage according to the reduced average output power to the PA. The proposed SM, dc/dc converter and PA ICs were designed and implemented using CMOS processes for 0.9 GHz LTE application. Using an LTE uplink signal with a signal bandwidth of 5 MHz and a PAPR of 7.5 dB, a PAE of 38.4% at an average output power of 24.0 dBm was obtained under an ACLR of −30.0 dBc for the overall ET-PA. At a 6 dB back-off for the average output power, a PAE of 24.6% was achieved using the ET mode. A maximum PAE improvement of 8.0% point using the proposed SM IC was achieved compared to the stand-alone PA.

This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the need for Time-to-Digital Converter (TDC) is eliminated through providing the CFTL circuitry. This feature makes the design compact, low power, and suitable for IoT applications. The proposed design is based on a synthesizable pulse injection and frequency-locked loop along with an ultra-low-power LC Digitally-Controlled Oscillator (LC-DCO). The presented CFTL circuit adjusts the frequency of the DCO continuously and prevents the frequency drift after the reference injection. Inside the designed LC-DCO core, the power consumption is minimized by optimizing the $\text{g}_{\mathrm {m}}~/\text{I}_{\mathrm {D}}$ and adjusting the power supply to 0.5 V. The proposed ILFM based ADPLL is fabricated in 55 nm CMOS technology and covers the operational frequency range of 2.402 GHz to 2.480 GHz with a reference frequency of 32 MHz. The measured phase noise performance of the ADPLL is −111.15 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.4 GHz. It consumes only 0.46 mW power with an active area of 0.129 mm2.

A compact single-fed circularly polarized dielectric resonator antenna (DRA) with an enhanced 3-dB axial ratio bandwidth (ARBW) and gain is proposed. The DRA is implemented by joining a smaller dielectric resonator (DR) to one side wall of a main rectangular DR and is excited by an offset vertical metallic strip. With this configuration, two sets of degenerate orthogonal modes, the TE111 mode and TE113 mode, are simultaneously excited to realize wideband circular polarization operation. Furthermore, by removing a small DR portion from the lower corner of the main DR, the boresight gains at higher frequencies are significantly enhanced. An antenna prototype is fabricated and measured to verify the performance of the proposed design. The experimental results illustrate that the proposed antenna achieves a measured 3-dB ARBW of approximately 44.73% (3.68-5.80 GHz) in conjunction with a broad -10 dB impedance bandwidth of 69.66% (2.9-6.0 GHz). The measured boresight gain is found to be 5.49± 0.85 dBic within the passband with a maximum value of 6.34 dBic at 4.7 GHz. Moreover, reasonable agreement between the simulated and measured results is achieved.

In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the target channel, it adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power and constant current DCO operates in sub-threshold region and its power consumption is minimized by gm/ID methodology optimization, constant current source for limiting current in DCO core through adaptive low-dropout regulator (LDO) and lowering the supply voltage. The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is 1800 μm2 with 1.233 K gate count. The RMS current consumption is 103.32 μA from 1 V voltage supply with 103.32 μW power requirement. The experimental results reveal, DCO draws 480 μA current from 0.55 V supply voltage at center frequency. It has frequency resolution of 4.8 kHz. The oscillator PN, FOM and FOMT at 1-MHz offset frequency from 2.44 GHz carrier frequency are -122.85 dBc/Hz, 196.38 dBc/Hz and 208.19 dBc/Hz, respectively.

This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (lowpower) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from -18 dBm to -5 dBm, maintaining 13-dB input power range with peak PCE of 33% at -8 dBm for 200 kΩ load resistance. The proposed circuit demonstrates -20.2 dBm sensitivity across 1 MΩ load resistance while producing 1 V output DC voltage.

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (VCM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is 45 μW when operated at 1 V power supply.

In this paper, a high performance adaptive digital low-dropout voltage regulator (ADLDO) is proposed for Internet-of-Things (IoT) applications. In the proposed ADLDO, a fully synthesizable adaptive digital controller is designed. It automatically senses load variations and adaptively controls multi-loop architecture to reduce quiescent current, minimize output voltage ripples and achieve fast transient response. The multi-loop architecture with hill climbing reduces the total bi-directional shift registers length which results in the reduced leakage current in the transistor-switch-array (TSA), and improves the recovery time and output DC voltage accuracy. A dithering technique is introduced to eliminate the limit cycle oscillation (LCO) and improve the performance of the regulator. The dynamic frequency scaling (DFS) mechanism is proposed for reducing controller power consumption in steady state. In order to reduce the offset and output voltage error, a dynamic latch comparator is utilized. When the input supply voltage is varied from 0.5 V to 1 V, the measured output voltage ranges from 0.45 V to 0.95 V with 50 mV dropout voltage. The operating frequency is 10 MHz with fast transient response and quiescent current of 350 ns and 3.7μA, respectively. The maximum measured power and current efficiencies are 89.7 % and 99.97 %, respectively, with 1.9 mV output voltage ripples. Measured load and line regulations are 2.2 mV/mA and 9.5 mV/V respectively. The proposed circuit is implemented in 28 nm CMOS process and occupies 0.016 mm2 chip area.

This paper presents a look-up table (LUT)-based focal beamforming system that can effectively transmit RF power up to mid-range distances (≤ 3 m) including when the Rx is in the near-field zones. The Tx elements control and radiate signals for the Rx even at the near-field zone ensuring the received signals are in-phase. Since the proposed system uses a LUT for storing the phase sets of the signals for the Tx elements, it requires only very simple hardware and a very simple adaptive control algorithm compared to conventional retroreflective method. In order to track the moving Rx, a 2-D adaptive sequential searching algorithm is proposed. The system can find the optimum phase set by sequentially searching the phase sets for a pre-determined 2-D area. The LUT of the phase sets are generated using geometric analysis over the entire 2-D area where the Rx could be located. To verify the proposed method, a 5.2 GHz mid-range (≤ 3 m) MPT system composed of a 4 × 8 Tx array and a 2 × 3 Rx array was designed and implemented. Using the proposed 2-D adaptive sequential searching algorithm, the optimum phase set for focal beamforming can be quickly found for a given position of the Rx. In our experiments, the results showed an RF power level of 177.8 mW was received at the Rx with a distance of 1 m with a total radiated RF power of 16W. Since the measured received power levels for various Rx positions agree well with the simulation results, the proposed system was proved to be an excellent candidate for the practical application.

A co-design consisting of a filtering antenna integrating a cavity-backed patch antenna and a low-pass coaxial filter is proposed for size reduction of the RF front-end. The cavity-backed patch antenna is developed to exhibit a broad impedance bandwidth and a unidirectional radiation pattern. The low-pass coaxial filter is implemented to suppress harmonic resonances and gain in the stop-band of the antenna and is embedded directly inside the antenna cavity to realize a compact small-footprint co-designed filtering antenna structure. Two prototypes of the proposed filtering antennas, which integrate cavity-backed patch antennas with 4th and 5th order low-pass coaxial filters and with the overall dimensions of 0.697λ0 × 0.585λ0 × 0.236λ0 and 0.697λ0 × 0.585λ0 × 0.320λ0 (where λ0 is the free space wavelength at 3.15 GHz), respectively, are fabricated and measured. The experimental results show fractional bandwidths of 25% and 23.8% and gain suppression levels exceeding 11 dB and 22 dB in the stop-bands for the filtering antennas with the 4th and 5th order filters, respectively. The measured gain is more than 6.5 dBi in the pass-band for both filtering antennas. In addition, excellent agreement is obtained between the simulated and measured results.

This paper presents a low-cost, low-sidelobe-level, differential-fed, substrate-integrated waveguide (SIW)-based slot array antenna with zero beam squint. The antenna consists of two identical six-way unequal power dividers (PDs) and a 6 × 16 slot array and is realized on a single-layer substrate. The six-way unequal PD provides tapered amplitude and in-phase excitation for six SIWs, and each of them has 16 radiating slots. The 1 × 16 linear slot array on each SIW is excited using a differential feed to avoid undesired beam squinting across its operating band. A two-way hybrid waveguide (WG)-to-SIW E-plane PD is developed to provide equal amplitude and out-of-phase excitation for two six-way unequal power dividers. Moreover, metallic decoupling walls are implemented between two adjacent linear slot arrays to reduce E-plane external mutual coupling. An antenna prototype is fabricated and experimentally verified. The fabricated antenna shows that the measured −10 dB reflection bandwidth is 7.15% (9.57–10.28 GHz), with the achieved gain ranging from 20.30 to 21.92 dBi. A stable boresight beam is observed over the entire operating band. Furthermore, at the designed frequency of 10 GHz, peak SLLs of −29.1 dB and −29.4 dB are achieved in the E- and H-plane, respectively.

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 mm2, 0.063 mm2, 0.045 mm2, and 0.03 mm2 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.

This paper presents a broadband gallium-arsenide pseudomorphic high-electron-mobilitytransistor (GaAs pHEMT) power amplifier integrated circuit (PAIC) based on a dual-frequency selective impedance matching technique for warfare applications. For a broadband PA design, lower and upper-frequency corners where serious performance degradation is likely to occur should be carefully considered. Feedback and resistive biasing circuits were adopted for driver and main stages to making their frequency responses as flat as possible. Optimum impedances of not only extended lower and upper-frequency corners but also center frequency, were then extracted. Such dual-frequency selective impedance matching technique was applied for extended lower and upper-frequency corners while checking the mismatch level for the center frequency. The proposed broadband PAIC for frequency band from 6 to 18 GHz was designed using a 0.15 μm GaAs enhanced-mode pHEMT (E-pHEMT) process. The implemented broadband PAIC with a simple two-stage structure had a very small chip size of 1.19×0.82 mm2. It exhibited a power gain of more than 16.4 dB and output power of 19.2 dBm. Very flat characteristics in power gain and an output power within ±1.0 dB through the whole band were achieved.

This paper presents a two-stage stacked power amplifier integrated circuit (PAIC) for broadband and high efficiency using a 2-μm InGap/GaAs HBT process with a second-harmonic control circuit and a bias-switching circuit for an average power tracking (APT) application. For APT operation, active bias circuits with a bias switching circuit for the stacked stage were proposed. A simple L-section matching network with a second-harmonic termination circuit was adopted for broad bandwidth and high efficiency. The frequency-independent power and efficiency contours for fundamental and second-harmonic frequency band were extracted at the current-source plane of the transistor. The implemented two-stage PAIC was evaluated using a long-term evolution signal with a peak-to-average power ratio (PAPR) of 7.5 dB and a signal bandwidth of 10 MHz. From 1.55 to 1.95 GHz, the power amplifier exhibited average output power ranging from 27.4 to 28.5 dBm, a power gain of more than 28.6 dB, and a power-added efficiency (PAE) of 36.5 to 41.2% at an ACLR of -30 dBc. At an average output power back-off of 5 dB, the PAE improved to 29.5% with APT using an external buck-boost dc-dc converter, while it was 18.7% without APT.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

This paper presents the manufacturing procedure and electrical properties of a microstrip line on flexible printed circuit boards (FPCBs) fabricated using the micro pattern transfer printing (MPTP) method for millimeter wave band application. The MPTP method presented herein is compared to the conventional FPCB process based on the degree of insertion loss as it pertains to the cross-sectional shape of the formed microstrip line. Electromagnetic field simulations were performed to confirm that the cross-sectional arch shape fabricated by the MPTP process reduces insertion loss in the high-frequency band. Based on the simulation, the microstrip transmission line was optimized to a width of 217 µm and a length of 30 cm, fabricated on a 50 µm thick poly-cyclohexylene dimethylene terephthalate (PCT) substrate to measure the insertion loss. The insertion loss fabricated using the MPTP method is measured as 0.37 dB/cm at 10 GHz, while the conventional FPCB is measured as 0.66 dB/cm. Through the analysis, it was confirmed that the FPCBs manufactured by the MPTP process show lower insertion loss compared to the conventional FPCBs.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of −10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and −11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is −11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed a synthesizable RTL-based CNN architecture for this purpose. The adopted technique of parallel computation of multiplication and accumulation (MAC) approach optimizes the hardware overhead by significantly reducing the arithmetic calculation and achieves instant results. While multiplier bank sharing throughout the convolutional operation with fully connected operation significantly reduces the implementation area. The CNN model is trained in MATLAB® on MNIST® handwritten dataset. For validation, the image pixel array from MNIST® handwritten dataset is applied on proposed RTL-based CNN architecture for biosensor applications in ModelSim®. The consistency is checked with multiple test samples and 92% accuracy is achieved. The proposed idea is implemented in 28 nm CMOS technology. It occupies 9.986 mm2 of the total area. The power requirement is 2.93 W from 1.8 V supply. The total time taken is 8.6538 ms.

In this article, a high gain and compact 4 × 4 circularly polarized microstrip patch antenna array is reported for the data transmission of the next-generation small satellite. The radiating element of the circularly polarized antenna array is realized by the conventional model of the patch with truncated corners. A compact two-stage sequential rotational phase feeding is adopted that broadens the operating bandwidth of the 4 × 4 array. A small stub is embedded in the sequential rotational feed, which results in better performance in terms of the S-parameters and sequential phases at the output ports than sequential rotational feed without open stub. A prototype of the array is fabricated and measured. Fulfilling the application requirements of the next-generation small satellites, the array has the left-handed circularly polarized gain of more than 12 dBic with the axial ratio level below 1.5 dB in the ±10∘ angular space with respect to the broadside direction for the whole bandwidth from 8.05 GHz to 8.25 GHz. Moreover, the left-handed circularly polarized gain varies from 15 to 15.5 dBic in the desired band. The radiation patterns are measured; both the co- and X-pol are validated.

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

In this paper, a dual-band RF wireless power transfer (WPT) system with a shared-aperture dual-band Tx array antenna for 2.4 and 5.8 GHz is proposed. The final configuration of the Tx array, which is made up of 2.4 GHz right-handed circular polarization (RHCP) patches and 5.8 GHz RHCP patches, is derived from the optimization of 2.4 and 5.8 GHz thinned arrays, ultimately to achieve high transmission efficiency for various WPT scenarios. The dual-band RF WPT Tx system including the Tx array antenna and a Tx module is implemented, and Rx antennas with a 2.4 GHz patch, a 5.8 GHz patch, and a dual-band (2.4 and 5.8 GHz) patch are developed. To validate the proposed dual-band RF WPT system, WPT experiments using a single band and dual bands were conducted. When transmitting RF wireless power on a single frequency (either 2.482 GHz or 5.73 GHz), the received power according to the distance between the Tx and Rx and the position of the Rx was measured. When the distance was varied from 1 m to 3.9 m and the transmitted power was 40 dBm, the received power value at 2.482 GHz and 5.73 GHz were measured and found to be 24.75–13.5 dBm (WPT efficiency = 2.985–0.224%) and 19.25–6.8 dBm (WPT efficiency = 0.841–0.050%), respectively. The measured results were in good agreement with the calculated results, and it is revealed that the transmission efficiency when wireless power is transmitted via beam-focusing increases more than that with conventional beam-forming. Furthermore, the dual-band WPT experiment proves that 2.482 GHz beam and 5.73 GHz beams can be formed individually and that their wireless power can be transmitted to a dual-band Rx or two different Rx.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

This paper proposes a class-F synchronous rectifier using an independent second harmonic tuning circuit for the power receiver of 2.4 GHz wireless power transmission systems. The synchronous rectifier can be designed by inverting the RF output port to the RF input port of the pre-designed class-F power amplifier based on time reversal duality. The design of the class-F power amplifier deploys an independent second harmonic tuning circuit in the matching networks to individually optimize the impedances of the fundamental and the second harmonic. The synchronous rectifier at the 2.4 GHz frequency is designed and implemented using a 6 W gallium nitride high electron mobility transistor (GaN HEMT). Peak RF-dc conversion efficiency of the rectifier of 69.6% is achieved with a dc output power of about 7.8 W, while the peak drain efficiency of the class-F power amplifier is 72.8%.

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

In the above article [1], the received power in dc referred from the reference [2], which is the reference [35] in the original article [1], was incorrectly introduced. It was written as 0.2 W (dc) in the introduction of [1], but the correct received power in the specified condition is 2 W (dc).

This paper presents an adaptive control and communication protocol (ACCP) for the ultra-low power simultaneous wireless information and power transfer (SWIPT) system for sensor applications. The SWIPT system-related operations depend on harvested radio frequency (RF) energy from the ambient environment. The necessary power for SWIPT system operation is not always available and it depends on the available RF energy in the ambient environment, transmitted RF power from the SWIPT transmitter, and the distance from the transmitter and channel conditions. Thus, an efficient control and communication protocol is required which can control the SWIPT system for sensor applications which mainly consists of a transmitter and a receiver. Multiple data frame structures are used to optimize the exchange of bits for the communication and control of the SWIPT system. Both SWIPT transmitter and receiver are capable of using multiple modulation schemes which can be switched depending on the channel condition and the available RF energy in the ambient environment. This provides support for automatic switching between the time switching scheme and power splitting scheme for the distribution of received RF power in the SWIPT receiver. It also adjusts the digital clock frequency at the SWIPT receiver according to the harvested power level to optimize the power consumption. The SWIPT receiver controller with ACCP is implemented in 180 nm CMOS technology. The RF frequency of the SWIPT operation is 5.8 GHz. Digital clock frequency at the SWIPT receiver can be adjusted between 32 kHz and 2 MHz which provides data rates from 8 to 500 kbps, respectively. The power consumption and area utilization are 12.3 µW and 0.81 mm².

In this paper, an extremely low-profile ferrite dipole antenna operating on the VHF band (30−300 MHz) is proposed. The design antenna consists of 44 plate-type ferrite cells arranged into two stacked ferrite layers: a bottom ferrite layer with 2 × 12 grid cells and a top ferrite layer with 2 × 10 grid cells. The antenna is excited by an electric loop feeding structure and maximum gain performance is achieved when the loop feeding structure has five loops. To validate the performance of the proposed antenna, an antenna prototype is fabricated and tested at an outdoor range. The antenna weighs 1.45 kg and has electrical dimensions of approximately 0.0636 × 0.0112 × 0.0008 λ L 3 at the lowest operating frequency of 30 MHz. The measured realized gain varies from −31.48 to −2.44 dBi within the VHF band. Reasonable agreement is also obtained between the measurement and simulation results. To assess the performance of the proposed antenna, it was mounted on the integrated mast of an offshore patrol vessel (OPV) model. The antenna on the OPV was also simulated and the results discussed.