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In this letter, we investigate the effect of Carbon (C) doping concentration on dynamic RON, vertical leakage and Capacitance-Voltage (C-V) characteristics of p-GaN gate High Electron Mobility Transistors (HEMTs). Measurements performed on state-of-the-art samples show that further increasing C-doping concentration in the GaN buffer above $10^{{19}}$ cm $^{-{3}}$ yields a reduced dynamic-RON degradation, in contrast with the behavior reported in the literature for lower C-doping concentrations. This is confirmed by a complete data set showing a consistent increase in the vertical leakage and in the output capacitance while increasing the C doping, stemming from a less insulating buffer and a reduced 2-DEG depletion, respectively. These observations can be attributed to an increased incorporation of compensating donors leading to a reduction of the net acceptors as the C doping concentration is raised above $10^{{19}}$ cm $^{-{3}}$ .

Dynamic on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}{)}$ affects the stability of p-GaN power HEMTs. In Schottky-gate HEMTs, dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is associated to either electron trapping at device surface or dynamic effects occurring in the buffer. However, in p-GaN HEMTs the floating p-GaN region can have an additional role on dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ , due to removal/injection of holes from/into the barrier with relatively long time constants, which can be erroneously interpreted as a reliability issue. In this letter, we present a model to explain the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ due to surface-related effects in p-GaN power HEMTs. The model, called ‘hole virtual gate’, attributes the experimentally observed ${R}_{ \mathrm{\scriptscriptstyle ON}}$ instability due to negative/positive gate bias stress (NGS/PGS) to the charging/discharging of surface traps in the AlGaN barrier by the removal/injection of holes through the gate metal/p-GaN Schottky junction. We verify the validity of the model by means of calibrated numerical simulations, that correlate the activation energy ${E}_{\text {A}}~\approx ~0.4$ eV of both ${R}_{ \mathrm{\scriptscriptstyle ON}}$ increase/decrease during NGS/PGS to the thermal ionization energy of traps in the barrier.

In this article, we present an analysis of the correlation between interface traps (ITs) and border traps (BTs) on distinctive features of ${C}$ – ${V}$ curves in vertical Al2O3/gallium-nitride (GaN) MOS capacitors. First, pulsed ${C}$ – ${V}$ curves were characterized during the application of quiescent gate bias stresses of different magnitudes and signs. This characterization revealed four main distinctive features: 1) rightward rigid shift; 2) leftward rigid shift; 3) decrease of the $\Delta {C}$ – $\Delta {V}$ slope; and 4) formation of a hump in a gate bias range before the accumulation of electrons at the oxide/semiconductor interface. By means of a combined experimental/simulation analysis, these features were univocally attributed to specific ITs or BTs in the overall trap distribution. The simulation-aided analysis enhances the physical understanding of the ${C}$ – ${V}$ curves features and increases the dependability of the adopted IT measurement technique, allowing for a more rapid process optimization and device technology development.

Application of gallium nitride high-electron-mobility transistors (GaN HEMTs) to millimeter-wave power amplifiers requires gate length scaling below 150 nm: in order to control short-channel effects, the gate-to-channel distance must be decreased, and the device epitaxial structure has to be completely redesigned. A high 2-D electron gas (2DEG) carrier density can be preserved even with a very thin top barrier layer by substituting AlGaN with AlN, InAl(Ga)N, or ScAlN. Moreover, to prevent interaction of hot electrons with compensating impurities and defects in the doped GaN buffer, the latter has to be separated from the channel by a back barrier. Other device designs consist in adopting a graded channel (which controls the electric field) or to adopt nitrogen-polar (N-polar) GaN growth (which decreases the distance between gate and channel, thus attenuating short-channel effects). The aim of this article is to review the various options for controlling short-channel effects, improve off-state characteristics, and reduce drain–source leakage current. Advantages and potential drawbacks of each proposed solution are analyzed in terms of current collapse (CC), dispersion effects, and reliability.

We discuss the degradation mechanisms of C-doped 0.15- $\mu \text{m}$ gate AlGaN/GaN HEMTs tested by drain step-stress experiments. Experimental results show that these devices exhibit cumulative degradation effects during the step-stress experiments in terms of either (i) transconductance ( $g_{\mathrm{ m}}$ ) decrease without any threshold-voltage ( $V_{\mathrm{ T}}$ ) change under OFF-state stress, or (ii) both $V_{\mathrm{ T}}$ increase and $g_{\mathrm{ m}}$ decrease under ON-state stress conditions. To aid the interpretation of the experiments, two-dimensional hydrodynamic device simulations were carried out. Based on the obtained results, we attribute the $g_{\mathrm{ m}}$ decrease accumulating under OFF-state stress to hole emission from CN acceptor traps in the gate-drain access region of the buffer, resulting in an increase in the drain access resistance. On the other hand, under ON-state stress, channel hot electrons are injected into the buffer under the gate and in the gate-drain region where they are captured by CN traps, leading to $V_{\mathrm{ T}}$ and $g_{\mathrm{ m}}$ degradation, respectively.

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, high-speed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field.

In this letter, we investigate the on-resistance (RON) instability in p-GaN power HEMTs induced by a positive or negative gate bias ( ${V}_{\text {GB}}$ ), following the application of a quasi-static initialization voltage ( ${V}_{\text {GP}}$ ) of opposite sign. The transient behavior of this instability was characterized at different temperatures in the 90–135 °C range. By monitoring the resulting drain current transients, the activation energy as well as time constants of the processes are characterized. Not trivially, both RON increase/decrease were found to be thermally activated and with same activation energy. We attribute the thermal activation of both (RON) increase/decrease to the charging/discharging of hole traps present in the AlGaN barrier in the region below the gate.