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Conventional hysteresis current controllers have the disadvantage of a variable switching frequency. This paper presents a novel hysteresis current control method which uses the adjacent current error zero-crossing time to calculate the upper/lower hysteresis bandwidth after the measured half current error period. This strategy makes the algorithm independent of load parameters and thus it can achieve a stable switching frequency. An improved switching scheme has been successfully applied to a single-phase three-level H-bridge voltage source inverter driving a vibration test bench based on the novel hysteresis current. It can select appropriate switching states to overcome dead-time effects without dead-time compensation according to the relation of the current switching state, the current error, and the upper/lower hysteresis bandwidth. Field-programmable gate array has enough computational power to allow multiple sampling within a current error period and logic control power to implement state machine transitions. The simulation and experimental results are given to demonstrate the validity and features of the novel hysteresis current controller with the improved switching scheme.

A novel main circuit topology of transformer-less series voltage sag compensator is proposed. The sagged voltages are compensated by half bridge inverters, which are directly connected in series with the residual voltages and are charged by the residual line-to-line voltages. The proposed compensator can compensate symmetrical three-phase sags down to 37%, or one or two phase sags down to zero if at least one phase is rated voltage. Besides the excellent compensation property related to the compensating depth, the proposed system only need small capacitance in the inverters because they are continuously charged by the residual voltages during the sags. In fact the capacitors are not energy storers but filters, so there is no limit on their compensating time interval. Theoretical analysis is done and the concerned results are derived. Simulation results on resistance loads demonstrated the compensating performances.

Conventional hysteresis controllers have a major disadvantage of a variable switching frequency. This paper presents a variable hysteresis control method for implementing multilevel modulation of multilevel inverters with constant switching frequency, by using the current error zero crossing time to calculate the hysteresis bands in a switching period. This strategy makes algorithm independent of load parameters, and can be adapted to multilevel inverter with double-band and slope detection. Simulation results confirm the effectiveness of the proposed approach.

Voltage sags are an important power quality problem. Enhancing compensating capability is the key technique in voltage sag compensators. In this paper, a transformer-less series voltage sag topology without energy storage capacitors is proposed first. This topology is cost-effective by eliminating the large injection transformer and energy storage capacitors that are used in conventional series injection devices. This topology can both be used in three-phase three-line and three-phase four-line systems, and can compensate symmetrical three-phase voltage sags down to 37%, or one or two phase sags down to zero if others at least one phase is rated. Secondly, this paper proposes and illustrates a new compensation control strategy which combines energy optimal control with time optimal control to enlarge the compensating time and draw a minimum amount of energy from the compensator during sags. And then, an asymptotically angle rotation method is proposed to avoid sudden phase jump of the load-side voltage. Simulation results demonstrate the good features.

Digital system exhibits better accuracy, stability, flexibility, and anti-noise property than analog scheme. Among various existent PWM principles natural sampled PWM (NPWM) is the best one in aspects of the harmonic distortion, attenuation, and time delay of the base-band modulating signals. So the best PWM implementing scheme would be a fully digital implemented scheme based on the natural sampled PWM principle. In this paper a universal digitized naturally sampled PWM (DNPWM) scheme was studied. The pulse width errors of DNPWM output compared with the NPWM output were theoretically analyzed in detail, which are caused by the finite sampling period TADC, the word length nADC in analog-digital conversion (ADC), and digital clock period T0 of the digital system. A set of equations of pulse width errors with respect to various system parameter were derived. The redundant pulses caused by the step effects of sampling and quantization in ADC and quantization in digital carrier, which is inevitable, were analyzed in detail too, and a method to eliminate the redundant pulses is presented. To Cancel redundant pulses would bring about additional pulse errors, which had also been analyzed. Finally, simulation research gave statistical results that demonstrate the validity of the analysis in this paper, and experimental results are given too.