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This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm² core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7-6.6 dB at dc-28 GHz and the rms amplitude and phase errors of four measured chips are

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The $\pi $ -type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole–zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5–8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm2 core area and consumes negligible power.

This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP $_{\mathrm {1\,dB}}$ ) at 9 GHz from −12.2 to −5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than −14 dB. This chip occupies $1.44\times0.68$ mm2 area excluding pads and consumes 75 mW.

A true-time-delay-based (TTD-based) receiver front end with 800-ps time delay for 6.5–9-GHz wideband phased arrays has been designed for satellite communication in a 65-nm CMOS technology. The proposed receiver front end consists of a balanced low-noise amplifier (LNA), a 6-bit attenuator with 15.75-dB tuning range, a programmable TTD element featuring 800-ps delay with 25-ps delay step, and an output buffer amplifier. A differential origami inductor is proposed to boost the delay unit’s quality factor and mitigate the insertion loss introduced by the artificial transmission line (ATL). A current-mode radio-frequency (RF) multiplexer is designed to ensure a rapid delay switching. The receiver front end demonstrates a 3.6-dB noise figure (NF) with an 18-dB typical gain and an input 1-dB compression point (IP1dB) of −17 dBm at 6.5–9 GHz. This TTD element allows for a low insertion loss and a small chip area per unit time delay of ATL-based RF TTDs.

Phased arrays have demonstrated great potential in 5/6G communication, radar and sensor applications [1– 4]. To achieve excellent performance, phased arrays require low-noise and high-linearity front-ends [5]. Most importantly, arrays demand uniform performance from all elements for optimum receiving G/T value and transmission effective isotropic radiated power (EIRP) [6]. Figure 14.7.1 exemplifies it with an array whose antenna element has 3dBi uniform gain on one side and no radiation on the other side. When all elements in an $8 \times 1$ linear array with a $\lambda/2$ space have identical characteristics, the array presents a 19dBi gain in the normal direction. Any temperature change in the array can be decomposed into an absolute temperature change superposed with a relative temperature variation. When the absolute temperature increases, the frontend gain decreases by as much as $-0.1dB/^{\circ}C$ [1]. When there is non-uniform solar radiation or heat generation inside the array, the relative temperature variation may present a gradient or a parabolic distribution. Taking a $64 \times1$ array as an example, when there is a gain/phase mismatch with an average value of $0.125dB/1.25^{\circ}$ between adjacent elements in a parabolic distribution locating at the center of the array, the formed beam presents a 1.4dBi main-lobe reduction in the normal direction and an 11.9dBi side-lobe degradation, shown in Fig. 14.7.1. It also shows an active array receiver front-end highlighting all the temperature-sensitive blocks. Calibration can adjust temperature-dependent performances [7]. However, periodic calibration inevitably takes time overhead and prevents array systems from full-time operations. Digital background calibration allows systems to operate uninterrupted, but may induce antenna boresight instability due to abrupt gain/phase change. In contrast, analog background calibration like adaptive healing design can resolve the above issues [8]. In this paper, we present an adaptive analog temperature healing receiver front-end with ± $0.005 dB/^{\circ}C$ gain variation from -15 to $85^{\circ}C$ environment temperature for a 17.7-to-19.2GHz phased array.

This paper presents a 4-element 7.5-9 GHz phased array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. All the elements are fully-connected to each output beam using 32 phase shifters and 8 active combiners. The current-starving gm-based phase shifter with 6-bit phase resolution achieves

This paper presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy from DC to Ka band, designed and fabricated in a 55-nm CMOS technology. Staggered π-type and bridge-T type stages with capacitive compensation are proposed to minimize amplitude and phase errors, and to extend its operation bandwidth. The chip demonstrates a 32.385-dB attenuation range with a 0.255-dB attenuation step and a 3.5-8.4 dB IL across DC to 32 GHz. The measured RMS amplitude and phase errors are below 0.32 dB and 5.33° respectively. The die occupies 0.054 mm2(0.632 mm × 0.086 mm) core area and consumes negligible power. To the best of our knowledge, this work shows the smallest area and the widest bandwidth among the reported switch type attenuators.

This paper presents a wideband balanced variable-gain low-noise amplifier (VGLNA) implemented in a 55-nm CMOS process. A frequency-selective non-foster gain equalization technique is proposed to compensate the gain variation of interstage dual-resonant tanks. This VGLNA leverages current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1dB) at 9 GHz from -12.2 dBm to -5 dBm. The LNA achieves a maximum power gain of 20.2 dB with ±0.5 dB gain variation and a minimum noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Owing to lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 mm × 0.68 mm area without pads and consumes 75 mW.