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A 5-to-0.4 $\sim $ 1.2-V reconfigurable capacitive-sigma dc– dc converter with 98.4% peak efficiency is presented. By input-series and output-shunt an efficient unregulated 2:1 switched-capacitor (SC) converter with a reconfigurable hybrid Dickson Buck converter, the proposed converter achieves high efficiency for the entire output voltage and current ranges. Besides, the proposed converter also demonstrates decent regulation and transient responses. The prototype achieved 98.4% and 90.4% peak efficiency at 1.2- and 0.4-V output, respectively. The output shows a static error of 1.1 mV and under-/overshoot voltages of –23 and 23.8 mV with 0.1% settling time of 25 and 30 $\mu \text{s}$ , respectively, over 2-A load range. Compared with the prior state of the arts, the converter improves the peak efficiency by 1.5% at voltage conversion ratio (VCR) = 4.2 and by 4.9% at VCR = 12.5.

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance ( ${Z} _{\mathbf {in}}$ ) boosting. In order to achieve a high ${Z} _{\mathbf {in}}$ , a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors ( ${C} _{\mathbf {in}}$ = 0.5 pF, ${C} _{\mathbf {fb}}$ = 25 fF) are used with a biased pseudo-resistor ( ${R}$ = 2.5 $\text{G}\Omega $ ) fed back to an amplifier internal node. As a result, a high achievable ${Z} _{\mathbf {in}}$ and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF ${C} _{\mathbf {amp}}$ is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its ${Z} _{\mathbf {in}}$ boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/ $\surd $ Hz, and an integrated noise of $0.85~\mu $ Vrms in 200 Hz band. The ${Z} _{\mathbf {in}}$ is boosted to 1.92 $\text{G}\Omega $ at DC and 1.02 $\text{G}\Omega $ at 50 Hz with only $1.0~\mu \text{A}$ in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming $20.3~\mu \text{W}$ in total.

This article presents a 15-bit pseudo-pseudo-differential (PPD) incremental zoom analog-to-digital converter (ADC). It employs two single-ended (SE) 3-bit successive-approximation-register (SAR) ADC and a third-order SE incremental $\Delta \Sigma $ ADC to process a pair of differential input signals. A novel three-phase clock helps eliminate the half-cycle delay between the positive and the negative input sampling, boosting this work’s common-mode-rejection ratio (CMRR). Fabricated in 55 nm CMOS technology, the ADC achieves a measured 89.9 dB signal-to-noise ratio (SNR) in a conversion time of 0.378 ms while consuming only $1.07 \mu \text{W}$ from a 1 V supply. This corresponds to a Schreier figure-of-merit (FoM) of 180.8 dB.

This article presents a fully dynamic 2–0 multistage noise-shaping (MASH) analog-to-digital converter (ADC) for low-power and high-precision applications. It implements the feedforward digitally with a 3-bit asynchronous successive-approximation-register (SAR) ADC and reuses it as the zeroth backend stage. Correlated level shifting (CLS) boosts the floating inverter amplifier (FIA) gain, embedded in the loop filter to implement integration. Dynamic body-biasing (DBB) technique helps boost the gain of a single-stage FIA with only one reservoir capacitor. Fabricated in 55-nm CMOS technology, the prototype ADC achieves measured SNDR of 94.0 and 96.9 dB dynamic range (DR) in 1-kHz BW at an oversampling ratio (OSR) of 125 while only consuming $2.87~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 179.4 dB and a DR-based FoM of 182.3 dB.

A 15-bit self-timed incremental analog-to-digital converter (ADC) for event-driven applications is presented. It is based on an asynchronous zoom ADC structure and a fully differential self-timed dynamic-amplifier (DA)-based integrator. Dynamic element matching (DEM) and chopping techniques mitigate the mismatch and noise. Measurements show that the ADC without oversampled clock achieves 93-dB SNR in a conversion time of 0.37 ms while consuming only 4.96- $\mu \text{A}$ current from a 1-V supply. This corresponds to a Schreier FoM of 177.3 dB. The 0.23-mm2 chip was fabricated in a standard 55-nm CMOS process.