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Among the various faults of power transformers, winding faults are particularly common. It is known that short‐circuit parameters can reflect the winding condition, so the on‐line identification of short‐circuit parameters is of great significance for monitoring the power transformer health. An instantaneous phasor extraction method based on Second‐Order Generalised Integrator Frequency‐Locked Loop is introduced, and then an on‐line identification algorithm of power transformer short‐circuit parameters based on an instantaneous phasor is proposed. In this algorithm, multi second‐order generalised integrator frequency‐locked loop is used to extract the fundamental instantaneous phasors of the voltage and current signals on the primary and secondary sides of the transformer. After that, the short‐circuit parameters are calculated from the phasor equation of the transformer. The effectiveness of the proposed algorithm has been verified with experimental results. [ABSTRACT FROM AUTHOR]

Multiple second-order generalized integrators (MSOGI) has been widely used to extract the signal that contains multiple harmonics. The MSOGI needs to be implemented in the discrete-time domain for its practical applications. More critically, the discretization method can greatly affect its performance. The existing discretization methods for MSOGI can be divided into three categories: entire transfer-function discretization, SOGI-transfer-function discretization, and integrator discretization. The theoretical analysis indicates that the first method can avoid the errors caused by unit delay, but it is hard to be digitally realized for high-order transfer functions. The other two methods have nonnegligible errors in both the phase and the quadrature characteristic due to the unit delay. In this letter, we propose a novel discretization method by modifying the structure of integrator discretization. This method can enhance the performance in both the phase and the quadrature characteristic with an acceptable computation burden, which has been theoretically analyzed and experimentally verified. [ABSTRACT FROM AUTHOR]

In a three-phase three-level grid-connected inverter, the ac output current ripple actually fluctuates four times per switching period with each fluctuation generating some core loss. However, only the two larger fluctuations are considered in most loss estimation methods, resulting in a smaller core loss evaluation. In this letter, an alternative method has, hence, been proposed, beginning with the deduction of fundamental and ripple equivalent circuits from the inverter. These circuits permit current ripple to be calculated, from which its four fluctuations are all considered for forming the dual current-ripple envelopes (DCREs). These DCREs, together with the fundamental current and a selected core loss model, can then be solved to give the estimated fundamental and ripple core loss values. The nonlinear characteristic of the filter inductor has also been considered in the calculation of the DCREs and the core loss. The estimated values have eventually been verified through testing with a 10-kW three-phase T-type three-level grid-connected inverter. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]

Accurate flux estimation is essential for the implementation of a high-performance ac motor drive. However, it still faces some problems, which can better be projected by analyzing performances of existing flux estimators, implemented with either a pure integrator or a low-pass filter (LPF). To solve the problems, an alternative flux estimator, implemented with a single second-order generalized integrator (SOGI) and a frequency-locked loop (FLL), is discussed for induction motor drives. The SOGI block included in this algorithm works for integrating the back-electromotive force, which unlike the pure integrator and LPF, does not experience saturation and significant dc offsets caused by different initial conditions. The single-SOGI-FLL estimator does not need additional magnitude and phase compensation, while its performance may deteriorate at low speed, caused by the inverse proportional relationship between its estimated flux and the frequency. A multi-SOGI-FLL flux estimator is, thus, proposed for uncompromised attenuation of dc and harmonic errors even under low-speed condition. Excellent flux estimation can, hence, be offered over the full-speed range, as proven through theoretical studies and experiments. [ABSTRACT FROM AUTHOR]

A Neutral Point Clamped (NPC) type three-level inverter has the advantages of a low switch voltage and a high-quality output waveform. However, there are inherent problems, such as neutral point potential asymmetry and common mode interferences, which easily affect the symmetry of the three-phase output voltage and the safe operation of the inverter. Firstly, according to the different modulation degrees, the fluctuation of midpoint potential can be suppressed by adding an action time correction factor to the traditional space vector pulse-width (SVPWM) modulation strategy and virtual space vector pulse-width (VSVPWM) modulation strategy, respectively. Secondly, considering the suppression of common mode voltage, a new virtual space vector pulse-width (NVSVPWM) modulation strategy is proposed, which uses a set of new vector synthesis methods. Finally, the simulation and experiment prove that the NVSVPWM strategy with an action time correction factor can suppress the fluctuation of the neutral point potential and common mode voltage at the same time, and the effect is significant. [ABSTRACT FROM AUTHOR]

The carrier-based pulse width modulation (CBPWM) with zero-sequence component injection is equivalent to the space-vector PWM (SVPWM), and hence it can be taken as a simplified alternative to the SVPWM. However, it is quite complex to calculate the zero-sequence component in CBPWM for three-level (3L) converters such as the T-type converter, making the 3L SVPWM still have a large computation burden. In this letter, unified expressions for the zero-sequence component are analytically derived, and the modulation waves of 3L SVPWM can be directly calculated by only 7 simple equations with 3 steps. The computation burden for implementing 3L SVPWM is therefore significantly reduced without sector determination, calculation and assignment of dwell times. [ABSTRACT FROM AUTHOR]

No dead-time is contained in the existing dead-time elimination pulsewidth modulation (PWM) for three-phase three-level T-type converters, where complementary drive pulses are allocated alternatively according to polarities of output currents. Consequently, the dead-time effect can be inherently avoided. However, the dependency on current polarities seriously limits its widespread application. Wrong current polarities, e.g., in a dynamic process, will lead to the output-voltage disappearance, thus aggravating the possible “algebraic loop” issue and impairing the stability of the system. In this article, in order to reduce the dependency on current polarities while retaining the characteristic of dead-time-effect elimination, a double-modulation-wave PWM is proposed by modifying the dead-time elimination PWM. Two modulation waves with a magnitude difference are adopted for generating underlap periods between complementary drive pulses, which can avoid the shoot-through failure and no dead-time effect will be generated. And to further simplify the implementation process, the two modulation waves are decomposed by introducing a magnitude-adjustment factor related to the current polarity. Whereas it is also due to the employment of two modulation waves, extra issues of overmodulation, single drive pulses, and a shorter underlap period may occur, which are analyzed in detail and the negative effect can be avoided. Finally, the proposed PWM is experimentally verified, showing the effectiveness on harmonic suppression and the reduced dependency on current polarities. [ABSTRACT FROM AUTHOR]

Given the high complexity of the conventional three-level space-vector pulsewidth modulation (3L SVPWM), simplified SVPWM algorithms are usually adopted instead. However, existing simplifications for 3L SVPWM still have a large computation burden, which limits its applications, e.g., in high-switching-frequency silicon-carbide converters with a short computation period. In this letter, based on a typical simplified algorithm known as the center-aligned 3L SVPWM, a simplified analytical algorithm in abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only eight simple equations, without sector determination, calculation, and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced. [ABSTRACT FROM AUTHOR]