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A novel Lateral Double-Diffused MOSFET (LDMOSFET) with ultra-low resistance is investigated by experiments. The proposed LDMOSFET features an extended gate field plate consisting of two back-to-back diodes. In the ON state, the electron accumulation layer is formed below the gate field plate and greatly reduces the resistance of the drift region. In the OFF state, the field plate assists in depleting the drift region and modulates the electric field distribution of the drift region, which ensures high breakdown voltage (BV). The key fabrication process steps for the proposed device are given. The fabricated prototype device shows specific on-resistance ( ${R} _{{\text {on},\text {sp}}}$ ) of 70 $\text{m}\Omega \cdot $ cm2 and BV of 680 V, which is superior performance for reported 600 V-rated lateral devices. The ${R} _{{\text {on},\text {sp}}}$ of the proposed LDMOSFET is decreased by 50% compared with the LDMOSFET without accumulation effect.

In this paper, we present a lateral injection enhanced insulated gate bipolar transistor (LIEGT) and investigate its mechanism. The LIEGT features a recessed trench at the cathode side of the drift region formed by LOCal oxidation of silicon (LOCOS) process. The recessed trench suppresses holes being extracted and enhances the electron injection, thus contributing to a very low loss in the ON-state. The ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the LIEGT is reduced by 24% at the current density of 200 A/cm2 and the saturation current is 40% higher than that of the conventional lateral insulated gate bipolar transistor (LIGBT). The LIEGT exhibits an improved tradeoff between ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and turnoff loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). For the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is decreased by 38% compared with that of the conventional LIGBT.

A novel split triple-gate (STG) LDMOS is proposed to improve static-state and switching performances. The proposed structure features a triple-gate and split gates (SGs). The triple-gate consists of planar part and trench part, and the SGs are embedded into the drift region and isolated with slanted oxide. The triple-gate enlarges the channel width. Furthermore, the trench part of triple-gate and trench drain–source contributes to a uniform on-state current density distribution from the surface to the bottom of the drift region, resulting in a high average current density. Consequently, the specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ) and the transconductance are improved. In the off-state, the SGs act as a slanted field plate to not only modulate the electric field distribution, but also assist in depleting the drift region to increase the optimal doping concentration, which further decreases the ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ and maintains a high BV. Moreover, the SG is introduced to reduce the gate–drain capacitance and switching power dissipation. Compared with the triple-gate LDMOS (TG LDMOS), the STG LDMOS not only reduces the ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ by 66%, but also decreases the gate–drain charge by 41%.

A 600-V snapback-free fast-switching silicon-on-insulator lateral insulated gate bipolar transistor with an embedded self-biased n-MOS (SBM) is proposed and investigated by simulations. The proposed device features an n-MOS which consists of the N+ anode, p-layer, N-buffer, and the anode trench gate (ATG) embedded between the P+ anode and N+ anode. It is worth noting that the ATG is driven by the anode, without any additional control circuits. At the initial conduction stage, p-layer/N-buffer junction acting as electron barrier contributes to snapback-free with a reduced cell pitch. Simultaneously it provides an extra built-in path to extract electrons at the turn-OFF stage, which hence reduces the turn-OFF energy loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ) and increases the switching speed. Furthermore, the hole leakage current of the SBM LIGBT in the blocking state is suppressed due to the electron accumulation/inversion formed along the sidewall of the ATG, avoiding triggering the P+NP transistor and thus increases the breakdown voltage by 11% in comparison with that of the conventional LIGBT. Simulation results show that the SBM LIGBT reduces ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ by 31% and 43% compared to the conventional LIGBT with the same on-state voltage drop ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ), at the load current of 100 and 200 A/cm2, respectively.

A novel carrier stored (CS) SOI lateral insulated gate bipolar transistor (LIGBT) with ultralow on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and high current capability is proposed and its electronic performance is investigated by simulation. The device features the CS layer and the trigate (TG) structure, named TGCS LIGBT. The CS effect in the on-state delivers an ultralow ${V}_{ \mathrm{\scriptscriptstyle ON}}$ . The TG is employed to increase the channel density and modulate the current distribution, further reducing the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and achieving high current capability. Moreover, TG assists in depleting the highly doped CS layer, which enhances the conductivity modulation and maintains high breakdown voltage. The extended P+ in the comb-shaped P+ region provides a low-resistance hole current path, and thus enhances the latch-up immunity. At the same turn-off loss, the TGCS LIGBT reduces the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ by 32.5% and 36.4% compared with the tridimensional channel (TC) LIGBT and the conventional (Con). LIGBT, respectively. The TGCS LIGBT exhibits high current capability, which has an improvement of 151% and 26.8% compared with those of the Con. LIGBT and the TC LIGBT, respectively. The TGCS LIGBT shows a little better short-circuit capability than does the Con. LIGBT.

A novel ultralow specific on-resistance ( $R_{\mathrm{\scriptscriptstyle ON},\text {sp}})$ SOI lateral double-diffused MOS (LDMOS) with three separated gates (TSGs) and high- $k$ (HK) pillars is proposed and investigated by simulation. The TSGs include the planar gate ( $G_{X}$ ), the segmented trench gate ( $G_{Y})$ between the p+ body contact regions, and the embedded trench gate ( $G_{Z}$ ) connected with HK pillars and p-well regions. First, in the on-state, the TSGs form three channels, including one lateral channel and two vertical channels, which can decrease $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ significantly. Second, $G_{Y}$ and $G_{Z}$ are extended to the buried oxide, widening the vertical conduction area and enhancing the current density in the bulk to further reduce $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ . Furthermore, the electron accumulation layer (EAL) is formed not only beside the extended $G_{Y}$ and $G_{Z}$ , but also along the sidewall of the drift region near the source side, thus reducing $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ greatly. Third, the HK pillars can increase the optimal drift doping concentration ( $N_{d})$ to decrease $R_{\mathrm{\scriptscriptstyle ON},{\mathrm{ sp}}}$ owing to the assisted depletion effect. The device obtains an ultralow $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ of 0.34 $\text{m}\Omega \cdot {\mathrm{ cm}}^{2}$ at BV = 97 V. Compared with the conventional LDMOS and other previous devices, the TSG-HK LDMOS achieves better tradeoff between the breakdown voltage and $R_{\mathrm{\scriptscriptstyle ON},\text {sp}}$ .