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The microstructure of epitaxially grown self-assembled Ge islands on patterned SiO2/Si substrates was analyzed using high resolution transmission electron microscopy. The Ge islands were grown by molecular beam epitaxy on hexagonally ordered Si hole arrays with ∼25 nm diameter and ∼40 nm center-to-center distance, which are covered by 30 nm thick SiO2 mask layer patterned using self-assembled diblock copolymers. The Ge islands nucleate preferentially at the edge of overetched Si surface, and subsequently grow selectively on Si surface as opposed to SiO2 surface with increasing coverage. The lattice planes of some Ge islands are tilted from those of Si substrates. This is believed to be the reason for the observed misalignment of moiré fringes. The diameter of the Ge islands is identical to that of Si holes for large Ge coverage due to the selective growth behavior. These islands are found to have dislocations at the interface with the Si substrate. These results highlight the important microstructural issues and growth behavior of quantum dots on patterned substrates. [ABSTRACT FROM AUTHOR]

Based on projections of the International Roadmap for Semiconductors (ITRS), the continued scaling of complementary metal-oxide semiconductor (CMOS) devices will face severe technical challenges. Among the most critical are power dissipation and device-level variabilities that will make circuit design very difficult. Potential device-level solutions that take advantage of new functional materials, serf-assembly processes, low dissipation nanoscale devices, and architectures that aim in sustaining Moore's law beyond the ITRS are discussed in this paper. Two potential paths forward are clear at this point. One path is to continue increasing chip-scale functional throughput by looking at new functional materials at atomic and molecular levels for assembly into new low-power devices with different logic state variables that can better tolerate variabilities. Another distinct approach is to increase chip-scale functionality by exploiting the heterogeneous integration of materials, such as compound semiconductors on silicon as enabled by the unique features in nanoscale epitaxy and self-assembly on a common substrate. This paper will discuss some possible methods forward in maintaining scaled CMOS and going beyond the roadmap. [ABSTRACT FROM AUTHOR]

Direct integration of III-V compound semiconductor (GaAs) on silicon (Si) substrates has been demonstrated using selective epitaxy on patterned substrates. GaAs was grown directly on patterned (001), (011), and (111) Si substrates covered with 60 nm thick thermally grown SiO(2). After growth, GaAs crystals with both dot and wire shapes show preferred {011} facets. GaAs grown on particular wire patterns which are parallel to {011} surfaces shows uniform nanowire structure. Transmission electron microscopy shows dislocation-free GaAs with low density of anti-phase domain boundaries along [111] directions. Metal-oxide-semiconductor structures with aluminum oxide as gate dielectric were fabricated using GaAs nanowires on Si. Capacitance-voltage measurements show clear inversion and accumulation.