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Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (

This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output power ( $P_{\mathrm {out}}$ ) and high power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce a new transformer-based series output combiner design method to achieve a true-Doherty load modulation that uses a compact footprint. The output stages of the main PA and the auxiliary PA (aux. PA) both use a differential three-stacked FET topology for high output power without posing a reliability issue. The intermediate-node matching is achieved by using a shunt inductor for voltage waveform alignment and efficiency improvement. A modified differential quadrature hybrid is proposed to achieve the desired quadrature power splitting function without the need for an input balun. For the proof of concept, the proposed PA is implemented in a 22-nm CMOS fully depleted silicon-on-insulator (FD-SOI) technology with a core area of 0.2 mm2. At 28 GHz, the measured saturated output power ( $P_{\mathrm {sat}}$ ), 1-dB output compression point (OP1dB), and peak power-added efficiency (PAE) are 22.5 dBm, 21.1 dBm, and 28.5%, respectively. State-of-the-art International Technology Roadmap for Semiconductors (ITRS) figure-of-merit (FOM) and power density are achieved. The measured PAE at 6-dB PBO is 22.1%, which results in an efficiency enhancement ratio of 1.56/3.12 with respect to an ideal class-B and class-A PA. The proposed PA can support 2.4-Gb/s 64-quadratic amplitude modulation (64-QAM) and 0.8-Gb/s 256-QAM signal with a competitive average PAE. Excellent device reliability is validated by operating the implemented PA under 3-dB gain compression point for 12 h with less than 0.06-dB $P_{\mathrm {out}}$ variation. The proposed Doherty PA with a compact footprint is suitable for the integration purpose of future 5G multiple-input multiple-output (MIMO) and phased-array applications.

The recently released CENDL-3.2 nuclear data library is deemed as an important achievement in the field of nuclear data research in China. To verify the applicability of the library to the shielding calculation of PWR and analyze the influence of multigroup cross-section parameters on the shielding calculation, ARES-MACXS module is used to process the MATXS format multigroup library based on CENDL-3.2 to generate multigroup working cross sections for PWR shielding calculation. VENUS-3 experimental facility has a clear and complete geometry. It is often used to test the ability of the advanced transport calculation method of calculating RPV fast neutron flux and to evaluate the accuracy of cross-section library. Different cross-section parameters are chosen for ARES to calculate VENUS-3 benchmark, and equivalent neutron flux of 58Ni(n,p)58Co, 115In(n,n′)115mIn and 27Al(n,α)24Na detectors is calculated according to the data provided by the benchmark report. The numerical results demonstrate that almost all the relative deviations between the calculated results and the experimental results are within 20%, which satisfies the requirement of shielding calculation. CENDL-3.2 is suitable for PWR shielding calculation. The comparison of various cross-section parameters results indicates that multigroup cross-section parameters have large effects on the transport calculation results.

This paper presents a D-band front-end module (FEM) with an integrated transmit/receive (T/R) switch in 22-nm fully-depleted silicon on insulator (FD-SOI) CMOS technology for beyond-5G communication. The asymmetric T/R switch topology with intrinsic ESD protection leverages the Tx- and Rx-mode RF performance. Both the PA and LNA have a differential topology with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics, especially at the antenna port. The adopted stacked-FET PA achieves a high output power while consuming much less area than a PA based on passive power combining. At 140 GHz, the Tx achieves a power gain $G_{p}$ of 33.6 / 35.7 dB, a saturated output power Psat of 12.5 / 14.7 dBm, a peak power-added efficiency PAE of 10.8 / 11.3%, and output 1-dB compression point (OP1dB) of 9.4 / 11.2 dBm with nominal/boosted supplies. At 140 GHz, the Rx achieves a 20-dB $G_{p}$ , a −24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA / LNA core area of 0.024 / 0.032 mm2, respectively.

This paper presents a 39 GHz front-end module (FEM) in 22 nm FD-SOI technology for 5G communications. The PA output stage uses a 2-stacked FET topology to achieve high output power. A two-way current combiner is used to combine output power from the output stage while maintaining a uniform waveform distribution over each transistor unit cell to enhance the device reliability. The LNA consists of two stages to obtain high power gain with low power consumption. Derivative-superposition (DS) with a common-mode inductor is used to improve the LNA linearity. The measured P sat and PAE max in TX mode are 20.4 dBm and 25.6%, respectively. The measured NF and IIP3 in RX mode are 5.7 dB and −13 dBm, respectively. A Pout, avg of 13.5 dBm and a PAE avg of 10.6% is achieved in 64-QAM 400 MSym/s single-carrier at EVM rms of −25 dB for TX-mode.

This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology for the fifth generation (5G) wireless communication. The design adopts a gain-boosting technique that is comprehensively analyzed with a transformer-based stacked-FET power amplifier (PA). Then, the co-design of the transmit/receive (T/R) switch with the PA and low-noise amplifier (LNA) is investigated, and an electrostatic-discharge (ESD)-aware T/R switch incorporating PA circuitry is proposed to leverage the Tx- and Rx-mode performance. Moreover, the robustness of standalone PA and Tx-mode FEM is simulated and experimentally verified. Furthermore, the ground return paths and supply parasitic paths of the adopted single-ended LNA together with the proposed T/R switch are studied, properly simulated, and assessed. Finally, the proposed PA topology is first verified standalone, exhibiting 32-dB power gain (Gp), an 18.2-dBm output 1-dBcompression point (OP1 dB), and a 31.1% power-added efficiency (PAE) at OP1 dB (PAE1 dB). Using this PA in the FEM yields a Tx-mode OP1 dB/PAE1 dB of 16 dBm/19.4%, and an average output power (Poutavg)/PAE of 10.1 dBm/8.3% for a 100-MHz bandwidth 256-QAM single-carrier signal at an error-vector magnitude (EVM) of -30 dB. In the Rx mode, noise figure (NF) and input-referred third-order intercept point (IIP3) are 3.2 and -5.4 dBm, respectively. A 2-kV human-body model (HBM) ESD protection of the FEM is predicted in transient simulations and measured with transmission line pulse (TLP) tests.

Millimeter-wave beamforming transmitters use antenna arrays to increase the EIRP by focusing the radiation pattern into a direction chosen by programming the TX phase shifters. However, under sharp scanning angles, the antennas load each other (see Fig. 26.4.1) such that in each antenna path the load seen by an individual PA in the output matching network (OMN) deviates from the load corresponding to boresight transmission. This situation can be accompanied by other external factors, such as antenna blockage, that increase VSWR. To restore the PA performance under increasing VSWR conditions, one can use a tunable matching network (TMN) that is controlled by the observed VSWR. The latter is then measured by a VSWR sensor, which is presented here. The overhead of such a sensor in terms of form factor, power consumption, and TX performance degradation should be minimal. The sensor described here can measure reflection coefficients with a magnitude of up to 0.7 (corresponding to a VSWR of 5.7) at 28GHz. It detects the complex voltage difference over a 235fF sensing capacitor that is inserted in the signal path at the PA output. The magnitude and phase of this voltage vary with the complex reflection coefficient $\Gamma$ and are detected separately. The loading effect of the rest of the sensor can be modelled as a 32fF shunt capacitor added to the matching network, equivalent to an extra insertion loss of less than 0.2dB.

This paper presents a Doherty power amplifier (PA) in 22nm FD-SOI for achieving high output power and high backoff efficiency for 28GHz 5G communications. The output stage of the main PA and the auxiliary PA both use a stacked-FET topology for high output power without posing a reliability issue. A dedicated transformer-based output matching network is proposed to achieve a true Doherty load modulation while maintaining a compact layout. The PA is fabricated in a 22nm FD-SOI technology with a core area of 0.2mm2. At 28GHz, the measured saturated output power (P sat ), 1dB output compression point (P 1dB ), and peak power-added efficiency (PAE) are 22.5dBm, 21.1dBm, and 28.5%, respectively. State-of-the-art ITRS figure-of-merit (FOM) and power density are achieved. The measured 6dB power back-off (PBO) PAE is 22.1%, which results in a PBO enhancement ratio of 1.56/3.12 with respect to a class-B/class-A PA. The proposed PA can support 2.4Gb/s 64-QAM and 0.8Gb/s 256-QAM signal with a competitive average PAE.

This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoM $_{T}$ of −191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoMRMS of −239 dB. Its frequency acquisition time improves from 780 to 45 $\mu \text{s}$ with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to −35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).

We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (P SAT ) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm2, Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P 1aB ) is 19.1 dBm. Measured PAE at P 1dB and 6dB power back-off are 23% and 10.3%, respectively.

While it is known that the charge-carrier mobility in amorphous metal oxide semiconductor thin film transistors (TFT) deviates from Arrhenius temperature dependence, we found that the Hall mobility measured in amorphous In-Ga-Zn-O (a-IGZO) follows an Arrhenius relation surprisingly well. We explain these observations by the effect of strong vertical electric field created by the gate voltage, which facilitates direct tunneling of trapped carriers into the conductive band and leads to virtually temperature independent mobility. We present a generalized Arrhenius model based on the effective temperature concept. We show that our model allows quantitative description of the temperature dependence of the mobility in a-IGZO TFTs over a broad temperature range.

This paper presents a 23GHz low-phase-noise transformer-feedback differential VCO with a 27% frequency tuning range. By adding a source-bridging capacitor between the sources of the transistors that are connected to the two feedback transformers, the phase noise at $1/ f^{3}$ region is improved due to the suppression of flicker noise up-conversion. The proposed VCO is implemented in a 22nm FD-SOI technology with a low supply voltage of 0.65V. The measured phase noise is −106 dBc/Hz at lMHz frequency offset with power consumption of 11. 5mW, and the corresponding FOM and FOM T are 182.6 dBc/Hz and 191 dBc/Hz, respectively.

An improved cut-off frequency model of a modified equivalent circuit of graphene field-effect transistors, which incorporates the additional capacitive effect physically present due to dipole layer between the metal and the graphene, is proposed. The original equivalent circuit is not accurate for a large separation distance dipole layer. Based on the improved equivalent circuit model, a more accurate parameter extraction by two-port analysis is possible, and the cut-off frequency will be more accurate particularly for largely separated dipole layer near the Dirac point. Considering the dipole layer, the equivalent circuit is never investigated before, and the cut-off frequency model shows good agreement with experiments.

In this paper, a surface potential-based gate-leakage current (GLC) model for organic thin-film transistors is proposed. It is found that the Poole–Frenkel emission is the main mechanism of GLC, which can be well described by our model for both accumulation and depletion modes. In addition, the source and drain partitions of the channel leakage current can be well explained based on our model. Furthermore, the dependence of GLC on drain voltage, temperature, and material disorder has been discussed in detail, which yields perfect agreement with the experimental data.

For the first time, we present a surface potential-based compact model for a-IGZO TFTs based on multiple trapping-release theory and benchmark our work against device measurements. This model does not require time-consuming calculation. Meanwhile, we have developed the automatic parameter extraction program, which can extract the parameters rapidly and accurately. Moreover, the compact model is coded in Verilog-A, and implemented in a vendor CAD environment. This model provides physics-based consistent description of DC and AC device characteristics and enables accurate circuit-level performance prediction and RFID circuit design of a-IGZO TFTs.

Resistive switching memory (RRAM) with three-dimensional (3D) integration is one of the most effective methods to satisfy the requirement of ultra-high density and ultra-large data storage. With the increase of the integration density of 3D RRAM, Joule heating effect and thermal crosstalk of the RRAM device will seriously affect the stability, reliability and life of RRAM device. Therefore, the biggest challenge for 3D RRAM is how to solve the problem of the thermal effect. Otherwise, the thermal effect will be particularly prominent as the feature size of RRAM device is ceaselessly decreased. Especially with the improving of the storage cell densities and hence the decreasing of the distance between adjacent cells, the thermal crosstalk from the adjacent cells will seriously restrict the development and application of 3D integrated RRAM. In this work, we present a new electro-thermal compact model for 3D RRAM arrays. The proposed model is based on the electro-thermal analogy which can couple thermal network to its electrical schematic. The comparison between the compact model simulation results and numerical simulation shows a good accuracy. This proposed model can be used to predict temperature distribution and analyze thermal crosstalk in 3D RRAM arrays. Our work will provide a reliable technical support for the late circuit design and practical application, and lay the foundation for the realization of the high-density 3D integration RRAM.