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Summary: The present study is devoted to articulating a modified folded‐cascode circuit, to make folded‐cascode structures an attractive configuration as a transimpedance amplifier (TIA) for being employed in Giga‐bit per second optical communication receiver systems. Giga‐bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes folded cascodes comparable to the famous regulated cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5 Gbps up to 8 Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65 nm CMOS validate the suitability of the modified circuit as a TIA. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µArms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper, describes a CMOS trans-impedance amplifier (TIA) and Limiting Amplifier (LA) for 2.5Gb/s, low-power opto-electronic communication receiver systems. The single ended TIA, which benefits form active type of inductors, is designed and simulated using 0.18µm CMOS process parameters. The proposed circuits are analyzed mathematically and all necessary simulations for proving the proper performance of the proposed TIA stage and the proposed LA stage such as eye-diagram, MONTECARLO and noise analysis are done. Simulation results in HSPICE show the transimpedance gain of 45.5dBO, frequency bandwidth of 1.85GHz and power consumption of 1.1mW at 1.5V supply for the TIA stage and 87dB gain and 2GHz frequency bandwidth for the whole receiver system, which consumes only 7.3mW power. Results indicate that the proposed circuits are suitable to work as a low-power building block as optoelectrical communication receiver. [ABSTRACT FROM AUTHOR]

In this paper, a one-bit ultra-low-power full adder cell using GDI structure is proposed. Main objective of this design is not only providing low power consumption, but also providing full swing outputs. In this paper, combination of different logics and stacking technique are used to provide an ultra-low power cell. Also, by using stacked inverters after each function, full swing characteristic for the cell is obtained. These characteristics are obtained in cost of more occupied chip area and higher delay. In order to verify the performance of the proposed cell, simulations are done in HSPICE using 90nm CMOS technology library. Beside Noise immunity, power consumption is also analyzed under different load conditions, different supply voltages and different temperatures. Although delay of the circuit is increased, results show a tremendous reduction in power consumption and an improved power-delay-product for the proposed full adder cell. [ABSTRACT FROM AUTHOR]

In this paper, a two-stage 5Gbps transimpedance amplifier (TIA) for an optical communication receiver system is presented. The presented TIA uses a regulated cascode configuration (RGC) as the input stage, which benefits from low input resistance, and is followed by a gain stage with negative feed-back network and a buffer stage in order to provide extra gain to operate properly at 5Gbps. DC operating point stabilizing is also considered in this paper. The proposed TIA is discussed mathematically and related simulations are performed in HSPICE using 0.18µm CMOS technology parameters. Results for the proposed TIA show the transimpedance gain of 42.1dBΩ, bandwidth of 3.6GHz, and power consumption of 12mW at 1.5V supply voltage. Also, Monte-Carlo analysis, noise analysis and effect of temperature variation on frequency response of the TIA are analyzed, which indicate that the proposed TIA is suitable to work as a 5Gbps TIA building block in an optical communication receiver system. [ABSTRACT FROM AUTHOR]

In this paper, an optical communication receiver system for 5Gbps applications is proposed concerning power consumption. An inductor-less circuit in three-stages is proposed as the trans-impedance amplifier (TIA), which benefits from the inherent low input resistance of a common gate topology as the first stage. By forming two zeros in this TIA, proper frequency response is obtained while the DC current is reduced. In order to obtain extra gain for the receiver system, three stages of conventional limiting amplifier (LA) are used. In order to verify the circuit performance, the proposed receiver is simulated in HSPICE using 90nm CMOS technology parameters. The receiver is mathematically studied and is matched with the simulations. This paper conducts the simulations, such as eyediagram, noise analysis and fabrication process analysis (Monte-Carlo). The proposed Trans-Impedance Amplifier shows 53.9dbΩ gain, 3.5GHz bandwidth, 15.2pA/√Hz and only 1.52mw power consumption for 1.2v supply voltage, and the receiver system shows 90.9dbΩ, 3.5GHz bandwidth and 6.34mw power consumption (for 2 stages of TIA and 3 stages of LA) for 1.2v supply voltage. Results indicate that the proposed receiver is suitable to work as a low-power 5Gbps optical communication receiver system. [ABSTRACT FROM AUTHOR]