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In this work, a single active element (Extra-X Current Controlled Conveyor) with grounded capacitor is used to design a reconfigurable first-order universal filter (CFUF). By simply swapping the digital control words (k1k2), the suggested circuit may implement all of the common filter responses, including high-pass, low-pass, and all-pass. An EX-CCCII serves as the active element in the filter setup, which is based on a novel topology, which provides several advantages, such as reduced complexity, low power consumption, and improved performance. The following advantages of the proposed circuit: high input impedance for voltage input signals, electronically controllable pole frequency that varies with bias current, and a single grounded capacitor that can be integrated into an IC. At a power supply level of ±0.5 V, the proposed circuit is modeled using specifications for 0.18-micrometer CMOS technology. PSPICE simulation tool is used to demonstrate the filter's performance. [ABSTRACT FROM AUTHOR]

This paper presents a new low-voltage low-power differential difference current conveyor transconductance amplifier (DDCCTA). The proposed DDCCTA utilizes a multiple-input gate-driven MOS transistor (MIGD-MOST) operating in the subthreshold region to achieve low supply voltage, minimum number of MOS differential pairs and minimum power consumption. To show the advantages of the proposed DDCCTA, it was used to realize a versatile analog filter. The filter uses three DDCCTAs, two grounded capacitors, and two grounded resistors to realize 65 transfer functions of low-pass, high-pass, band-pass, band-stop, and all-pass filters by appropriately selecting the input and output terminals without changing the filter topology. The filter also has the advantages of high-input impedance, which is ideal for voltage-mode circuits, independent control of the natural frequency and quality factor, and the ability to electronically tune the natural frequency. The proposed DDCCTA and versatile analog filter were designed and simulated using SPICE with TSMC $0.18~\mu $ m CMOS technology to verify the new circuits. The proposed filter uses ±0.5 V of supply voltage and $103~\mu $ W of power.

This work introduces and examines a new programmable electronic system, Board ADF339, designed for filtering analog measurement signals of low frequencies. The system operates in a mixed mode in collaboration with a digital controller implemented on the myRIO-1900 FPGA module. It enables the digital selection of the type and frequency settings of the UAF42 integrated circuit. In the technical implementation section, electronic filter and phase shifter circuit diagrams are presented, along with the digital counterpart of the analog filter. Tests of this system were conducted on signals generated using a function generator, which was followed by the filtration of signals occurring in real laboratory setups. A series of real responses from three different laboratory systems and a measurement system utilizing LabVIEW FPGA virtual instruments are demonstrated. After computing SNR indicators for noisy waveforms, the application scope and usability of the board are highlighted. [ABSTRACT FROM AUTHOR]

This paper presents a versatile first-order analog filter using differential difference transconductance amplifiers (DDTAs). The DDTA employs the bulk-driven (BD) multiple-input MOS transistors technique (MI-MOST) operating in the subthreshold region. This results in low-voltage and low-power operational capability. Therefore, the DDTA, designed using 130 nm CMOS technology from UMC in the Cadence environment, operates with 0.3 V and consumes 357.4 nW. Unlike previous works, the proposed versatile first-order analog filter provides first-order transfer functions of low-pass, high-pass, and all-pass filters within a single topology. The non-inverting, inverting, and voltage gain of the transfer functions are available for all filters. Furthermore, the proposed structure provides high-input and low-output impedance, which is required for voltage-mode circuits. The pole frequency and voltage gain of the filters can be electronically controlled. The total harmonic distortion of the low-pass filter was calculated as −39.97 dB with an applied sine wave input signal of 50 mVpp@ 50 Hz. The proposed filter has been used to realize a quadrature oscillator to confirm the advantages of the new structure. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-mode universal filter using a multiple-input multiple-output operational transconductance amplifier (MIMO-OTA). The multiple-input OTA is designed using the multiple-input MOS transistor technique (MI-MOST), resulting in a single differential pair and minimal power consumption. The MIMO-OTA is used to design a universal mixed-mode filter that provides input and output in voltage and current form. In a single topology, second order filters with low-pass (LP), high-pass (HP), band-pass (BP), band-stop (BS) and all-pass (AP) transfer functions can be obtained in voltage-mode (VM), current-mode (CM), transadmittance-mode (TAM) and transimpedance-mode (TIM). In addition, VM, CM, and TAM offer non-inverting and inverting transfer functions of LP, HP, BP, BS, and AP filters. The natural frequency and quality factor of all filter functions can be orthogonally controlled. Electronic tuning of the natural frequency is provided. The supply voltage is 0.5 V and the power consumption of the filter is 58 nW for 4 nA setting current. The filter was designed and simulated in the Cadence Virtuoso environment using TSMC $0.18~\mu \text{m}$ CMOS technology. The simulation results including Monte-Carlo analysis and process, voltage, and temperature corners are presented.

This paper presents a new application of the multiple-input operational transconductance amplifier (MI-OTA). The MI-OTA has been used to realize a first-order universal filter which shows that the first-order transfer functions such as low-pass, high-pass, and all-pass filters can be obtained easily from a single topology by applying the input signal to the appropriate terminals. Moreover, both non-inverting and inverting transfer functions of all filtering functions can be obtained. The pole frequency of all filters can also be controlled electronically. The first-order all-pass filters have been selected to realize high-quality band-pass filter. For low-voltage supply operation and extremely low power consumption, the proposed MI-OTA is realized by the multiple-input bulk-driven MOS transistor technique with transistors operating in subthreshold voltage region. The circuit has been simulated using the $0.18 \mu \text{m}$ TSMC CMOS technology with 0.5 V of supply voltage and it consumes 29.77 nW of power for 10 nA nominal setting current. The post-layout simulation results show that the applications of MI-OTA agree well with theory.

A simple yet effective approach to improve the linearity of the transconductor-capacitor ( $G_{m}-C$ ) filters is proposed without any area or power overhead. Following a generalized nodal analysis, the transconductors of classical filter topology are rewired such that their input differential voltage lies within the linear regime. The effectiveness of the proposed method is validated through the design and simulation of a fifth-order Butterworth low-pass filter (LPF) in a standard 65-nm CMOS process. The proposed filter implementation occupies 0.0164 mm2 (0.003 mm2/pole) die area and consumes 167- $\mu \text{W}$ for the cut-off frequency of 1-MHz. Operating at 1-V voltage supply, it shows an in-band total harmonic distortion (THD) of −49.14 dB for 200-mV peak-to-peak 1MHz differential voltage. An in-band 3rd-order intercept point (IIP3) of 9.36 dBm is also achieved with an in-band spurious-free-dynamic range (SFDR) greater than 53-dB, all of which reflect meaningful improvements relative to the classical architecture and despite the modest linearity performance of the internal $G_{m}$ stages.

In this paper, a CMOS wideband low-pass filter is proposed. In the wide band active filter design, the unit gain frequency (GBW) of OPAMP should be larger than GHz. The GBW of the proposed OPAMP is around 2.3 GHz. Additionally, the OPAMP with a complementary structure in signal and common mode feedback is proposed and has a wide operating voltage range at the input and output. The 1-dB gain compression point (P1dB) at the output is 4.9 dBm. A source follower is employed for driving 50 Ω output impedance without degrading the bandwidth and linearity of the filter. The power consumption is 27 mW from a 1-V supply voltage. The 3 dB bandwidth of the filter ranges from 330 MHz to 660 MHz with 3-bit cap tuning. This work is implemented in a 65-nm CMOS process, with a chip area of 0.18 mm2.

This paper presents new applications of low-voltage and low-power multiple-input multiple-output differential difference transconductance amplifier (DDTA). The multiple-input bulk-driven MOS transistor (MIBD MOST) technique provides multiple-input of the active device that simplifies the application’s topology and reduces its power consumption. The proposed DDTA has been used to realize multiple-input single-output shadow filter. Both voltage- and transimpedance-mode filtering functions can be obtained. The natural frequency and the quality factor of the shadow filter can be independently and electronically controlled using DDTA-based amplifiers. The proposed shadow filter has been modified to work as a shadow oscillator. The condition and frequency of oscillation can be controlled independently and electronically. The DDTA is capable to work with 0.5V supply voltage and consumes 218.2 nW. The applications have been designed and simulated in Cadence using $0.18\mu \text{m}$ TSMC CMOS technology.

This work explicitly states the design flows of the fractional-order analog filters used by researchers throughout the literature. Two main flows are studied: the FPAA implementation and the circuit realization. Partial-fraction expansion representation is used to prepare the approximated fractional-order response for implementation on FPAA. The generalization of the second-order active RC analog filters based on opamp from the integer-order domain to the fractional-order domain is presented. The generalization is studied from both mathematical and circuit realization points of view. It is found that the great benefit of the fractional-order domain is that it adds more degrees of freedom to the filter design process. Simulation and experimental results match the expected theoretical analysis.

In this paper, seven different MOSFET-C transimpedance filters with their corresponding transfer functions and basic filter specifications, are provided. Presented designs show second-order standard band-pass, low-pass, or high-pass characteristics. Moreover, some filters provide both low-pass and band-pass characteristics. Especially, having a tunability feature makes a design more useful and applicable for various communication and instrumentation systems. The selected filter topology was biased under various biasing conditions to tune central frequency by keeping bandwidth constant. To elaborate the design with different aspects, we checked its small-signal performance by introducing both changing temperature and implementation errors. The theoretical results are in detail verified by numerous simulations using Cadence IC6 Spectre analog design environment. In the design, transistors with 1.8 V supply voltage were used and modelled by the SilTerra Malaysia 180 nm CMOS process parameters. The implemented layout, including metal-insulator-metal on-chip capacitors, occupies an area of 175 μm × 75 μm, while the total power consumption of the filter is found to be only 128.86 μW. [ABSTRACT FROM AUTHOR]

This paper presents new voltage-mode shadow filters employing a low-power multiple-input differential difference transconductance amplifier (MI-DDTA). This device provides multiple-input voltage-mode arithmetic operation capability, electronic tuning ability, high-input and low-output impedances. Therefore, the proposed shadow filters offer circuit simplicity, minimum number of active and passive elements, electronic control of the natural frequency and the quality factor, and high-input and low-output impedances. The proposed MI-DDTA can work with supply voltage of ±0.5 V and consumes 9.94 μW of power. The MI-DDTA and shadow filters have been designed and simulated with the SPICE program using 0.18 μm CMOS process parameters to validate the functionality and workability of the new circuits. [ABSTRACT FROM AUTHOR]

The hysteresis nonlinearity and rate dependence of piezoelectric actuators seriously affect their positioning accuracy in precise positioning. Proper compensation needs to be given to improve the positioning accuracy of the actuator. In this paper, the static hysteresis characteristics are described by improving the BP neural network model based on the adaptive particle swarm optimization algorithm, and the PI model is used as the hysteresis factor by the extended space method to realize the multi-valued mapping of hysteresis nonlinearity. And input three types of voltage signals, compare and analyze the experimental data and model prediction output, and use the maximum relative error and root mean square error as the evaluation indicators to prove the accuracy of the built model. Based on the improved BP neural network model, a second-order low-pass analog filter is introduced to construct a rate-dependent hysteresis model. Comparing and analyzing the rate-dependent hysteresis model and the static hysteresis model, the experimental results show that when the signal frequency is 10 Hz, 40 Hz, and 100 Hz, the predicted output of the rate-dependent hysteresis model is compared with that of the static hysteresis model, and the root mean square error decreases by 46.3%. %, 59.6%, and 65.1%, the model can more accurately describe the hysteresis characteristics of piezoelectric actuators. Finally, a rate-dependent hysteresis inverse model is established, and the rate-dependent hysteresis inverse model is used as a feedforward combined with a single neuron network PID control to form a composite controller, and the experimental verification is carried out. The results show that the maximum error between the composite controller and the actual expectation is only 2.15%. Therefore, the established model can accurately express the rate-dependent hysteresis characteristics of piezoelectric actuators, and the use of a composite controller can effectively reduce the accuracy error caused by the hysteresis nonlinear characteristics of piezoelectric actuators. [ABSTRACT FROM AUTHOR]

In this work, a new versatile voltage- and transconductance-mode analog filter is proposed. The filter, without requiring resistors, employs three differential-difference transconductance amplifiers (DDTAs) and two grounded capacitors, which is suitable for integrated circuit implementation. Unlike previous works, the proposed filter topology provides: (1) high-input and low-output impedances for a voltage-mode (VM) analog filter, that is desirable in a cascade method of realizing higher order filters, and (2) high-input and high-output impedances for a transconductance-mode (TM) analog filter without any circuit modification. Moreover, a quadrature oscillator is obtained by simply adding a feedback connection. Both VM and TM filters provide five standard filtering responses such as low-pass, high-pass, band-pass, band-stop and all-pass responses into single topology. The natural frequency and the condition of oscillation can be electronically controlled. The circuit operates with 0.5 V supply voltage. It was designed and simulated in the Cadence program using 0.18 µm CMOS technology from TSMC. [ABSTRACT FROM AUTHOR]

In this paper, new Gm-C all-pass and amplitude-equalizer biquads are shown to be realized from a generalized Gm-C biquad filter structure by using Gm-simulated negative resistor in series with integrating capacitor in the lossless integrator. The non-ideality analysis of the all-pass/ amplitude-equalizer biquad using finite output conductance and parasitic output capacitance of Gm-cells is presented. The proposed Gm-C all-pass and amplitude-equalizer biquads are simulated for 0.18 μm CMOS technology with ± 0.9 V power supply in Cadence environment to validate the frequency response characteristics. For the Gm-C AP biquad filter designed for 1 MHz cut-off frequency and pole quality factor of 2, the power consumption is 82.37 µW, the input-referred noise is 137.6 μ V / H z and the dynamic range is 62.84 dB. The biquad has the figure of merit (FoM) of 0.2969 × 10−13 J. [ABSTRACT FROM AUTHOR]

Featured Application: Our research can be used as poultry breeding equipment or as an authenticated device for other breeding methods. It is of great significance for poultry breeding or weight tracking and monitoring of feeding behavior. The feeding behavior of poultry at a young age is very likely to determine the final growth of the chicken, and can also reflect the feeding status and the health status. It is also of great significance for breeding. This paper describes the development and testing of a real-time automated system and a single passage for monitoring the individual feed intake and body weight of poultry. This system integrates an automatic feeding mechanism, an RFID reading module, a weight scale, a feed scale, and a drop weighting scale. The system uses analog circuits and digital filtering to improve the weighing accuracy, and directly measures the amount of feed falling to the ground using a high-precision weighing scale. Through the sequential opening and closing of a sliding door, group-housed chickens are separated so that the young ones are fed individually. As a result of the experiment, we learned that a young chicken grows at a rate of about 8.88 g/day, and the food conversion rate (FCR) is about 4.4, which proves that this system matches the single passage and can accurately monitor the body weight change and feeding behavior of young chickens. [ABSTRACT FROM AUTHOR]

A new realisation of an electronically tunable first-order voltage-mode all-pass filter enjoying the feature of low voltage and low power is proposed in this paper. The proposed realisation of filter employs only one active element namely differential voltage extra-x current controlled conveyor and one grounded capacitor. The use of minimal number of components makes the proposed structure simple and attractive from chip fabrication point of view. The performance of proposed structure is also discussed by considering the effects of parasitic and non-idealities of the used active element. Additionally, higher order filter realisation is also included to enrich the presented work by exploring possible applicability aspects. The theoretical performance is validated at schematic level using 0.18 µm CMOS technology parameters with ±1 V supply voltages. Furthermore, Cadence Analog Design Environment (ADE) with gpdk 0.18 µm technology is used to design the layout of the proposed circuit. Pre-layout and post-layout simulation verification is provided to extend the real time validation of theoretical aspects. [ABSTRACT FROM AUTHOR]

In this study, MOS-Only transimpedance mode filters are proposed. The presented circuits use two capacitors and MOS transistors that operate in saturation mode. The circuits are additional examples contributing to the set of previously published circuit topologies. One of the circuits is chosen and its functionality is verified with simulations. An important aspect of the chosen design is the versatility of filter parameters. Changing the drain currents of MOSFETs makes it possible to adjust the center frequency after production. We performed simulations with the LTSPICE simulation program using 0.18 μm TSMC CMOS technology. Simulation results are found in close agreement with the theoretical results. [ABSTRACT FROM AUTHOR]

This work is a review article that sheds light on the active and passive sensitivities of the active RC filters based on opamp. This work provides a detailed analysis through different filters realization criteria and sensitivity summary tables and quantitative insight by discussing the most significant. However, some are almost forgotten, filters families in the literature over decades. A detailed mathematical analysis for the passive sensitivity to compare the filters' realizations is presented. The concept of dealing between filter design theory and filter design circuit realization is highlighted. Some filters families are chosen from the literature for the analysis. Some detailed specifications tables for each filter family are given. Monte Carlo simulation is carried out on some filters to compare their passive sensitivity. Furthermore, the effect of the active sensitivity of some filters is verified through simulation by adjusting the input common-mode voltage to lower the DC gain of the amplifier. The results of the simulation match with the theoretical analysis and the summary provided in the specifications tables. [ABSTRACT FROM AUTHOR]

An improved class AB version of the super source follower is used to implement a compact and power-efficient second order analog low-pass filter. The proposed circuit achieves a 41% power reduction as well as an improvement in linearity and pass band gain with respect to its class A counterpart. Measurement results of a test chip prototype fabricated in a 180 nm CMOS technology show a power consumption ranging from 50.3 $\mu \text{W}$ to 85.27 $\mu \text{W}$ for cutoff frequencies from 600 kHz to 890 kHz, with a supply voltage of ±0.75 V. A third order intermodulation distortion of −35.34 dB (for an input signal of 0.4 mVpp and 350 kHz) and a THD of −69.7 dB (for an input signal of 0.4 mVpp and 100 kHz) are measured, which results in an improvement with respect to the conventional class A version of 13.98 dB and 43.6 dB, respectively. The silicon area is 0.0592 mm2 (using external capacitors). [ABSTRACT FROM AUTHOR]

This paper presents a versatile first-order analog filter using differential difference transconductance amplifiers (DDTAs). The DDTA employs the bulk-driven (BD) multiple-input MOS transistors technique (MI-MOST) operating in the subthreshold region. This results in low-voltage and low-power operational capability. Therefore, the DDTA, designed using 130 nm CMOS technology from UMC in the Cadence environment, operates with 0.3 V and consumes 357.4 nW. Unlike previous works, the proposed versatile first-order analog filter provides first-order transfer functions of low-pass, high-pass, and all-pass filters within a single topology. The non-inverting, inverting, and voltage gain of the transfer functions are available for all filters. Furthermore, the proposed structure provides high-input and low-output impedance, which is required for voltage-mode circuits. The pole frequency and voltage gain of the filters can be electronically controlled. The total harmonic distortion of the low-pass filter was calculated as −39.97 dB with an applied sine wave input signal of 50 mVpp@ 50 Hz. The proposed filter has been used to realize a quadrature oscillator to confirm the advantages of the new structure.

Input test signal plays important role in testing of analog circuits. Single type of input stimulus cannot maximally reveal the state of the circuit. To combat this shortcoming, this work proposes to integrate information from the output responses corresponding to different input stimuli and to use the combined information to improve the accuracy of fault diagnosis in analog circuits. The circuit under test is excited with different input signals and wavelet features are extracted from the output responses of the circuit. Ultimate fault features have been defined by applying data fusion algorithm to the sets of wavelet features obtained from individual output. Data fusion has been performed in two steps, data whitening and Principal component analysis (PCA). Fused features are used to train SVM (Support Vector Machine) classifier for fault diagnosis. The proposed approach is validated with three types of filter circuits, i.e. Sallen-Key band pass filter, four OPAMP high pass filter and elliptic low pass filter. The average accuracy of the proposed fault classification method has been found greater than 99.8% for all the test circuits. The proposed technique offers improved classification accuracy, lower computational burden and lesser implementation complexity. • This work proposes to integrate information from the output responses corresponding to different input stimuli to improve the accuracy of fault diagnosis. • Wavelet energy vectors have been used as pre-processor. • Fault features have been constructed by applying multi-source data fusion algorithm. • Data fusion has been performed in two steps, data whitening and Principal component analysis (PCA). • The fused features are used to train SVM (Support Vector Machine) classifier for fault diagnosis. • The proposed technique offers improved classification accuracy, lower computational burden and lesser implementation complexity. [ABSTRACT FROM AUTHOR]

This brief presents the analysis, design, and measurements of a compact analog frontend for a catheter-integrated ultrasound imaging digitizer. This frontend requires several functions, including single-ended-to-differential conversion, AC coupling, amplification, anti-aliasing, and the capability to drive the subsequent ADC. To minimize chip area and to maximize power efficiency, a 2-stage frontend was designed, where the active stages are built using self-biased inverter-based amplifiers. The measured prototype in 40nm CMOS offers a gain of up to 15dB and a bandwidth up to 20MHz, while consuming up to $162\mu \text{W}$ from a 1.1V supply. The peak FoM of 158dB(J−1) and chip area of 0.0054mm2 are in line with state-of-the-art filters, while the proposed design includes the aforementioned extra functionalities as well. [ABSTRACT FROM AUTHOR]

In the present paper, a new analog filter is proposed to check with high accuracy the axle load and gross vehicle weight of commercial vehicles moving at normal speed without disruption of traffic flow and ensure their respect to the transport regulation. The proposed technique is based on the zero crossing detector, designed as the basis component of the new analog filter which significantly decreases the range of measured errors according to the international standard. The promising results prove the effectiveness and the reliability of the filter under study. The intended accuracy is achieved since the maximum weighting error is less than 1% for the vehicle axles whereas the gross vehicle weight is less than 0.3% for a speed range of 40-100 km/h.

Prototype filters have wide usage for the design of filters with required quality indexes (QI) of gain-frequency response (GFR). The designed filter is obtained from a prototype filter b means of frequency transformation, which preserves these QI. But most of employed frequency transformations result in variations of QI of phase-frequency response (PFR). In this paper we proposed to use prototype filters that are Pareto-optimal for QI of GFR and PFR. Transfer functions of these filters may be found by means of heuristic optimization algorithms. This method will be efficient if the frequency transformation preserves the optimality of filters. It was shown that frequency transformation has this feature if it preserves the result of QI comparison (more or less) for filters with equal orders. Compliance of this criterion was checked for bilinear transformation of analog low pass filters (LPF) into digital LPF and for Konstantinidis transformation of digital LPF into other digital LPF. The analysis showed that Pareto-optimality for QI of GFR and PFR is preserved if the delay-frequency characteristic of the filter has a minimum at zero frequency and has a maximum at the upper boundary of the pass band. These conditions are complied for LPF with sufficiently small unevenness of GFR in the pass band and sufficiently fast decline of GFR at higher frequencies. Examples confirming these conclusions are given.

As the evolution of traditional electroencephalogram (EEG) monitoring unit for epilepsy diagnosis, wearable ambulatory EEG (WAEEG) system transmits EEG data wirelessly, and can be made miniaturized, discrete and social acceptable. To prolong the battery lifetime, analog wavelet filter is used for epileptic event detection in WAEEG system to achieve on-line data reduction. For mapping continuous wavelet transform to analog filter implementation with low-power consumption and high approximation accuracy, this paper proposes a novel approximation method to construct the wavelet base in analog domain, in which the approximation process in frequency domain is considered as an optimization problem by building a mathematical model with only one term in the numerator. The hybrid genetic algorithm consisting of genetic algorithm and quasi-Newton method is employed to find the globally optimum solution, taking required stability into account. Experiment results show that the proposed method can give a stable analog wavelet base with simple structure and higher approximation accuracy compared with existing method, leading to a better spike detection accuracy. The fourth-order Marr wavelet filter is designed as an example using Gm-C filter structure based on LC ladder simulation, whose power consumption is only 33.4 pW at 2.1Hz. Simulation results show that the design method can be used to facilitate low power and small volume implementation of on-line epileptic event detector.

In this paper, a novel methodology is proposed to implement the Morlet wavelet transform in an analog circuit. Under the proposed scheme, the impulse response of the linear time-invariant system is used to approximate the Morlet wavelet function. The approximation accuracy is guaranteed by the constrained L2 -norm method, which reduces the approximation error by decreasing free parameters in searching routines. Due to the complex wavelet function, a common-pole strategy is presented for filter construction. With the common poles in real and imaginary parts, partial components can be shared during the analog implementation of the wavelet transform. With the reasonably good approximation for Morlet wavelet function, an analog continuous-time filter is designed based on the Gm-C integrator and orthonormal ladder topology. Application examples are introduced to illustrate the superior performance of the proposed filter. It is shown that the designed analog filter approximates the ideal Morlet wavelet function well in both time and frequency.

This paper presents new voltage-mode shadow filters employing a low-power multiple-input differential difference transconductance amplifier (MI-DDTA). This device provides multiple-input voltage-mode arithmetic operation capability, electronic tuning ability, high-input and low-output impedances. Therefore, the proposed shadow filters offer circuit simplicity, minimum number of active and passive elements, electronic control of the natural frequency and the quality factor, and high-input and low-output impedances. The proposed MI-DDTA can work with supply voltage of ±0.5 V and consumes 9.94 μW of power. The MI-DDTA and shadow filters have been designed and simulated with the SPICE program using 0.18 μm CMOS process parameters to validate the functionality and workability of the new circuits.

In this work, a new versatile voltage- and transconductance-mode analog filter is proposed. The filter, without requiring resistors, employs three differential-difference transconductance amplifiers (DDTAs) and two grounded capacitors, which is suitable for integrated circuit implementation. Unlike previous works, the proposed filter topology provides: (1) high-input and low-output impedances for a voltage-mode (VM) analog filter, that is desirable in a cascade method of realizing higher order filters, and (2) high-input and high-output impedances for a transconductance-mode (TM) analog filter without any circuit modification. Moreover, a quadrature oscillator is obtained by simply adding a feedback connection. Both VM and TM filters provide five standard filtering responses such as low-pass, high-pass, band-pass, band-stop and all-pass responses into single topology. The natural frequency and the condition of oscillation can be electronically controlled. The circuit operates with 0.5 V supply voltage. It was designed and simulated in the Cadence program using 0.18 µm CMOS technology from TSMC.

This paper introduces a simulated grounded inductor (SGI) circuit realization based on two terminal active devices, namely negative impedance converters. The proposed SGI contains a minimum number of passive components when compared to its two terminal active device-based realization counterparts in the literature. It includes a grounded capacitor that is an advantage in integrated circuit process. Nonetheless, a single resistive matching constraint is needed for its realization. SPICE simulations are performed with 0.13 µm CMOS IBM technology parameters with supply voltages of ± 0.75 V. Also, an experimental study is included to verify the theory. [ABSTRACT FROM AUTHOR]

The feeding behavior of poultry at a young age is very likely to determine the final growth of the chicken, and can also reflect the feeding status and the health status. It is also of great significance for breeding. This paper describes the development and testing of a real-time automated system and a single passage for monitoring the individual feed intake and body weight of poultry. This system integrates an automatic feeding mechanism, an RFID reading module, a weight scale, a feed scale, and a drop weighting scale. The system uses analog circuits and digital filtering to improve the weighing accuracy, and directly measures the amount of feed falling to the ground using a high-precision weighing scale. Through the sequential opening and closing of a sliding door, group-housed chickens are separated so that the young ones are fed individually. As a result of the experiment, we learned that a young chicken grows at a rate of about 8.88 g/day, and the food conversion rate (FCR) is about 4.4, which proves that this system matches the single passage and can accurately monitor the body weight change and feeding behavior of young chickens.

A new analog block, Differential Voltage Extra-X Current Controlled Conveyor (DV-EXCCCII) based current mode universal filter configuration is introduced in this paper. Only one current mode analog block DV-EXCCCII, three grounded components are used to design proposed filter configuration. This circuit provides high output impedance, which allows cascading feature to circuit without need of extra buffer circuit. This configuration realise all five (Low Pass, High Pass, All Pass, Band Pass and Band Reject) second-order filter functions with an appropriate selection of input. Bias current of DV-EXCCCII provides the electronic tuning characteristic to proposed circuit. Sensitivity due to passive components and non-idealities of the analog block is low and magnitude is below unity. The proposed filter circuit configuration is designed in CADENCE and simulated with SPECTRE using 180 nm UMC CMOS process technology. [ABSTRACT FROM AUTHOR]

To provide multiple options for specific application in biosignal processing, the programmable Gaussian‐derived Gm‐C wavelet filter has been proposed. To realize the programmable characteristic, the analog wavelet base with one numerator term is constructed by using hybrid artificial fish swarm algorithm. Also, the inverse follow‐the‐leader feedback Gm‐C filter structure with a switch array is employed. By programming switches only, Gaussian and Marr wavelet transforms can be realized flexibly with all component parameters unchanged. The seventh‐order programmable wavelet filter is designed as an example. Simulation results show that power consumption is only 141.68 pW at scale a = 0.1, with dynamic range of 42.6 dB and figure‐of‐merit of 2.05 × 10−13. Due to the programmability, the proposed design method can implement two wavelet filters with very low circuit complexity. [ABSTRACT FROM AUTHOR]

In addition to ever-present thermal noise, various communication and sensor systems can contain significant amounts of interference with outlier (e.g., impulsive) characteristics. Such outlier noise can be efficiently mitigated in real time using intermittently nonlinear filters. Depending on the noise nature and composition, improvements in the quality of the signal of interest will vary from “no harm” to substantial. In this paper, we explain in detail why the underlying outlier nature of interference often remains obscured, discussing the many challenges and misconceptions associated with state-of-the-art analog and/or digital nonlinear mitigation techniques, especially when addressing complex practical interference scenarios. We then focus on the methodology and tools for real-time outlier noise mitigation, demonstrating how the “excess band” observation of outlier noise enables its efficient in-band mitigation. We introduce the basic real-time nonlinear components that are used for outlier noise filtering and provide examples of their implementation. We further describe complementary nonlinear filtering arrangements for wideband and narrowband outlier noise reduction, providing several illustrations of their performance and the effect on channel capacity. Finally, we outline “effectively analog” digital implementations of these filtering structures, discuss their broader applications, and comment on the ongoing development of the platform for their demonstration and testing.

High-rise structures are characterized as wind-sensitive vertical structures, estimating the wind-induced vibration response is a key to the structural design procedure. This study presented universal wind load spectral models for high-rise structures, including tri-para and κ model for along-wind load characterized by power dissipating with frequency and analog filter model for cross-wind load dominant by power concentration induced by vortex excitation. The spectral models appear to provide good agreement with wind tunnel data of buildings with various configurations. With analog filter approach, the along-wind spectra can be approximated by a linear filter polynomial and the cross-wind spectra is expressed by a quadratic filter polynomial. Thus forming a simple differential equation for the along- and cross-wind excitation based on a pseudo idea white noise. The closed form solutions to the wind-induced responses are derived based on analog filter approach. The Lyapunov equations are also provided in the state-space for high-rise structures with and without extra damping devices. The presented closed form solutions can provide a powerful tool in codification and vibration control optimization.

This brief presents a highly linear and high-speed operational amplifier that consists of a double-recycling folded cascode input stage and an adaptive biasing with a flipped voltage follower to boost slew-rate and unity-gain frequency. In addition, frequency compensation is performed by an input cross-coupled phase-lead passive compensation scheme and hybrid Miller-cascode compensation. A 56 MHz −3 dB bandwidth fifth-order programmable gain continuous-time active low pass filter is fabricated in 180 nm CMOS to validate the proposed scheme. The filter achieves 30.5 dBm of third-order interception point at 38 MHz and occupies 0.215 mm2. The filter consumes 14.7 mW with 1.8 V supply and has 0.2 dB in-band ripple. [ABSTRACT FROM AUTHOR]

In this paper, an electronically tunable mixed-mode analog filter is proposed, which employs only a single active element, namely Extra X Current Controlled Conveyor (EX-CCCII), two capacitors and a single resistor. The proposed circuit uses minimum components, so it is easy to integrate on chip. The circuit provides all four mode operations, namely current mode, voltage mode, transadmittance mode (TAM) and transimpedance mode without changing the circuit configuration. The circuit can provide all the five filter functions: low pass, high pass, band pass, band reject, and all pass by selecting appropriate input signals except the TAM. The parameters of the proposed circuit, i.e. angular frequency (ωo) and the quality factor (Q) are independent, while ωo is electronically tunable. The frequency range is 2.29 MHz to 22.9 MHz with a bias current variation from 1 to 100 µA. The effects of non-idealities and parasitics of the active element on the circuit performances are discussed. The results are verified through PSPICE simulation using a 0.18 µm CMOS technology with the supply voltages of ± 0.5 V. The power consumption is 13.5 µW at 1 µA, and 1.35 mW at 100 µA. The experimental setup further validates the theory and simulation results. [ABSTRACT FROM AUTHOR]

In this paper, we present six area-efficient transimpedance type second-order analog filters. There are many applications where the available signal is current, however the necessary signal for further processing is voltage type. For such applications the presented circuits will be a useful solution. The technique employed is called MOS-only technique and to the best of our knowledge this is the first attempt to implement transimpedance type filters with MOS-only technique. Starting from the core circuit biasing is illustrated and the functionality is shown with LT SPICE simulations using TSMC 0.18u technology parameters. From six core circuits one circuit is selected and the design is completed for illustration purpose. [ABSTRACT FROM AUTHOR]

This article presents a fully differential (FD) low-voltage (LV) fourth-order Butterworth active-RC low-pass filter (LPF) with a maximum cutoff frequency $(f_{o})$ of 160 MHz, $f_{o}$ programmability, and adaptive power. The proposed filter targets communication systems requiring high and reconfigurable $f_{o}$ at supply voltages $(V_{\mathrm {DD}}s)$ of 0.6 V. The filter is implemented with an active-RC topology, a programmable $f_{o}$ between four steps, 20/40/80/160 MHz, and a $f_{o}$ fine-tuning option after fabrication via capacitor banks. A compact LV FD amplifier with feedforward gain-boosting implementation is used to meet the stringent filter’s performance. The novel amplifier achieves an open loop gain of 66 dB and a maximum unity-gain frequency (UGF) of 759 MHz with $V_{\mathrm {DD}} = 0.6$ V and 5.27 mW of power dissipation. Using the proposed amplifier, the filter achieves the highest $f_{o}$ reported in the literature for LV active-RC implementations and 40% power reduction over similar high- $f_{o}$ LV filters. The filter was fabricated in a CMOS 130-nm technology; it has a THD = 50.7 dB, signal-to-noise and distortion (SNDR) = 45.37 dB, $P_{\mathrm {1dB}} = 4.26$ dBm and 520- $\mu \text{V}$ RMS integrated noise over the filter’s bandwidth (BW), while consuming 23.8 mA from a 0.6-V supply for $f_{o} = 160$ MHz. [ABSTRACT FROM AUTHOR]

In this paper, plus-type differential voltage current conveyor based two voltage-mode (VM) analog filters with high input impedance properties yielding easy cascadability with other VM circuits are proposed. The first proposed filter can simultaneously provide all the second-order universal filter responses except all-pass one, and employs only grounded passive elements that are canonical in number. The second one can simultaneously realize all the second-order universal filter responses, and includes one floating resistor, one grounded resistor and two grounded capacitors. No passive element matching condition is required for both of the proposed analog filters. However, both of the proposed filters do not have the feature of orthogonal control of angular resonance frequency and quality factor. Many simulations such as AC, transient, Monte Carlo, etc. are performed to denote the performances of both of the proposed analog filters. [ABSTRACT FROM AUTHOR]

Time-domain operational amplifier (op-amp) is developed with only time-domain circuits such as voltage-controlled oscillator (VCO) and voltage-controlled delay line (VCDL). The infinite dc-gain of the voltage-to-phase transfer characteristic of VCO allows the time-domain op-amp to have large dc-gain. The frequency compensation is performed by the left-half plane (LHP) zero created by VCDL whose output phase is proportional to its control input voltage. With the proposed time-domain op-amp, a fourth-order continuous-time (CT) analog filter with 25 MHz cut-off frequency has been implemented in a 65 nm CMOS technology. The filter occupies 0.107 mm2and operates with 0.9 V supply consuming 8.2 mW. The measured in-band input third-order intercept point (IIP3) is 22.6 dBm and the peak signal-to-noise+distortion ratio (SNDR) is 60.9 dB. [ABSTRACT FROM AUTHOR]