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Based on the operating principle and cushioning characteristic of a shift clutch,the mechanical model of the shift clutch and the hydraulic model of the buffer circuit are respectively established in Recur Dyn and AMESim,then the mechanical-hydraulic co-simulation is realized through the software interface. The operating characteristics of the shift clutch with buffer circuit are analyzed,then the reliability is tested and the typical factors that affected the performance are explored. The basis for the failure mechanism and maintenance of the shift clutch is provided.

Existing mechanical HVDC circuit breakers (CB) are capable of interrupting HVDC currents within several tens of milliseconds, but this is too slow to satisfy the requirements of a reliable HVDC grid. HVDC CB based on semiconductors can easily overcome the limitations of operating speed, but need large number of the series (parallel) connection of electronic switching devices. To overcome these shortcomings, this paper introduces a topology of hybrid CB; this paper first describes the principle of hybrid CB; then a control strategy of fault pre-treatment is also proposed, that is, the ‘pre-action and action (or recovery)’ of the switches, in order to improve the breaking speed of the hybrid CB and the equalising circuit of its solid-state switch has been designed. The proposed topology and control strategy do not produce loss in the normal operation of CB, and instantaneous trigger solid-state switch with quickly cutting short-circuit current during short-circuit faults; at last the simulation and experiment of the hybrid HVDC CB have also been done. The results turn out when a short circuit occurs, the hybrid HVDC CB can quickly break the short-circuit current; the buffer circuit can be provided for the release of the stored energy circuit.

Existing mechanical HVDC circuit breakers (CB) are capable of interrupting HVDC currents within several tens of milliseconds, but this is too slow to satisfy the requirements of a reliable HVDC grid. HVDC CB based on semiconductors can easily overcome the limitations of operating speed, but need large number of the series (parallel) connection of electronic switching devices. To overcome these shortcomings, this paper introduces a topology of hybrid CB; this paper first describes the principle of hybrid CB; then a control strategy of fault pre-treatment is also proposed, that is, the 'pre-action and action (or recovery)' of the switches, in order to improve the breaking speed of the hybrid CB and the equalising circuit of its solid-state switch has been designed. The proposed topology and control strategy do not produce loss in the normal operation of CB, and instantaneous trigger solid-state switch with quickly cutting short-circuit current during short-circuit faults; at last the simulation and experiment of the hybrid HVDC CB have also been done. The results turn out when a short circuit occurs, the hybrid HVDC CB can quickly break the short-circuit current; the buffer circuit can be provided for the release of the stored energy circuit. [ABSTRACT FROM AUTHOR]

A new design method has been conceived for a buffer circuit using TIS. In the buffer circuit of a taper type with a fan-out of 3 intended for driving a large load capacitance, a new design procedure is conceived that minimizes the pattern area without sacrificing characteristics such as power consumption. In the new design method, the “planar+TIS” method is employed, in which planar-type transistors are used in the front stage of the buffer circuit while TIS-type transistors are used in the latter stage. This design method is applied to a large-capacity DRAM. Relative to the case in which conventional planar transistors are used, the chip area can be reduced by about 8% without sacrificing characteristics such as power consumption. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(4): 9–15, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10152 [ABSTRACT FROM AUTHOR]

Internal speedup architecture is a very useful approach to increase system performance. A single flux quantum circuit, which can operate at a speed 10 times higher than that of the fastest CMOS circuits, is suitable for use with this architecture. To realize this architecture in a system, a speed conversion interface is required. We proposed a new speed conversion method and designed a speed conversion circuit that converts serial bit streams from 10 to 40 Gbps. This circuit consists of stream demultiplexers, stream multiplexers and shift registers. We designed a physical layout of the stream demultiplexer and confirmed correct 10 GHz operations by simulations. As a demonstration, we fabricated a critical part of the stream demultiplexer and confirmed that it operated correctly. [Copyright &y& Elsevier]