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This paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2. [ABSTRACT FROM AUTHOR]

An audio power amplifier is an electronic device used to amplify a small signal source power at the input into a large signal power at the output that is speaker. In general, audio power amplifiers use class-AB amplifiers. In the process of amplifying the signal power, there will be power losses in the amplifiers which results in relatively lower amplifier power efficiency because there is a difference between the supply and output voltage levels. In this paper a class-G series audio power amplifier for subwoofers is designed to minimize these power losses and increase the power efficiency of the amplifier. The designed amplifier voltage supply is 40 V with a maximum output power of 80 W at an 8 Ω load. The amplifier has frequency response from 20–200 Hz and gain twice. Realization of the power amplifier and measurements were carried out using the circuit maker simulator, and the measurement results of the class-G power amplifier were compared with the class-AB power amplifier. The measurement results show that both power amplifiers meet the design specifications. The proposed class-G amplifier has 0.14% larger total harmonic distortion (THD) but has 10.4% greater power efficiency advantages over the class-AB amplifier. [ABSTRACT FROM AUTHOR]

This paper presents a low-power class-AB second-generation voltage conveyor (VCII) based on a new high-drive flipped voltage follower (FVF) circuit. The proposed FVF cell establishes an additional negative feedback loop to enhance the driving capability of the VCII. This improvement ensures a very low output impedance and guarantees the accuracy of the circuit. Since the VCII is configured using two of the proposed FVF cells, it benefits from a simple structure, very low impedance at Y and Z terminals, high impedance at X terminal, and high accuracy in current and voltage conveying. In addition, the driving capability of the VCII is several tens of times larger than its biasing current. The circuit was fabricated using TSMC $0.18~\mu $ m CMOS technology occupying a silicon area of $121.5~\mu $ m $\times 123.3~\mu $ m. Experimental results at a supply voltage of ±0.9 V show bandwidths of 155 MHz and 55.3 MHz for voltage and current transfer functions, respectively, while a static power of $342~\mu $ W is consumed. The impedances at Y, Z and X terminals were measured by $0.2\Omega $ , $0.3\Omega $ , and 146 k $\Omega $ , respectively.

In this study, the proposed bulk-driven amplifier utilizes the bulk-driven flipped voltage follower together with the auxiliary amplifier to form the adaptive biasing input stage. The quasi-floating gate technique to build the class-AB output stage can enhance the gain-bandwidth, DC gain and slew rate of the conventional bulk-driven counterpart. Therefore, the current efficiency is improved. Simulation verification using a 0.18 μ m CMOS technology, with a supply voltage of 0.8V, showed a DC gain of 76.6 dB, a CMRR of 106.6 dB, a gain-bandwidth product of 6.78 MHz and an average slew rate of 3.48 V / μ s. [ABSTRACT FROM AUTHOR]

This brief presents a high current-efficiency rail-to-rail class-AB op-amp with dual-loop control. Based on the conventional folded cascode op-amp with gain-boost, a dual-loop control strategy consisting of a gain-boost loop and an adaptive output stage current control loop is proposed to achieve bidirectional large load driving capability and high DC gain. Furthermore, the adaptive output stage current control loop achieves class-AB operation with symmetric separate signal paths to the output transistors and high reconfigurability. In addition, the implementation of the constant transconductance ($\text{g}_{\mathrm{ m}}$) rail-to-rail input and slew rate (SR) enhancement circuit is adopted to widen the input voltage range and improve the large-signal transient response. The proposed op-amp is fabricated in a 0.18- $\mu \text{m}$ 5 V CMOS process with an active area of about 0.25*0.27 mm2. Measured results show the proposed op-amp achieves over 122 dB DC gain, 1 MHz gain-bandwidth, and 2.1 V/ $\mu \text{s}$ SR under bidirectional load conditions (100pF and 10k $\boldsymbol{\Omega }$). At 1.5 V and 5.5 V supplies, positive current-efficiency (CE+) are 15 and 1780, negative current-efficiency (CE−) are 37 and 1658, power consumptions are 59.2 $\mu \text{W}$ and 225.5 $\mu \text{W}$ , respectively. [ABSTRACT FROM AUTHOR]

High‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA) and power combiner for millimeter‐wave applications using 130 nm CMOS technology are presented in the paper. The suggested PA uses transformer coupled for input, inter‐stage, and output matching networks where the inter‐stage matching inductors are utilized to enhance the RF performance. The proposed power amplifier is composed of three stages: first, driver, and power stages. The first stage operates in a class‐C to improve the efficiency and decrease power dissipated while a class‐AB is used in the driver and power stages to maximize the output power. The proposed PA and power combiner designs are suitable for mm‐wave 5G applications. The coupling transformers, inter‐stage matching inductors, and output combiner are analyzed and designed using Ansoft high‐frequency structure simulator (HFSS) and achieve high‐quality factor and high‐coupling coefficient over the frequency range from 26 to 33 GHz. The proposed three‐stage transformer‐coupled power amplifier covers a frequency band from 26 GHz to 33 GHz with a saturated output power of 13.1 dBm, a peak power added efficiency (PAE) equals 19.1%, and a maximum power gain of 13.25 dB. Whereas the proposed power combiner has a saturated output power of 16.3 dBm, a maximum PAE equals 20.5% and a peak gain of 16.5 dB. The proposed three‐stage transformer‐coupled PA and power combiner consume low power of 65 mW and 128 mW, respectively. Moreover, the adjacent channel power ratios (ACPR) of the proposed PA and power combiner equal −30 dBc and −36 dBc, respectively, for 20 MHz channel bandwidth. Finally, the active areas of the proposed power amplifier and power combiner equal 0.25 mm2 and 0.69 mm2, respectively, while the chip areas are 0.55 mm2 and 1 mm2, respectively. [ABSTRACT FROM AUTHOR]

A high-performance class-AB flipped voltage follower (FVF) cell consisting of a level shifter, a bulk-driven transistor, and a folding transistor is presented in this paper. The level shifter improves the voltage swing while the bulk-driven transistor enhances the current driving capability. Further, a folding transistor allows the flow of sourcing current by providing an alternate path, which leads to required low output resistance. The other electrical features of the proposed circuit are high gain and wide bandwidth. The proposed circuit has been designed and simulated using Cadence tool in 0.18 µm CMOS technology. Using Layout XL editor, the physical layout of the proposed circuit has been designed. The post-layout simulation results of the proposed circuit have been given to demonstrate its performance. To show the robustness under extreme conditions, the analysis of the proposed circuit at various corners has also been presented. [ABSTRACT FROM AUTHOR]

The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. In this paper, a novel architecture of CCII for differential capacitive sensor interfaces is presented. The proposed topology shows a closed-loop configuration for both the voltage and the current buffer, thus leading to better interface impedances at terminals X and Z. Moreover, a low power consumption of 600 µW was obtained due to class-AB biasing of both buffers, and the inherent drawbacks in terms of linearity under the mismatch of class-AB buffering are overcome by its closed-loop configuration. The advantages of the novel architecture are demonstrated by circuit analysis and simulations; in particular, very good robustness under process, supply voltage and temperature variations and mismatches were obtained due to the closed-loop approach. The CCII was also used to design a capacitive sensor interface in integrated CMOS technology, where it was possible to achieve a sensitivity of 2.34 nA/fF, with a full-scale sensor variation of 8 pF and a minimum detectable capacitance difference of 40 fF. [ABSTRACT FROM AUTHOR]

A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω. [ABSTRACT FROM AUTHOR]

This article presents a class-AB operational transconductance amplifier (OTA) with a high slew rate. The proposed class-AB OTA is applied with a slew-rate enhancement technique using an extremely low quiescent current. The additional current-reference common-mode feedback loop resolves the susceptibility to process, voltage, and temperature fluctuations resulting from slew-rate enhancement transistors. The proposed class-AB OTA is most widely used in block design, including, a switched-capacitor circuit, analog-to-digital converter, digital-to-analog converter, low-dropout regulator, and switched-capacitor DC-DC converters. In this study, performance was validated by applying the proposed class-AB OTA to a switched-capacitor delta-sigma modulator which requires high performance and high precision. The circuit was designed and simulated using a 0.18-μm complementary metal-oxide semiconductor process.

This article presents a wideband ultralinear fully integrated power amplifier (PA) in 22-nm fully-depleted silicon-on-insulator (FD-SOI) technology for phased array-based $E$ -band backhaul networks. A novel amplitude to phase modulation (AMPM) compensation technique called NP (N-type P-type) matrix is presented. The performance of the proposed amplifier compared to a traditional N-type common-source (CS) PA is demonstrated in simulation across the corners and wide frequency range. The proposed PA occupies 0.084 mm2 core area and achieves peak 13.1-/13.7-dB gain, 61.8–83.7 GHz (21.9 GHz) 3-dB small signal bandwidth with 0.8 V/1 V supply. At 78 GHz, 13.8-/15.4-dBm peak saturated output power ($P_{\text {SAT}}$) with 13.1%/17% PAE from 0.8 V/1 V supply is measured, respectively. AMPM distortion at the output referred 1-dB compression point ($\text{OP}_{\text {1dB}}$) is less than 3.6° from 65 to 90 GHz. It achieves 18-/24-Gbit/s data rate with 10.7-/8.5-dBm average output power and 8%/4.9% average PAE at 73 GHz with 64/256 QAM modulation and a 0.8-V supply. [ABSTRACT FROM AUTHOR]

The paper proposes a current mirror designed using the current sensor structure of class‐AB flipped voltage follower cell at the input stage and super cascode structure at the output stage. The proposed current mirror offers low input resistance due to the current sensor at the input stage and high output resistance due to super cascode configuration at the output stage. The proposed current mirror offers a good dynamic range of 0 to 300 μA with less copying error of 0.54%, wide bandwidth of 319.8 MHz, high output resistance of 19.8 GΩ, and low input resistance of 161.34 Ω. The proposed current mirror is designed using BSIM3V3 180‐nm CMOS technology and simulated using spectre in the Cadence Virtuoso analog design environment at room temperature. The Cadence Virtuoso layout XL editor has been used to design the physical layout of the proposed current mirror. The pre‐layout and post‐layout simulation results of the proposed current mirror have been shown to validate its performance. The Monte Carlo analysis has also been performed to analyze the effects of process variations and mismatches on the performance of the proposed current mirror. [ABSTRACT FROM AUTHOR]

A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely | V GS | + 2 | V dsat |. Fabricated on a 0.18 μ m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves − 7 2 dB total harmonic distortion (THD) + noise (N) with a loudspeaker load of 100 ohm while operating from a 1.2 V supply and being subject to a 1 kHz sinusoidal input. [ABSTRACT FROM AUTHOR]

A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω.

A broadband and compact harmonic-tuned power amplifier (PA) is presented for 5G and mobile satellite communication (SATCOM). A noninverting 1:1 transformer is the core of the output matching and provides an embedded second harmonic trap in a compact layout. The proposed PA is fabricated by the BiCMOS SiGe-8XP technology. At $P_{1\,\text {dB}}$ , an output power of 11 dBm and a collector efficiency of more than 30% from 30 to 39 GHz are achieved. The PA has a single-ended topology with electrostatic discharge (ESD) protection, which is well suited for deployment in the output stage of the multichannel beamformer transmitter (TX) monolithic microwave integrated circuit (MMICs). Detailed analysis, design methodology, and experimental results are presented. [ABSTRACT FROM AUTHOR]

Summary: A 4th‐order Butterworth class‐AB current‐mode low‐pass filter is proposed, based on second‐generation Current Conveyors (CCII). Class‐AB operation allows high‐power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class‐AB output buffer with error amplifiers: this topology is known to be sensitive to mismatch errors, which cause offsets in the error amplifiers, affecting the biasing current of the stage. This problem is solved via a control loop, which compensates the effect of mismatches. The technique is shown to be effective in Monte Carlo simulations with process variations and mismatches. Simulations have been carried out in 40 nm CMOS technology. The proposed filter achieves good power efficiency, thanks to the class‐AB architecture, and good dynamic range, thanks to the closed‐loop output buffer. A cut‐off frequency of 6 MHz, with 184 μW of total quiescent power consumption, is achieved, with a THD of ‐55 dB and a SNR of 49 dB. [ABSTRACT FROM AUTHOR]

Transmit mixers frequently use Gilbert cells driven by common-source baseband amplifiers. Class-AB biasing is used in the latter for high efficiency, but this causes poor linearity. In this article, linearity is enhanced by using negative feedback to directly sense and linearize the baseband current flowing into the switching pair of the mixer. By suppressing both gate- and drain-induced nonlinearities, it achieves higher linearity and permits a higher power output compared to using replica devices of the common-source amplifiers in negative feedback. The technique is demonstrated using two prototypes: a 130 nm prototype designed for 1.9 GHz long term evolution (LTE) signals and a 65 nm LP prototype designed for Bluetooth basic data rate (BDR) and enhanced data rate (EDR) modes. The 130 nm prototype has an adjacent channel leakage ratio (ACLR) of −41.3/−40.4/−37.6 dBc for LTE5/10/20 at 11.7 dBm output, −148.6 dBc/Hz noise at 80 MHz offset for 10 dBm output, and −53.8 dBc CIM3 for 9 dBm output power. It consumes 335 mW from 3 V and 1.3 V supplies, including 79 mW in the LO buffers. The 4.4% efficiency represents 70% improvement over the state-of-the-art. The 65 nm prototype provides 4 dBm output power (EDR) while consuming 50.5 mW from 1.8 V. [ABSTRACT FROM AUTHOR]

A single-stage multipath class-AB bulk-driven operational transconductance amplifier working in weak inversion region with enhanced power efficiency is presented in this paper. The proposed bulk-driven amplifier makes use of four signal path to conduct small signal current, which leads to significant enhancement of transconductance when compared to conventional recycling structure. In addition, two of the signal paths build output stage operating at class-AB, resulting in a boost of slew rate. Most of all, the power efficiency of the proposed amplifier is improved over that of traditional recycling counterpart, enabling it more suitable for low-power applications. Simulated on SMIC 180 nm process, results demonstrate that the proposed bulk-driven amplifier achieves a 256% slew rate improvement and 100% unity-gain bandwidth enhancement when compared to the conventional recycling structure. [ABSTRACT FROM AUTHOR]

This paper presents a new predistortion linearization technique for high linearity and high modulation efficiency in millimeter-wave (mm-wave) CMOS power amplifiers (PA) for fifth-generation (5G) mobile communications. Our proposed linearizer adopts a transformer-based (i.e., inductive) self-compensated predistortion network at the input of the PA whose amplitude-modulation to phase-modulation (AM–PM) response is opposite compared with the AM–PM response of a CMOS PA, resulting in an AM–PM cancellation effect. This proposed inductive linearization method mitigates the large gain reduction problem in traditional capacitor-based linearization approaches while consuming no extra dc power or without introducing additional control circuitry. As a result, a significant improvement in power-efficiency and linearity is achieved with high-order complex modulation signals. To validate the proposed linearization method, a PA prototype in 65-nm CMOS technology was fabricated and tested, and it exhibited <1° of $\vert $ AM–PM $\vert $ distortion at $P_{\mathrm {o,1\, dB}}$ over 4 GHz of bandwidth (27–31 GHz). At 28 GHz, the measured saturated $P_{\mathrm {o}}$ and peak power-added-efficiency (PAE) was 15.6 dBm and 41%, respectively, while achieving a 6-dB $P_{\mathrm {o}}$ back-off PAE of 25%. To assess PA’s large-signal performance for 5G communications, the prototype was measured with the 64-quadratic-amplitude modulation (QAM) signal at 2-Gb/s data rates at 28 and 30 GHz, and the PA achieves modulated-PAE of 18.2%/17.6% and average- $P_{\mathrm {o}}$ of 9.8 dBm/10 dBm, respectively, while maintaining <−30 dBc of adjacent-channel-power-ratio and <−25.5 dB of error-vector-magnitude. The achieved modulated-PAE at 28 and 30 GHz shows more than $2\times $ improvement in comparison with the recently reported 28-GHz linear CMOS PAs. Also, the PA occupies a compact active-area of 0.24 mm2. [ABSTRACT FROM AUTHOR]

A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves −101.4-dB total harmonic distortion plus noise (THD+N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a $16\Omega \|0.33$ -nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 $\times $ improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power $\times $ THD+N[%])). It occupies 0.16 mm 2 in a standard 65-nm CMOS. [ABSTRACT FROM AUTHOR]

An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input common-mode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common-mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented. [ABSTRACT FROM AUTHOR]

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-m CMOS technology at 0.5V supply with 35nW power budget. The results show a 57.9dB DC gain, 8.8kHz gain bandwidth and 38.2V/ms slew rate for the proposed amplifier. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and low-noise capacitive-feedback amplifier with a current-reused OTA for ECG recordings. To improve the noise-power efficiency, the proposed OTA employs a current-reused architecture, which adopts an inverter-based differential input stage for low noise, and a class-AB output stage for large output range and high gm/I efficiency. The driving branch of the class-AB output stage is merged into the input stage to realize current reuse and reduce power consumption further. Fabricated in a 0.35-μm CMOS process, the amplifier consumes 160 nA from a 2-V supply, while achieving an input-referred noise of 2.05 μVrms, corresponding to a noise efficiency factor (NEF) of 2.26. The measured common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) exceed 65 dB and 70 dB, respectively. The total harmonic distortion (THD) is less than 1% with a 15-mVpp input at 20 Hz and the active area is 0.3 mm × 0.6 mm. [ABSTRACT FROM AUTHOR]

In this paper, a high-efficiency frequency-reconfigurable CMOS power amplifier (PA) design technique is presented at 24 and 28 GHz using integrated tunable neutralization and matching networks. To cope with the adverse effects of gate–drain capacitance ( C\mathrm {gd} ) in millimeter-wave (mm-wave) CMOS PAs in deep-submicrometer technologies, we propose a reconfigurable coupling-coefficient-based transformer. This technique provides optimum neutralization of C\mathrm {gd} in a common-source configuration, while enabling tunable neutralization in a frequency reconfigurable PA. Furthermore, to reconfigure the PA’s input and output matching networks, a low-loss frequency-reconfigurable matching topology using a switched substrate-shield inductor is proposed. The adopted matching network addresses the high loss in a conventional frequency reconfigurable matching approach, while facilitating high efficiency in the proposed PA design. Using the proposed techniques, a class-AB PA is fabricated in a 65-nm CMOS technology. This prototype achieves measured saturated power-added efficiency (PAEsat) of 42.6%, saturated output power ( Po,\mathrm {sat} ) of 14.7 dBm at 24 GHz, and 40.1% PAEsat, and 14.4 dBm Po,\mathrm {sat} at 28 GHz while occupying an active area of only 0.11 mm2. At 24 and 28 GHz, the PA is tested under 16 and 64-quadrature amplitude modulation (QAM) signals with 250 MHz of channel BW. The PA achieves modulated PAE of 15.2%/14.1%, error vector magnitude of −26.4/−26.6 dB, and adjacent channel leakage ratio of −30/−32 dBc at an average output power of 7.1/7 dBm for a 64-QAM signal with 250-MHz BW at 24 and 28 GHz, respectively. To the best of the author’s knowledge, the design presents one of the highest PAEs among mm-wave CMOS PAs reported to date, while it also supports multiband operation. [ABSTRACT FROM PUBLISHER]

A wideband amplitude to phase (AM–PM) compensated class-AB power amplifier (PA) suitable for highly integrated fifth-generation phased arrays is designed in 0.9-V 28-nm CMOS without RF ultra-thick top metal. Design techniques to realize broadband impedance transformation, power division/combining, and phase distortion linearization are discussed. Further, second-order effects due to practical layout constrains imposed by deep-scaled technologies are addressed and simple design solutions are proposed. The designed PA shows a measured $S_{21} -3$ dB bandwidth (BW) from 29 to 57 GHz (65%) with $|\text {AM}-\text {PM}|<1 {^{\circ }}$ up to $P_{1~\text {dB}}$. The measured $P_{\mathrm{ sat}}$ is 15.1 dBm over >56% $\text {BW}_{-1~\text {dB}}$ , with a peak power added efficiency of 24.2%. When a signal with wide modulation BW is applied, the realized PA enables up to 10.1-, 8.9-, and 5.9-dBm average $P_{\mathrm{ OUT}}$ while amplifying a 1.5-, 3-, and 6-Gb/s 64-quadratic-amplitude modulation, respectively, at 34 GHz. The in-band and out-of-band linearity measured in error vector magnitude and adjacent channel power ratio are always better than −25 dB and −30 dBc, respectively, without any digital pre-distortion. [ABSTRACT FROM AUTHOR]

An ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate is presented. Based on adaptive biasing and nonlinear current mirror techniques employed in a proposed symmetric current recycling structure, the proposed OTA not only achieves the maximum output current proportional to Vin 8 , but also has the symmetric positive and negative slew rates. Also, the proposed self-biasing output stage makes the slew rate unconstrained. Simulation results demonstrate that the slew rate of the proposed OTA is enhanced by 1500% over that of the conventional folded cascode counterpart with a little increased power, which is suitable for large capacitive load applications. [ABSTRACT FROM AUTHOR]

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated. [ABSTRACT FROM AUTHOR]

This article presents the design, simulation, implementation, and experimental results of a highly efficient, concurrent dual-band, gallium nitride (GaN), class-AB power amplifier (PA) at two frequencies: 1.84 and 3.5 GHz. It proposes a novel dual-band bandpass filter (DBBPF) with quad-section stepped-impedance resonators (SIRs) capable of rejecting the annoying frequencies of the second and third harmonics in the dual-band. The proposed DBBPF was applied in the design of a dual-band PA using a packaged 10 W GaN transistor. The PA prototype maintained a peak power-added efficiency (PAE) of 75.3% at the 1.84 GHz frequency and 64.5% at the 3.5 GHz frequency. For a continuous wave output power of 40.9 dBm, the measured gain was 13 dB in the two frequency bands. Linearized modulated measurements, concurrently using 10 MHz quadrature amplitude modulation (16 QAM) signals and worldwide interoperability for microwave access (WiMAX) signals, showed an average PAE of 48.5% and 39.8% and an adjacent channel leakage ratio of −46 and −45 dBc with an average output power of 37.8 and 36.8 dBm at the two frequency bands, respectively. This PA is used for wireless systems. It is especially useful in standard simultaneous global system for mobile (GSM) and WiMAX wireless systems. [ABSTRACT FROM AUTHOR]

A wideband low-noise transconductance amplifier (LNTA) with high linearity is proposed. The differential LNTA adopts complementary common-gate (CG), current mirror (CM) and common-source (CS) schemes to obtain noise and distortion cancellation, and $$g_{m}$$ -enhancement. A high third-order input intercept point (IIP3) is obtained due to the distortion cancellation and the complementary characteristics of NMOS and PMOS transistors. The gain expansion of the class-AB CS stage compensates the gain compression of the CG-CM stage, which leads to a high large-signal linearity. A wide input matching bandwidth is achieved by utilizing a $$\uppi $$ -type input matching network without the use of on-chip bulky inductors, and the passive voltage gain of the $$\uppi $$ -network further enhances the effective transconductance. Designed in a 0.18- $$\upmu \hbox {m}$$ CMOS process, the simulation results show that it provides a minimum noise figure (NF) of 2.95 dB and a maximum transconductance of 79 mS from 0.1 to 3.6 GHz. An input 1-dB compression/desensitization point and an IIP3 of 8.1/5.59 and 18.14 dBm are obtained, respectively. The NF is degraded by 0.3 dB with a 0-dBm blocker. The circuit draws 10.7 mA from a 2.5-V supply, and the core area is only $$0.5 \times 0.12\,\hbox {mm}^{2}$$ . [ABSTRACT FROM AUTHOR]

This paper demonstrates a systematic approach for the design of broadband, high efficiency, high power, Class-AB RF amplifiers with high gain flatness. It is usually difficult to simultaneously achieve a high gain flatness and high efficiency in a broadband RF power amplifier, especially in a high power design. As a result, the use of a computer-aided simulation is most often the best way to achieve these goals; however, an appropriate initial value and a systematic approach are necessary for the simulation results to rapidly converge. These objectives can be accomplished with a minimum of trial and error through the following techniques. First, signal gain variations are reduced over a wide bandwidth using a proper pre-matching network. Then, the source and load impedances are satisfactorily obtained from small-signal and load-pull simulations, respectively. Finally, two highorder Chebyshev low-pass filters are employed to provide optimum input and output impedance matching networks over a bandwidth of 100 MHz-500 MHz. By using an EM simulation for the substrate, the simulation results were observed to be in close agreement with the measured results. [ABSTRACT FROM AUTHOR]

A low-power FM demodulator operating across a 2–10-GHz IF bandwidth for its application in wideband heterodyne receivers is presented. A four-stage ring oscillator locks to one-fourth of the input FM, thereby reducing the energy required for wideband demodulation. The measurements show that the oscillator is capable of locking to at least a modulating frequency of 400 MHz, and further testing is limited by the FM source. Linear demodulation of the quadrature-phased outputs is realized using a low-power folded CMOS mixer, even as the fractional bandwidth of the input FM approaches unity. The inductorless 65-nm CMOS prototype occupies 0.17 mm2 and dissipates 3.2 mW from 1.2 V at the quiescent point. The measured SNR sensitivity is 8 dB and the demodulator bit-error rate is 0.1% at 10 Mb/s for a 45-mVpp input signal at IF. [ABSTRACT FROM AUTHOR]

This paper demonstrates a systematic approach for the design of broadband, high efficiency, high power, Class-AB RF amplifiers with high gain flatness. It is usually difficult to simultaneously achieve high gain flatness and high efficiency in a broadband RF power amplifier, especially in a high power design. As a result, the use of computer-aided simulation is most often the best option to achieve these goals, but a systematic approach with an appropriate initial value is necessary to rapidly converge the simulation results. In this way, the above objectives can be achieved with minimum trial and error. Signal gain variations are reduced over a wide bandwidth using a proper pre-matching network. Source and load impedances are satisfactorily obtained from small-signal and load-pull simulations, respectively. Two high-order Chebyshev low-pass filters are employed to provide optimum input and output impedance matching networks over 100-500 MHz. The resulting power amplifier yields good performance over an octave of bandwidth, 44.2-44.8 dBm output power at the 1-dB gain compression point, 16.5 ± 0.3 dB gain, and greater than 52% power-added efficiency throughout the band. Using a non-linear model of the transistor and an EM simulation for the substrate, it is observed that the simulated results are in close agreement with measured results. [ABSTRACT FROM AUTHOR]

This article suggests a broadband linear power amplifier (PA) for DC-10 GHz for Fifth-generation (5G) and multi-standard applications using 180 nm CMOS technology. The suggested radio frequency power amplifier is appropriate for wideband LTE, IoT, WSN, multi-standard, and 5G radio frequency transmitters. T -coil peaking and bridged-shunt-series peaking amplifiers are used for bandwidth extension and gain flatness. Also, the interstage matching inductors between common source and common gate transistors are applied to improve radio frequency achievement. The suggested PA consists of four stages as follows; input stage, two stages using the T -coil peaking technique, and the last stage utilizing bridged-shunt-series peaking topology. The input stage is a complementary current reuse (CCR) common gate with active shunt feedback (SFB) architecture. It is utilized to extend the matching of RF input impedance with agreeable linearity and power gain at little power consumption. The second stage works in class-C operation to enhance the efficiency and reduce DC power consumed whereas the class-AB mode is utilized in the third and fourth stages to improve the output power. The suggested PA obtains a peak constant power equal to 14.25 dBm, a maximum Power-Added-Efficiency (PAE) of 16 %, and a peak gain equal to 22 dB. The proposed power amplifier dissipates a DC power of 80 mW. The die size of the proposed power amplifier equals 1 m m 2 , whereas the total chip size includes the pads is 1.62 m m 2. [ABSTRACT FROM AUTHOR]

This paper presents a load-adaptive Class-G headphone amplifier to improve the power efficiency for different headphone impedances. For an impedance value, the amplifier utilizes two techniques, voltage rails selection and Class-G switching activity control, to reduce the power dissipation of the amplifier and the power loss of a Class-G power generator, respectively. In addition, a supply-rejection bandwidth enhancement technique for the Class-AB output stage is proposed to suppress the out-of-band noise by the Class-G supply rails switching. Compared with the conventional fixed 2-level Class-G amplifier, the integrated 0.18~\mu \text m CMOS amplifier improves the total-path efficiency to 37% from 31% (1.45 mA current can be saved from a 1.8 V supply) while delivering 5 mW into a $16~\Omega $ . The PSRR of the amplifier is 130 dB at 217 Hz and is still larger than 100 dB up to 20 kHz. Finally, the decoder and amplifier together achieve 108 dB DR and 95 dB SNDR with a $16~\Omega $ headphone load. [ABSTRACT FROM PUBLISHER]

This paper presents a complementary push-pull 60-GHz power amplifier (PA) in 40-nm CMOS. The proposed technique is used to mitigate the amplitude to phase modulation (AM-PM) distortion caused by the nonlinear input capacitance of an MOS transistor. By operating in deep class-AB mode, the back-off efficiency of the PA is improved without compromising gain. The proposed interstage transformer with two secondary windings enables right impedance transformation concurrently for the two separate transistors with independent biasing ability. The two-stage PA achieves a gain of 22.4 dB, power added efficiency (PAE) PAEMAX of 23%, and saturated output power ( P\text {SAT} ) of 16.4 dBm with 8% PAE at 6 dB back-off. With <0.8° AM-PM distortion, the linearity is demonstrated by amplifying a 250-MHz 3-Gb/s 64-QAM signal with 7 dBm of average output power and achieve an error vector magnitude (EVM) of −25.2 dB and >35 dB of adjacent channel power ratio. Also a comparison with a common-source PA is presented, which shows its limitation in dealing with AM-PM distortion. [ABSTRACT FROM PUBLISHER]

Two Voltage followers (VF) suited to low-voltage operation and able to operate with a high-slew rate and low-output impedance are presented. The buffer core is based on the flipped voltage follower (FVF) which is previously presented in literature. A detailed comparison of proposed buffers and other voltage followers is presented. These buffers have been simulated using 0.18 μm CMOS technology models provided by TSMC. The buffers consume 10 μA from 1.2 V supply and have a power consumption of 25 μw. The first and second proposed buffers have slew rate of 13 V/μs and 32 V/μs, respectively, with output impedance of about 50 Ω. [ABSTRACT FROM AUTHOR]

This paper presents a high-efficiency wideband hybrid supply modulator (HSM). We show that proper control of the average current from the class-AB linear amplifier (LA) and proper selection of the inductor value are essential to efficiency optimization. In line with the above criteria, a single-capacitor current-integration (SCCI) control method is proposed. Current integration is achieved by using a single capacitor, circumventing the need of the high-speed full-range current sensor required for conventional HSMs and reducing the design complexity greatly. The ripple current of the LA is controlled indirectly, and enhanced efficiency is achieved by enforcing the average output current from the LA to be around zero. A wideband LA is proposed to suppress the output voltage ripple. A proof-of-concept design using an inductor with an optimized value of 100 nH is fabricated in 130 nm CMOS technology. It switches at a peak frequency of 50 MHz, achieves up to 8% efficiency improvement when compared to recent works, and is able to track a 0.8\;\textV_\textpp sinusoidal signal with high fidelity up to 10 MHz. The measured output voltage ripple is reduced to below 8 mV. The peak conversion efficiency is 88.3% at the maximum output power of 23 dBm. [ABSTRACT FROM PUBLISHER]

A low total harmonic distortion (THD) programmable gain amplifier (PGA) with dual operational amplifiers (op-amps) for electrocardiogram (ECG) signal acquisition applications is presented. The proposed op-amp comprises the rail-to-rail input stage and class-AB output stage. To solve the transconductance (g m) variation caused by the supply voltage changes in rail-to-rail amplifiers with the traditional DC level-shifting technique, a common-mode-detection-based transconductance linearization scheme is proposed in this paper, associated with a 7-steps resistor-feedback digital gain control from 1 V/V to 12 V/V, which can realize less than 2.7% transconductance variations. The proposed rail-to-rail class-AB PGA is implemented in 0.18- μ m CMOS technology with 2.7-V ∼ 5-V power supply voltage and 0.07-mm 2 core area. Spice simulation results show that the THD is − 110 dB with an input signal of 5 mV p p and the input-referred noise spectrum density is 0.5 μ V/ H z at a 10-Hz frequency point, after adopting an 8-kHz chopping. The total power consumption including the bias circuit is 81 μ W at 2.7 V. [ABSTRACT FROM AUTHOR]

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15 MHz LP bandwidth, 2–8 MHz CBP bandwidth and 0–36 dB gain range with 1 dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65 nm CMOS. It achieves 15.2 dB m/27.1 dB m IB/OB-IIP3, −2 dB m IP1dB and 71 dB m IIP2 while consuming 3.6–9.1 mW from a 1.2 V power supply and 0.75 mm 2 chip area. [ABSTRACT FROM AUTHOR]

A CMOS saturated power amplifier (PA) is developed for optimally implementing the envelope-tracking (ET) transmitter. The CMOS saturated PA is used to maximize the efficiency of the ET PA. The dynamic feedback control and the biasing techniques at the gates of the common-gate stage and the common-source of the cascode structure are proposed to improve the dynamic range, linearity and efficiency. The fully-integrated CMOS PA with a supply modulator is fabricated using a 0.18-\mum RF CMOS technology. For a long-term evolution signal at 1.85 GHz with a 10-MHz bandwidth and a 16-quadrature amplitude modulation 7.5 dB peak-to-average power ratio, the ET-based CMOS PA module delivers a power-added efficiency of 37.6%, an error vector magnitude of 2.4%, and an an evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE\-UTRA) of -36.8 dBc at an average output power of 26.5 dBm. The proposed auxiliary circuits enable the ET-based CMOS PA to provide the significantly improved performance. [ABSTRACT FROM AUTHOR]