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A direct current (DC) compact model for negative capacitance field-effect transistors (NCFETs) based on a metal-ferroelectric-insulator-semiconductor (MFIS) structure is proposed, considering the influence of deep-level interface trap states. To overcome the bottleneck problem of accurately and efficiently solving models, an explicit algorithm is developed, which is used to solve the complex Landau–Devonshire (LD) formula for the second-order phase transitions in physical models and the transcendental equation of trap density of states and surface potential. Compared with existing algorithms based on analytical surface potential, the new method does not require the numerical methods involving several iterations to obtain more accurate results, and the model can accurately reflect the opposite control effect of interface traps on surface potential and current under different ferroelectric (FE) thicknesses. The high precision of the model was verified through comprehensive numerical calculations and experimental data, indicating that the model can be effectively applied to circuit simulation design under low-power condition. [ABSTRACT FROM AUTHOR]

In this work, a surface-potential based compact model focusing on the quantum confinement effects of ultimately scaled gate-all-around (GAA) MOSFET is presented. Energy quantization with sub-band formation along the radius direction of cylindrical GAAs or thickness direction of nanosheet GAAs leads to significant quantization effects. An analytical model of surface potentials is developed by solving the Poisson equation with incorporating subband effects. In combination with the existing transport model framework, charge-voltage and current-voltage formulations are developed based on the surface potential. The model formulations are then extensively validated using TCAD numerical simulations as well as Si data of nanosheet GAA MOSFETs. Simulations of typical circuits verify the model robustness and convergence for its applications in GAA technology. [ABSTRACT FROM AUTHOR]

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore's era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented. [ABSTRACT FROM AUTHOR]

InGaN/GaN green micro‐light‐emitting diode (micro‐LED, μLED) arrays with varying device sizes down to 4 μm are fabricated and characterized. The size effects on current‐voltage and capacitance‐voltage characteristics are analyzed showing minimal sidewall effects only at low bias. The influence of pulse modulation frequency on luminance is also characterized and the effect of diode negative capacitance is discussed. Subsequently, a universal and comprehensive compact model for μLEDs are built based on these findings, which covers the capacitance frequency dispersion and size scaling effects. This work reveals the significance of frequency in the display driving strategy and provides design enablement for μLED micro‐display applications including augmented/mixed reality (AR/MR). [ABSTRACT FROM AUTHOR]

Dynamic memristors with short-term memory have been widely researched for their high biomimetic properties to mimic the leaky and integration functions of biological neurons. However, the limited reliability and poor switching window still hinder the implementation of dynamic memristors in a neuromorphic system. Here, we propose a highly reliable dynamic memristor with nanolayered NbO2 material based on the transition effect between two-electron emission processes. The introduced additional oxygen defects effectively enhance the electron emission effect and therefore enlarge the switching window over 107, accompanied by a low variation below 2%. Meanwhile, the designed conduction transition avoids the structural damage and the direct connection between two electrodes, benefiting the high endurance (>109) and low operating energy (19 fJ). Subsequently, we confirm the conduction transition mechanism during the dynamic behavior by data analysis, device surface expansion detection, and oxygen-controlled fabrication. The proposed mechanism is mathematically verified by a constructed compact model, which can be used not only to instruct the device fabrication but also to simulate neuron design. Based on the developed neuron with dynamic memristors, we construct a spiking neural network. The interaction between different aspects of the memristor in the network is discussed, which helps to achieve a reasonable compromise among the network accuracy (94.63%), energy consumption, and peripheral circuit requirements. [ABSTRACT FROM AUTHOR]

This paper presents numerical simulation and compact modeling of 2,7-Dioctyl {1} benzothieno {3,2-b}{1} benzothiophene (C8-BTBTC8) organic semiconductor-based TFT. It shows the entire modeling process flow of this organic semiconductor (OSC) and tests the device realization using a ring oscillator. The paper comprises OSC characterisation, band-gap modeling, electrostatic modeling, and capacitance modeling. The TCAD model consists of the Hopping and Pool Frenkel premise and characterizes the Density of State (DOS) for traps in deep and tail states. The findings from this research provide valuable information for improving OTFT models, enhancing their predictive accuracy, and advancing the understanding of organic semiconductor device behavior. The electrostatics demonstrate device structure dependency. [ABSTRACT FROM AUTHOR]

In thin‐film transistors (TFTs), issues such as interface states may lead to unstable device performance and complex physical phenomena, such as frequency dispersion effects. This paper establishes a three‐terminal TFT compact model capable of replicating capacitance dispersion phenomena and directly applying to SPICE circuit simulations. The model decomposes the transistor's capacitance frequency response into the superposition of responses from different electronic states. The different electronic states are emulated by parallel branches, each composed of voltage‐dependent capacitance and resistance connected in series. The Powell algorithm is employed to achieve automatic parameter optimization. The model is generic for TFTs and successfully replicates capacitance dispersion phenomena in carbon nanotube (CNT) and indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistors. This work provides insights to the circuit behavior of display driver circuits at high frequencies and improving circuit reliability. [ABSTRACT FROM AUTHOR]

Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths ( L r e f ), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model's validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

Leveraging poly(vinylidene fluoride-trifluoroethylene) [(PVDF-TrFE)] as the dielectric, we fabricated organic ferroelectric field-effect transistors (OFe-FETs). These devices demonstrate quasi-static transfer characteristics that include a hysteresis window alongside transient phenomena that bear resemblance to synaptic plasticity-encapsulating excitatory postsynaptic current (EPSC) as well as both short-term and long-term potentiation (STP/LTP). We also explore and elucidate other aspects such as the subthreshold swing and the hysteresis window under dynamic state by varying the pace of voltage sweeps. In addition, we developed an analytical model that describes the electrical properties of OFe-FETs, which melds an empirical formula for ferroelectric polarization with a compact model. This model agrees well with the experimental data concerning quasi-static transfer characteristics, potentially serving as a quantitative tool to improve the understanding and design of OFe-FETs. [ABSTRACT FROM AUTHOR]

A DC model is proposed for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) applicable to various active layer thicknesses. With the back surface potential and its coupling with the front surface potential being considered, an explicit potential solution is developed. Then, the analytical drain current and physical definition of threshold voltage are derived based on a non-chargesheet expression of free charge density. It is verified that in the previous models for AOS TFTs, typically ignoring the back surface potential and the active layer thickness effects could result in obvious deviations in the values of parameters during the characterization of DC performance, especially for scaled devices with low channel thicknesses. By comparing with numerical calculations and experimental data, this model is validated to be more suitable for AOS TFTs with decreased dimensions, which could give more realistic distributions of the density of states in the channel during parameter extraction.

In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.

We address the challenges associated with traditional analytical models, such as BSIM, in semiconductor device modeling. These models often face limitations in accurately representing the complex behaviors of miniaturized devices. As an alternative, Neural Compact Models (NCMs) offer improved modeling capabilities, but their effectiveness is constrained by a reliance on extensive datasets for accurate performance. In real-world scenarios, where measurements for device modeling are often limited, this dependence becomes a significant hindrance. In response, this work presents a large-scale pre-training approach for NCMs. By utilizing extensive datasets across various technology nodes, our method enables NCMs to develop a more detailed understanding of device behavior, thereby enhancing the accuracy and adaptability of MOSFET device simulations, particularly when data availability is limited. Our study illustrates the potential benefits of large-scale pre-training in enhancing the capabilities of NCMs, offering a practical solution to one of the key challenges in current device modeling practices.

In this paper, we address the problem of compact model parameter extraction to simultaneously extract tens of parameters via derivative-free optimization. Traditionally, parameter extraction is performed manually by dividing the complete set of parameters into smaller subsets, each targeting different operational regions of the device, a process that can take several days or weeks. Our approach streamlines this process by employing derivative-free optimization to identify a good parameter set that best fits the compact model without performing an exhaustive number of simulations. We further enhance the optimization process to address three critical issues in device modeling by carefully choosing a loss function that focuses on relative errors rather than absolute errors to ensure consistent performance across different orders of magnitude, prioritizes accuracy in key operational regions above a specific threshold, and reduces sensitivity to outliers. Furthermore, we utilize the concept of train-test split to assess the model fit and avoid overfitting. We demonstrate the effectiveness of our approach by successfully modeling a diamond Schottky diode with the SPICE diode model and a GaN-on-SiC HEMT with the ASM-HEMT model. For the latter, which involves extracting 35 parameters for the ASM-HEMT DC model, we identified the best set of parameters in under 6,000 trials. Additional examples using both devices are provided to demonstrate robustness to outliers, showing that an excellent fit is achieved even with over 25% of the data purposely corrupted. These examples demonstrate the practicality of our approach, highlighting the benefits of derivative-free optimization in device modeling.

Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi-gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to $\sim ~50$ nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation-resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.

In integrated circuit design compact models are the abstraction layer which connects semiconductor physics and circuit simulation. Established compact models like BSIM provide a powerful platform for many kinds of conventional MOSFETs. However, novel device concepts like reconfigurable FETs (RFETs) come with a higher expressiveness. Due to their altered transport physics as compared to classical inversion mode MOSFETs those devices are hard to describe in a closed form expression by classical compact models. Table models bridge this gap for devices with novel features or materials, but circuit simulation becomes slow and inaccurate due to interpolation and convergence difficulties. Table model data can, however, be translated to closed form expressions, providing equation based models without the need for interpolation during simulation time. This work shows data driven approaches to generate compact models from biasing tables without physical analysis of the device behavior. Two automated modeling techniques are applied to a recently emerged RFET, forming a Verilog-A compact model for DC and transient simulation in Cadence Virtuoso. Drive current is implemented as a neural network, large enough to accurately predict behavior of a multi-gate device. The high dynamic range from $mA$ to $pA$ is covered by combining a linear model for high currents and a logarithmic model for low currents. For transient simulation precise models for electrode charges are essential. Here, symbolic regression provides human-readable closed form expressions which allow direct implementation in Verilog-A. The compact model approach is demonstrated with device data generated from a structural technology model (TCAD). However, the entire modeling flow can directly be used on real device measurements, if a technology model is unavailable or unpractical. We show that the presented machine learning based compact models show better convergence, more accurate predictions and faster simulation $(82$ to 308 times) in Cadence SPECTRE than simple table models generated from the same device.

In this paper, a gate bias-dependent velocity-field relationship model and a physics-based analytical model of current-voltage characteristics in AlGaN/GaN HFETs are developed. Based on Monte Carlo simulations, the experimental phenomenon that the channel electron velocity varies with the gate voltage is successfully reproduced. A modified gate bias-dependent velocity-field relationship model is established to obtain the velocity-field relationship of our fabricated AlGaN/GaN HFETs considering Polarization Coulomb Field (PCF) Scattering. This new velocity-field model can accurately describe the experimental phenomenon of velocity modulation by various gate biases and effectively reduce the fitting parameters. The parameters of the velocity-field model are incorporated into the compact model. The method cleverly maintains the direct relation between the velocity-field model parameters and AlGaN/GaN HFETs. All parameters have a specific physical meaning in our compact model and parasitic resistance factors and channel modulation effects are also incorporated. We validate the model with experimental data for AlGaN/GaN HFETs with gate lengths of $0.2~\mu \text{m}$ and $0.35~\mu \text{m}$ , respectively, and obtain good agreement.

The artificial neural network (ANN)-based compact model has significant advantages over physics-based standard compact models such as BSIM-CMG because it can achieve higher accuracy over a wide range of geometric parameters. This makes it particularly suitable for design space exploration and optimization. However, the ANN-based compact model using only one set of model parameters (global-ANN) requires larger model sizes to achieve wider coverage and higher accuracy in order to capture the unpredictable nonlinearities of emerging devices. This results in reduced simulation speed and a trade-off between simulation accuracy, model coverage, and simulation speed makes it difficult to utilize ANN-based compact models in a variety of ways. To solve this problem, we propose the first ANN-based compact modeling flow using a binning method (binning-ANN) and we address the training requirements and data sparsity issues that may occur due to the binning method in ANNs. In addition, we develop a bin size optimization guideline for the binning-ANN. As a result, the binning-ANN not only has higher accuracy, but also much better expandability than existing methods.

Resistive random access memory (RRAM), a new non-volatile memory, enables hardware accelerators based on in-memory computing with improved throughput and energy efficiency, enabling machine learning on-the-fly inference at the edge. However, sneak-path currents in RRAM crossbar arrays (CBAs) can cause crosstalk, limiting high-density applications. The best choice for suppressing leakage current is self-rectifying RRAM (SRR). Interface-type RRAMs offer CMOS compatibility, better controllability, higher reliability, and lower power consumption compared to filament-type counterparts. However, while there is much research on the filament-type RRAMs, there is little research and no measurement validation on the interface-type RRAMs. In this paper, a compact model of the interface-type RRAM is developed for circuit and system exploration. The model includes Schottky barrier diode, effective layer resistance, nano-battery effect, parasitic resistance, and capacitance. It also has a dynamic behavior model, including device-to-device variation, retention, and endurance. Compared with measurements, it reproduces high accuracy of 98.97% in DC and 98.05% in AC. The proposed model is applied to a neuromorphic $64\times64$ SRR CBA with 32-bit fixed-point precision. A nano-battery bias scheme is also proposed to zero the current of RRAMs having non-zero I-V crossing points, reducing the sneak-pass current error to 0.02%. A vector matrix multiplication application demonstrates 3.44 TOPS/W with a 50:50 LRS to HRS ratio, and a deep neural network on a VGG-8 architecture using the CIFAR-10 dataset observes an accuracy degradation of 1.36%.

Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node. [ABSTRACT FROM AUTHOR]

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. [ABSTRACT FROM AUTHOR]

As the semiconductor industry enters the post-Moore era, the carbon nanotube field-effect transistor (CNTFET) has become a powerful substitute for silicon-based transistors beyond 5 nm process nodes due to its high mobility, low power consumption, and ultra-thin-body electrical advantages. Carbon-based transistor technology has made significant progress in device manufacture and preparation, but carbon-based process design kits (PDKs) that meet the standards of commercial design tools are still an important bottleneck hindering the development of carbon-based integrated circuits. For the first time, a complete full-custom 90 nm CNTFET PDK is proposed in this paper, which includes Pcells for transistors, resistors, and capacitors; a compact model; DRC/LVS/PEX rules; and a standard cell and timing library. It can support the entire design flow of analog, digital, and mixed-signal carbon-based integrated circuits. To achieve an accurate compact model, the back-gate effect of CNTFETs and the influence of gate/drain voltage on transport probability are analyzed. Then the theoretical formulas for mobility and channel current are established. The comparison of the simulation and test results of CNTFET characteristics proves the accuracy of the compact model. Using this PDK, combined with standard IC design tools and design flow, the circuit and layout of an operational amplifier, SRAM, and 8-bit counter are completed. The simulation results verify the correctness and effectiveness of the PDK, laying a solid foundation for the large-scale industrialization of carbon-based integrated circuits. [ABSTRACT FROM AUTHOR]

As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01. [ABSTRACT FROM AUTHOR]

Investigations in the field of spiking neural networks (SNNs) encompass diverse, yet overlapping, scientific disciplines. Examples range from purely neuroscientific investigations, researches on computational aspects of neuroscience, or applicative-oriented studies aiming to improve SNNs performance or to develop artificial hardware counterparts. However, the simulation of SNNs is a complex task that can not be adequately addressed with a single platform applicable to all scenarios. The optimization of a simulation environment to meet specific metrics often entails compromises in other aspects. This computational challenge has led to an apparent dichotomy of approaches, with model-driven algorithms dedicated to the detailed simulation of biological networks, and data-driven algorithms designed for efficient processing of large input datasets. Nevertheless, material scientists, device physicists, and neuromorphic engineers who develop new technologies for spiking neuromorphic hardware solutions would find benefit in a simulation environment that borrows aspects from both approaches, thus facilitating modeling, analysis, and training of prospective SNN systems. This manuscript explores the numerical challenges deriving from the simulation of spiking neural networks, and introduces SHIP, Spiking (neural network) Hardware In PyTorch, a numerical tool that supports the investigation and/or validation of materials, devices, small circuit blocks within SNN architectures. SHIP facilitates the algorithmic definition of the models for the components of a network, the monitoring of states and output of the modeled systems, and the training of the synaptic weights of the network, by way of user-defined unsupervised learning rules or supervised training techniques derived from conventional machine learning. SHIP offers a valuable tool for researchers and developers in the field of hardware-based spiking neural networks, enabling efficient simulation and validation of novel technologies. [ABSTRACT FROM AUTHOR]

In this paper, we propose a graph model embedded with compact physical equations for modeling the thermal dynamics of buildings. The principles of heat flow across various components in the building, such as walls and doors, fit the message-passing strategy used by Graph Neural networks (GNNs). The proposed method is to represent the multi-zone building as a graph, in which only zones are considered as nodes, and any heat flow between zones is modeled as an edge based on prior knowledge of the building structure. Furthermore, the thermal dynamics of these components are described by compact models in the graph. GNNs are further employed to train model parameters from collected data. During model training, our proposed method enforces physical constraints (e.g., zone sizes and connections) on model parameters and propagates the penalty in the loss function of GNN. Such constraints are essential to ensure model robustness and interpretability. We evaluate the effectiveness of the proposed modeling approach on a realistic dataset with multiple zones. The results demonstrate a satisfactory accuracy in the prediction of multi-zone temperature. Moreover, we illustrate that the new model can reliably learn hidden physical parameters with incomplete data.

In order to predict the lifetime of InP Heterojunction Bipolar Transistor (HBT) devices and related circuits in the space radiation environment, a novel model including gamma radiation effects is proposed in this paper. Based on the analysis of radiation-induced device degradation effects including both DC and AC characteristics, a set of empirical expressions describing the device degradation trend are presented and incorporated into the Keysight model. To validate the effective of the proposed model, a series of radiation experiments are performed. The correctness of the novel model is validated by comparing experimental and simulated results before and after radiation.

Investigations in the field of spiking neural networks (SNNs) encompass diverse, yet overlapping, scientific disciplines. Examples range from purely neuroscientific investigations, researches on computational aspects of neuroscience, or applicative-oriented studies aiming to improve SNNs performance or to develop artificial hardware counterparts. However, the simulation of SNNs is a complex task that can not be adequately addressed with a single platform applicable to all scenarios. The optimization of a simulation environment to meet specific metrics often entails compromises in other aspects. This computational challenge has led to an apparent dichotomy of approaches, with model-driven algorithms dedicated to the detailed simulation of biological networks, and data-driven algorithms designed for efficient processing of large input datasets. Nevertheless, material scientists, device physicists, and neuromorphic engineers who develop new technologies for spiking neuromorphic hardware solutions would find benefit in a simulation environment that borrows aspects from both approaches, thus facilitating modeling, analysis, and training of prospective SNN systems. This manuscript explores the numerical challenges deriving from the simulation of spiking neural networks, and introduces SHIP, Spiking (neural network) Hardware In PyTorch, a numerical tool that supports the investigation and/or validation of materials, devices, small circuit blocks within SNN architectures. SHIP facilitates the algorithmic definition of the models for the components of a network, the monitoring of states and output of the modeled systems, and the training of the synaptic weights of the network, by way of user-defined unsupervised learning rules or supervised training techniques derived from conventional machine learning. SHIP offers a valuable tool for researchers and developers in the field of hardware-based spiking neural networks, enabling efficient simulation and validation of novel technologies.

Computation-in-memory (CIM) chips offer an energy-efficient approach to artificial intelligence computing workloads. Resistive random-access memory (RRAM)-based CIM chips have proven to be a promising solution for overcoming the von Neumann bottleneck. In this paper, we review our recent studies on the architecture-circuit-technology co-optimization of scalable CIM chips and related hardware demonstrations. To further minimize data movements between memory and computing units, architecture optimization methods have been introduced. Then, we propose a device-architecture-algorithm co-design simulator to provide guidelines for designing CIM systems. A physics-based compact RRAM model and an array-level analog computing model were embedded in the simulator. In addition, a CIM compiler was proposed to optimize the on-chip dataflow. Finally, research perspectives are proposed for future development. [ABSTRACT FROM AUTHOR]

A compact model for the drain current of a double-gate tunnel field-effect transistor (TFET) operating in the subthreshold and super-threshold regions is proposed in this paper. Using this drain current model, the key parameter for integrated analog circuit design technology, namely the transconductance-to-drain current ratio, was extracted. As this method is simple, it can be readily implemented for any type of dual-gate TFET with a few fitted parameters. The drain current calculated using this model was compared with the simulated drain current using 2D Sentaurus TCAD software, which validated the performance of the TFET. The proposed method can be adapted to obtain the desired transconductance to operate TFETs in the gigahertz range with very low-milliwatt power consumption. [ABSTRACT FROM AUTHOR]

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

Extracting behavioral models of RRAM devices is challenging due to their unique "memory" behaviors and rapid developments, for which well-established modeling frameworks and systematic parameter extraction processes are not available. In this work, we propose a physics-informed recurrent neural network (PiRNN) methodology to generate behavioral models of RRAM devices from practical measurement/simulation data. The proposed framework can faithfully capture the evolution of internal state and its impacts on the output. A series of modifications informed by the RRAM device physics are proposed to enhance the modeling capabilities. The integration strategy of Verilog-A equivalent circuits, is also developed for compatibility with existing general-purpose circuit simulators. The Verilog-A model can be easily adopted into the SPICE-type simulator for the circuit design with a variable step that differs from the training process. Numerical experiments with real RRAM devices data demonstrate the feasibility and advantages of the proposed methodology. [ABSTRACT FROM AUTHOR]

In this paper, we study the robust multi-plant capacitated lot-sizing problem with uncertain demands, processing and setup times. This problem consists of a production system with more than one production plant, in which each plant can produce items to meet its demand or transfer items to other plants. The objective is to determine a minimum-cost production and transfer plan considering the compromise between production, inventory, and transfer costs. Using a static robust optimization approach, we propose two different robust mixed-integer programming formulations for the problem. The first formulation applies the standard duality technique to the constraints involving uncertain parameters while the second applies the duality technique only to the time constraints and introduces new parameters, accumulating the worst-case demand realizations, to the inventory balance constraints. This second formulation has the advantage of resulting from a more intuitive and straightforward approach. We perform extensive computational experiments to compare the performance of the formulations and to assess the effect of different budgets of uncertainty on the solutions. Moreover, we observe that demand, processing and setup times have different impacts when taking uncertainty into account. [ABSTRACT FROM AUTHOR]

This paper presents an improved multi-level simulation framework for 2D material-based nanoelectronics, which expands from device simulation, physics-based compact modeling, and circuit benchmarking, using the germanane (GeH) metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example. The device simulation employs the non-equilibrium Green's function method to obtain the characteristics of 2D GeH MOSFETs for both n-type MOSFETs and p-type MOSFETs. A compact model based on the MIT virtual source model is then revised to capture the unique behaviors of 2D-material-based MOSFETs, including voltage dependency of virtual source velocity and drain-induced barrier lowering, as well as the effect of quantum capacitance. HSPICE circuit simulations are performed to analyze and optimize CMOS digital benchmark circuits. The case study demonstrates that 2D material-based transistors favor a different range of supply voltage and threshold voltage than their silicon counterpart, to achieve the optimal energy-delay product. The impact of contact resistance is also analyzed using the proposed framework. This study offers a seamless multi-level simulation approach to bridge the gap between nanoelectronics and circuit behavior, thereby advancing the understanding of materials, devices, and circuits comprehensively. The framework tailored for GeH MOSFETs provides accurate device-circuit co-optimization which can be easily extended to devices based on other 2D materials. [ABSTRACT FROM AUTHOR]

In the processor-memory separated von-Neumann computation paradigm, the “memory-wall” effect becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and its related cryogenic bit-cell are investigated, based on 77 K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Compared with the simulated room temperature results, 70% reduction of sensing latency can be obtained at 0.7 V supply voltage, whereas writing latency and yield performance are significantly degraded. In order to overcome the above drawbacks, a novel joint trimming system is proposed including a build-in-self-test (BIST) block and a string of multi-stage level shifters (LS). A case study is executed with in-MRAM computing (IMC). Results show that cryogenic IMC with write trimming provides performance improvements of 33% on average, and concurrently reduces memory energy consumption by 70% on average. The proposed 77 K cryogenic design method can be further applied to other energy constrained applications. [ABSTRACT FROM AUTHOR]

This paper presents a compact model for organic thin-film transistors fabricated in the staggered or coplanar device architecture which includes short-channel effects related to the potential barrier in the channel region, which manifest themselves as threshold voltage roll-off, drain-induced barrier lowering, and subthreshold swing degradation. Furthermore, the effect of non-linear injection due to a work-function mismatch between the source/drain contacts and the semiconductor is considered. The model includes a charge-based capacitance model considering overlap and fringing regions in short-channel multi-finger layout structures. Extensions include a model for drain-current variability, low-frequency noise and non-quasistatic effects. The introduction of physically meaningful fitting parameters provides a high degree of flexibility to the model. The equation package is verified using the results of measurements performed on transistors fabricated on flexible substrates and is available in Verilog-A for an efficient circuit simulation on different design platforms.

This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.

This article presents a modified compact model of resistive random access memory (RRAM) with a tunneling barrier. The bilayer modulated RRAM can be integrated into a higher density array, reducing leakage current in standby mode. The model demonstrates current transition behavior from low- to high-bias regions by considering both bulk-limited and electrode-limited transport mechanisms. This model can evaluate RRAM array performance under various pulsing conditions and device parameter variations with calibrated model cards. The compute-in-memory application requires precise current sum results hindered by the wire resistance loading effect. This study also evaluates various sizes of arrays suitable for performance improvement.

When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics. However, only a limited amount of data can be used since V-NAND processes are time-consuming and expensive in the early stage of development. TCAD and numerical methods also require a considerable amount of time and effort to calculate bit error rate (BER), and it is impossible to explore the entire design spaces in time. In this paper, we propose a novel simulation acceleration technique for bit error rate prediction and yield optimization in 3D V-NAND technology. This acceleration framework includes a machine learning (ML)-based compact model for the lognormal variability of GIDL currents and a physics-inspired slow cell model for the read margin reduction. Using a combination of these models with efficient Monte Carlo (MC) circuit simulations, we can accurately estimate threshold voltage ( $V_{th}$ ) distributions to explore the entire design spaces using a limited amount of data. Based on the proposed technique, the predictive model achieves high accuracy in the current 176-layer V-NAND technology, and it also provides high scalability with respect to GIDL transistor geometries, temperatures, supply voltages, variabilities, and the number of stacking layers. Moreover, a contour map of bit error rate is newly introduced for the efficient design space exploration and read margin prediction. Therefore, the results indicate that the proposed framework can be further extended to large-scale experimental data and new architectures to accelerate the yield optimization in next-generation 3D V-NAND flash memory development.

In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Carbon nanotube thin‐film transistor (CNT‐TFT) is expected to be a promising candidate for backplane technologies for emerging displays including micro‐LED, due to its extraordinary driving capability. In this work, CNT‐TFTs are characterized, which exhibit excellent on‐state current, high carrier mobility, and low subthreshold swing. Different from conventional TFTs, a positive threshold voltage shift under negative bias stress is observed in these devices. The mechanism is explored and explained, and an improved stretched‐exponential model is developed for such phenomenon. To predict the driving capability of CNT‐TFT backplane technology, compact models for CNT‐TFTs and micro‐LEDs are built based on experimental data, and SPICE simulation of a 3T1C pixel circuit is carried out. The results indicate that CNT‐TFTs enables high driving current in active‐matrix micro‐LED display with relative ease, paving the way for practical applications of CNT‐TFTs. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, traditional equation-based modeling faces challenges in accuracy and development time. To overcome these limitations, neural network (NN)-based modeling methods have been proposed. However, the NN-based compact model encounters two major issues. Firstly, it exhibits unphysical behaviors such as un-smoothness and non-monotonicity, which hinder its practical use. Secondly, finding an appropriate NN structure with high accuracy requires expertise and is time-consuming. In this paper, we propose an Automatic Physical-Informed Neural Network (AutoPINN) generation framework to solve these challenges. The framework consists of two parts: the Physics-Informed Neural Network (PINN) and the two-step Automatic Neural Network (AutoNN). The PINN is introduced to resolve unphysical issues by incorporating physical information. The AutoNN assists the PINN in automatically determining an optimal structure without human involvement. We evaluate the proposed AutoPINN framework on the gate-all-around transistor device. The results demonstrate that AutoPINN achieves an error of less than 0.05%. The generalization of our NN is promising, as validated by the test error and the loss landscape. The results demonstrate smoothness in high-order derivatives, and the monotonicity can be well-preserved. We believe that this work has the potential to accelerate the development and simulation process of emerging devices. [ABSTRACT FROM AUTHOR]

A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs. [ABSTRACT FROM AUTHOR]

Leveraging poly(vinylidene fluoride-trifluoroethylene) [(PVDF-TrFE)] as the dielectric, we fabricated organic ferroelectric field-effect transistors (OFe-FETs). These devices demonstrate quasi-static transfer characteristics that include a hysteresis window alongside transient phenomena that bear resemblance to synaptic plasticity-encapsulating excitatory postsynaptic current (EPSC) as well as both short-term and long-term potentiation (STP/LTP). We also explore and elucidate other aspects such as the subthreshold swing and the hysteresis window under dynamic state by varying the pace of voltage sweeps. In addition, we developed an analytical model that describes the electrical properties of OFe-FETs, which melds an empirical formula for ferroelectric polarization with a compact model. This model agrees well with the experimental data concerning quasi-static transfer characteristics, potentially serving as a quantitative tool to improve the understanding and design of OFe-FETs.

Presents corrections to the paper, (Corrections to “Modeling of the Gate Bias- Dependent Velocity-Field Relationship and Physics-Based Current-Voltage Characteristics in AlGaN/GaN HFETs”).