26 results on '"de Barros Naviner, Lirida Alves"'
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2. Efficient reliability evaluation methodologies for combinational circuits
3. Sparse Realization in Unreliable Spin-Transfer-Torque RAM for Convolutional Neural Network
4. Triple Sensing Current Margin for Maintainable MRAM Yield at Sub-100% Tunnel Magnetoresistance Ratio
5. Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration
6. Exploring Hybrid STT-MTJ/CMOS Energy Solution in Near-/Sub-Threshold Regime for IoT Applications
7. Sparsity analysis using a mixed approach with greedy and LS algorithms on channel estimation
8. Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology
9. High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects.
10. Multiplexing Sense-Amplifier-Based Magnetic Flip-Flop in a 28-nm FDSOI Technology
11. Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction
12. A Non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction-Based Circuits.
13. A study of statistical variability-aware methods
14. Flip-Flop Selection for In-Situ Slack-Time Monitoring based on the Activation Probability of Timing-Critical Paths
15. Analytical method for reliability assessment of concurrent checking circuits under multiple faults
16. Simulation study of aging in CMOS binary adders
17. Shadow-scan design with low latency overhead and in-situ slack-time monitoring
18. Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults
19. Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection
20. Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy.
21. Efficient implementation for accurate analysis of CED circuits against multiple faults.
22. Reliability-aware delay faults evaluation of CMOS flip-flops.
23. Majority voter: Signal probability, reliability and error bound characteristics
24. A simple fault-tolerant digital voter circuit in TMR nanoarchitectures
25. Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
26. Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy.
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