219 results on '"de Souza, Michelly"'
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2. Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs
3. Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors
4. Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures
5. Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K.
6. Junctionless nanowire transistors parameters extraction based on drain current measurements
7. (Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs
8. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
9. Experimental Assessment of Gate-Induced Drain Leakage in Soi Stacked Nanowire and Nanosheet Nmosfets at High Temperatures
10. Impact of Series Resistance on the Drain Current Variability in Inversion Mode and Junctionless Nanowire Transistors
11. High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs
12. On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
13. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
14. Comparative of Analog Performance of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs
15. Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures
16. Analysis of Variability in Transconductance and Mobility of Nanowire Transistors
17. Variability Modeling in Triple-Gate Junctionless Nanowire Transistors
18. Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures
19. Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs
20. An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires
21. Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
22. A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors
23. Approximate analytical expression for the tersminal voltage in multi-exponential diode models
24. Trap density characterization through low-frequency noise in junctionless transistors
25. Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors
26. Junctionless Nanowire Transistors Based Wilson Current Mirror Configuration
27. Analysis of Capacitances in Asymmetric Self-Cascode SOI nMOSFETs
28. Junctionless Nanowire Transistors Based Common-Source Current Mirror
29. Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures
30. Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model
31. Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer
32. Performance of SOI O-Gate Nanowires from Cryogenic to High Temperatures.
33. On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks
34. Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
35. The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime
36. Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs
37. Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature
38. Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion
39. Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current Model
40. Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short Wavelengths
41. Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic Regime
42. Study of Matching Properties of Graded-Channel SOI MOSFETs
43. Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFET’s
44. Temperature, Silicon Thickness and Intrinsic Length Influence on the Operation of Lateral SOI PIN Photodiodes
45. List of Reviewers - SBMicro2020 Special Section
46. Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations
47. Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation
48. Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors
49. Charge-Based Continuous Explicit Equations for the Transconductance and Output Conductance of Submicron Graded-Channel SOI MOSFET'S
50. Design, Fabrication and Performance of Microdevices for Infrared Detection Applications
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