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This paper proposes a delta-sigma modulator (DSM) for audio band applications with low-area cost and high-resolution performance characteristics. The proposed circuit is implemented by discrete-time switched capacitor circuits. It employs an assisted 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) as the quantizer. Most importantly, it combines and shares the resistive digital-to-analog (DAC) in DSM and SAR ADC. Therefore, it can achieve high-efficiency advantages and reduce the chip layout cost. After all, the chip area is only 0.096 mm2 by the 0.18 um 1P6M CMOS process. It achieves 96 dB dynamic range (DR), 83.1 dB signal to noise and distortion ratio (SNDR), and 93.4 dB signal to noise ratio (SNR) with 25 kHz signal bandwidth and oversampling ratio (OSR) of 64. [ABSTRACT FROM AUTHOR]

In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 GHz and a bandwidth of 20 MHz has been implemented using VHDL on an FPGA platform. The proposed architecture utilizes a single clock frequency for generating RF signals. The second-order DSM is reconfigurable, offering three filter modes: LP, BP at Fs/4, and HP for signal synthesis. Since the coefficients remain simple for all modes, multiplication operations can be achieved using a shifter block. To investigate the effect of duty-cycle-error (DCE) and its compensation, various error values are applied to the modulator and compensation is performed. A novel solution is proposed to overcome the DCE by adjusting the filter and unilaterally narrowing the signal passband without adding extra hardware complexity. This approach significantly enhances the SNDR and SFDR of the DSM output, even for the BP mode. Another challenge is the mismatch error in DAC cells. This error is simulated and compensated using two methods: DWA and SDEM. Simulation results in ISE demonstrate that the SNDR values for LP, BP, and HP modes are 106.10, 105.65, and 104.95 dB, respectively.

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This paper presents a highly efficient, low-power, compact mixed-signal sinusoidal current generator (CG) integrated circuit (IC) designed for bioelectrical impedance spectroscopy (BIS) with low total harmonic distortion (THD). The proposed system employs a 9-bit sine wave lookup table (LUT) which is simplified to a 4-bit data stream through a third-order digital delta–sigma modulator (ΔΣM). Unlike conventional analog low-pass filters (LPF), which statically limit bandwidth, the finite impulse response (FIR) filter attenuates high-frequency noise according to the operating frequency, allowing the frequency range of the sinusoidal signal to vary. Additionally, the output of the FIR filter is applied to a 6-bit capacitive digital-to-analog converter (CDAC) with data-weighted averaging (DWA), enabling dynamic capacitor matching and seamless interfacing. The sinusoidal CG IC, fabricated using a 65 nm CMOS process, produces a 5 μA amplitude and operates over a wide frequency range of 0.6 to 20 kHz. This highly synthesizable CG achieves a THD of 0.04%, consumes 19.2 μW of power, and occupies an area of 0.0798 mm2. These attributes make the CG IC highly suitable for compact, low-power bio-impedance applications. [ABSTRACT FROM AUTHOR]

In this research, we present a 16-bit multi-mode digital-to-analog converter (DAC) with a time-interleaved (TI) structure operating at a frequency of 4 GHz over a bandwidth (BW) of 20 MHz, which is in compliance with the fifth generation (5G) wireless communications. The proposed architecture uses only one clock frequency to generate radio frequency (RF) signals and includes a second-order (2nd-order) delta-sigma modulator (DSM) with a reconfigurable low-pass (LP) mode, band-pass (BP) mode at Fs/4, and high-pass (HP) mode for signal synthesis. To increase the sampling frequency (Fs) of the TI structure, four channels are proposed, each working at a frequency of Fs/4. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. This leads to design simplification, lower power consumption, smaller occupied area, and higher speed. A major challenge in designing this type of structure is the duty-cycle-error (DCE), especially in interleaved mode. In this research, we propose a new solution that solves DCE-related problems without adding digital circuits to the output of the DSM, by adjusting the analog filter circuit. Simulation results in MATLAB show that the value of signal-to-noise and distortion ratio (SNDR) in LP is equal to 106.14 dB, in BP is equal to 107.84 dB, and in HP is equal to 105.34 dB. Compensating for filters increases the spurious-free dynamic range (SFDR) to more than 118 dB. [ABSTRACT FROM AUTHOR]

A low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain. [ABSTRACT FROM AUTHOR]

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs). [ABSTRACT FROM AUTHOR]

In this paper, a fourth-order, OTA-free, single-bit, low-consumption discrete-time (DT) delta-sigma (ΔΣ) modulator with CIFF structure is proposed for hearing aid applications. In portable medical devices such as hearing aids that are used permanently, the battery life and energy dissipation are very important. In a typical delta sigma modulator, the power-hungry parts are the OTA. Therefore, the elimination of OTAs is a challenge, and the proposed modulator uses new differential parametric amplifiers, with dynamic thresholde in even stages and inverter-based amplifiers in odd delta sigma stages instead of the OTAs. The dynamic threshold PMOS technique has been used for the first time in differential MPA, and the theoretical analyzes and simulations performed show better performance than the traditional method. Also, a chopper circuit is used on the first fstage to reduce the harmonics and flicker noise. The proposed differential modulator is simulated using standard 180 nm CMOS technology, which achieves 90.5 dB SFDR and 64 dB SNDR with an input bandwidth frequency of 10 kHz and an oversampling ratio of 128. The power supply is 1V and the FOMW were obtained as 3.43 PJ/step.

Oversampling analog-to-digital converters (ADC) serve as the backbone of high-performance, high-precision data interfaces, owing to their remarkable ability to filter out quantization noise. This attribute makes them the preferred choice for applications requiring high signal-to-noise ratio (SNR) and moderate bandwidth, with great design flexibility. This paper provides an extensive survey of the latest advancements in oversampling ADC tailored for such applications as documented in recent literature. Specifically focusing on design techniques employed within the last five years, the survey encompasses various oversampling ADC architectures, including discrete-time and continuous-time $\Delta \Sigma $ , noise-shaping SAR, zoom, incremental, and time-domain modulators. A thorough performance comparison between these different topologies is presented, highlighting designs that achieve the best figures-of-merit. Furthermore, the paper explores circuit-level design trends commonly shared among these architectures, with particular attention given to amplifier designs for loop filters. Conclusions drawn highlight the limitations of much of the research works in the context of implementing ADC within complete systems, while also providing insight into the expected future trends that will shape the field moving forward.

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm2. It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively. [ABSTRACT FROM AUTHOR]

Instability is a design challenge with high-order delta-sigma modulator (DSM). DSM stability shows maximum stable amplitude (MSA) where it achieves adequate precision across the bandwidth. Increasing DSM order reduces the stable amplitude range. In addition, the design of an efficient noise transfer function (NTF) is necessary for the synthesis of a DSM. In this brief, a systematic method to design stable high-order DSM without the need for a stability-recovery mechanism is presented. The proposed design method can be used for high-order single-bit and multi-bit DSM with maximum stability. To achieve maximum DSM amplitude stability, systematic simulation is used to design coefficients and obtain SNR values at different points of bandwidth. Actual SNR values will ensure that the genetic algorithm will search and find optimum stability coefficients, the most important feature of the proposed method. The design method is implemented for two DSMs with different specifications and the results are compared with similar studies, showing that the proposed method has acceptable performance. [ABSTRACT FROM AUTHOR]

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate the switched-capacitor sizes for optimal signal to noise ratio (SNR) and minimum chip area. The coefficients in feedback path and input path are optimized to avoid the signal distortion under the full-scale input voltage range with almost no increase in total capacitance sizes. Fabricated in 0.5 µm CMOS technology and powered by a 5 V voltage supply, the proposed delta-sigma modulator can achieve 136 dB peak SNR with 16 Hz input and 137 dB dynamic range in 100 Hz signal bandwidth with an oversampling ratio of 512. The modulator dissipates 700 µA. The core chip area is 1.96 mm 2 . The modulator occupies 1.41 mm 2 and the decimator occupies 0.55 mm 2 . [ABSTRACT FROM AUTHOR]

This paper presents a low-ripple and high-efficiency buck–boost DC–DC converter with delta-sigma modulator controller that converts 1.8 V to 1.2 V and 3.3 V. A current and voltage closed-loop controller has been designed to achieve better performance simultaneously such as lower settling-time, steady-state error and over shoot and under shoot. The converter is started in the current controller mode initially, when the output voltage approaches the desired value, the power stage is controlled with the voltage controller mode. PI compensator and a third-order delta-sigma modulator are utilized in the voltage mode. Also, the closed-loop stability of the designed converter has been analyzed with Lyapunov method using converter nonlinear model. This work has been simulated in MATLAB-SIMULINK environment. The performance results show that the maximum efficiency of the closed-loop DC–DC converter is 90% at 5 MHz switching frequency, and the output voltage ripple is 0.5% and 0.6% for the buck and boost modes, respectively. Also, the simulation results demonstrate the closed-loop stability of the converter in the presence of 10% load variation. [ABSTRACT FROM AUTHOR]

The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexity timeinterleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four-branch timeinterleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal-tonoise- and-distortion ratio.

This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.

A low-power common-mode detector (LPCMD) with process, supply voltage and temperature (PVT)-compensation technique for the dynamic amplifier in delta-sigma modulator (DSM) is proposed. By adopting the varying supply voltages to compensate the variation of the transistors' threshold voltage, the proposed LPCMD improves the robustness of the dynamic amplifier (DA). Additionally, the auxiliary circuit providing the varying supply voltages is realized by the low-power regulator, which has the advantage of low power and low complexity. To demonstrate the feasibility of the proposed LPCMD with the PVT-compensation technique, a second-order 2-bit quantization-based DSM is designed in 180 nm CMOS technology and the postlayout simulation is performed. The DSM achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic range (SFDR) of 93 dB and 95 dB at the sampling frequency of 204.8 kHz, respectively, with the power consumption of 11 µW, leading to a 171.6 dB SNDR-based Schreier figure-of-merit (FoMSNDR). Furthermore, the SNDR degradation of the DSM under all process corner and temperature from − 40 to 125 ℃ is less than 3 dB. The postlayout simulation result of the DSM verifies the feasibility and effectiveness of the proposed LPCMD and PVT-compensation technique. [ABSTRACT FROM AUTHOR]

We present a novel switched-capacitor, integrator-multiplexing, second-order delta-sigma modulator (DSM) featuring a single differential difference amplifier (DDA). Power consumption is low and resolution is high when this DSM is used for portable electroencephalographic applications. A single DDA (rather than a conventional operational transconductance amplifier) with appropriate switch and capacitor architectures is used to create the second-order switched-capacitor DSM. The configuration ensures that the resolution is high. The modulator was implemented using a standard 180 nm complementary metal–oxide–silicon process. At a supply voltage of 1.8 V, a signal bandwidth of 250 Hz and a sampling frequency of 200 kHz, simulations demonstrated that the modulator achieved an 82 dB peak signal-to-noise–distortion ratio and an effective number of bits of 14. [ABSTRACT FROM AUTHOR]

In this paper, an ultra-low-power second-order, single-bit discrete-time (DT) double sampling ΔΣ modulator was proposed for hearing aid applications. In portable biomedical devices that are permanently used such as hearing aids, short battery lifetime and power dissipation are considerable issues. In a typical delta–sigma modulator, the most power-consuming parts are the operational transconductance amplifiers (OTAs), and their elimination without loss of efficiency is now challenging. This proposed modulator includes an ultra-low-power self-biased inverter-based amplifier with swing enhancement instead of power-hungry OTAs. Low voltage amplifier design reduces output swing voltage, affecting delta–sigma modulator efficiency and decreasing the signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) values. In this article, the proposed amplifier's source and tail transistors were biased in the sub-threshold region, increasing the output swing voltage significantly and leading to desired properties for a hearing aid modulator. The proposed amplifier peak-to-peak swing voltage was approximately 1.01 V at a 1 V power supply. In addition, the proposed modulator design used a standard 180 nm CMOS technology, which obtained 140 dB DR and 93.27 dB SNDR for a 10 kHz signal bandwidth with an oversampling ratio (OSR) of 128. Finally, the modulator's effective chip area was 0.02 mm2 and consumed only about 9.9 µW, while the figure of merit (FOMW) and FOMs achieved 1.31 fJ/step and 183.31, respectively. [ABSTRACT FROM AUTHOR]

The Common Public Radio Interface (CPRI) used in mobile fronthaul has low spectrum efficiency. In this paper, we propose to use Delta-Sigma Modulation (DSM) technology as a new fronthaul interface. In addition, to solve the problem of high computational complexity in the parameter searching of high-order stable Delta-Sigma modulator, Genetic Algorithm (GA) is used to search and optimize the structural parameters of the fourth-order Delta-Sigma modulator. The simulation results under the optimized structural parameters are compared with those under the original structural parameters. Under the condition of 1 bit quantization, the Delta-Sigma modulator with optimized parameters increases the transmission capacity of the system while the average Error Vector Magnitude (EVM) decreases from 0.031 to 0.028. In the case of 2 bit quantization, the average EVM decreases from 0.013 to 0.011.

The Common Public Radio Interface (CPRI) used in mobile fronthaul has low spectrum efficiency. In this paper, we propose to use Delta-Sigma Modulation (DSM) technology as a new fronthaul interface. In addition, to solve the problem of high computational complexity in the parameter searching of high-order stable Delta-Sigma modulator, Genetic Algorithm (GA) is used to search and optimize the structural parameters of the fourth-order Delta-Sigma modulator. The simulation results under the optimized structural parameters are compared with those under the original structural parameters. Under the condition of 1 bit quantization, the Delta-Sigma modulator with optimized parameters increases the transmission capacity of the system while the average Error Vector Magnitude (EVM) decreases from 0.031 to 0.028. In the case of 2 bit quantization, the average EVM decreases from 0.013 to 0.011.

In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 μ m CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 μ m CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of − 117 dBc/Hz@1 MHz and − 138 dBc/Hz @ 10 MHz, and the RMS jitter of 0.860 ps. The area of the proposed FDIV is 60 × 245 μ m 2 , and the power consumption is 1.356 mW. The phase noise of the proposed FNPLL in the fractional division mode is just 2 dB higher than that in the integer division mode. [ABSTRACT FROM AUTHOR]

The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software‐defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low‐complexity time‐interleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four‐branch time‐interleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal‐to‐noise‐and‐distortion ratio. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μ W from a 2.5 V supply and the core area is 0.55 mm 2 . This results in a Schreier figure of merit (FoM) of 184.7 dB. [ABSTRACT FROM AUTHOR]

A 1-bit band-pass delta-sigma modulator (BP-DSM), which utilizes oversampling technology, allows a modulated signal to be directly output by using a high-speed 1-bit digital pulse train, thus realizing miniaturization of transmitters. For 1-bit BP-DSM, the noise transfer function (NTF) is used to suppress quantization noise power in the transmission band and a guideline of out-of-band gain of $\vert \text {NTF}\vert < 1.5$ is used to prevent oscillation. However, in previous studies, such as Butterworth and inverse Chebyshev filters, the out-of-band gain was designed indirectly by tuning the zeros and poles in the transmission band and thus, was not stabilized sufficiently. Furthermore, even though the zeros of the NTF are identical to the poles of the loop filter, there are still widely used designs in which the zeros are set on the unit circle, making stabilization quite difficult. Therefore, in this paper, we propose a feasible implementation of the NTF for 1-bit BP-DSM with an elliptic filter that can be used to set not only in-band but also out-of-band gain, in which both the zeros and poles are set inside the unit circle. As a design result, a modulation bandwidth of 400 MHz as a relative bandwidth of 11%, a noise suppression bandwidth of 800 MHz, and an adjacent channel leakage power ratio of 50 dB were achieved at a center frequency of 3.6 GHz, enabling a wider bandwidth and higher SNR than before by improving the stability.

This article presents a 5-GS/s continuous-time (CT) multi-stage noise-shaping (MASH) analog-to-digital converter (ADC). The ADC consists of three first-order modulators with a 3-bit quantizer/digital-to-analog converter (DAC) per stage. An RC-hybrid stabilization DAC is used to compensate for the excess loop delay and excess phase shift. A delay matching all-pass input filter with a low-pass feedforward filter is employed to suppress input signal leakage. As a result, inter-stage DACs are waived in residue generation, and low-power, area-saving Gm-C integrators are enabled in the back-end stages. The MASH ADC was implemented in 40-nm CMOS and occupies 0.21 mm2. The ADC achieves 68-dB dynamic range (DR) and 65-dB signal-to-noise and distortion ratio (SNDR) over a 360-MHz bandwidth (BW). The ADC consumes 158 mW from 1/1.1/1.8 V supplies, yielding 159-dB Schreier figure-of-merit (FOM) and 151-fJ/Conv. Walden FOM. [ABSTRACT FROM AUTHOR]

This article presents a third-order voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) that leverages pseudo-virtual ground (PVG) feedforwarding (FF), linearizing the VCOs and enabling higher order noise shaping with a single feedback digital-to-analog converter. This technique leads to a power-efficient ADC implementation with a wide dynamic range. The ADC is fabricated in a 65-nm process and achieves a 92.1-dB SNDR in a 2.5-kHz bandwidth. This results in a state-of-the-art 179.6-dB figure-of-merit (FoM) among previously published VCO-based ADCs. The PVG FF technique allows the ADC to attain extremely high linearity, 123-dB peak SFDR, with a wide 1.8-Vpp differential input range. The ADC maintains performance with up to 200-mV variation on the 0.8-V supply and across temperatures from 0 to 70 °C. [ABSTRACT FROM AUTHOR]

Featured Application: Low noise circuit, delta-sigma modulator, analog to digital converter. This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator's architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA. [ABSTRACT FROM AUTHOR]

This article shows the design of a wideband 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta–sigma (I- $\boldsymbol {\Delta \Sigma }$) analog-to-digital converter (ADC). The two stages’ quantizers (QTZs) are implemented by a single re-configurable multibit (MB) asynchronous (A)SAR ADC. The digital-to-analog converter (DAC) nonlinearities are suppressed by reconfiguring the asynchronous successive-approximation register (ASAR) ADC from 2 to 5 b, and correspondingly, the DACs dynamically switch from 1.5- to 4-b tri-level outputs within each Nyquist conversion cycle. This results in a DAC-calibration-free MB operation. A two-tap FIR filter is implemented in the feedback DACs to reduce jitter requirements in the initial 1.5-b cycles. Through the design representation, a detailed fundamental comparison between an X-0 SMASH architecture and an X-order single-loop modulator is discussed. This discussion highlights the introduction of an efficient tri-level combination between the MSB and the LSBs of the ASAR QTZ. The resulting SMASH CT I- $\boldsymbol {\Delta \Sigma }$ modulator was fabricated in 28-nm CMOS technology with an active area of 0.125 mm2. It achieves 97-dB spurious-free dynamic range (SFDR) without calibration, 89-dB dynamic range (DR), and 81.2-dB SNDR in a 1-MHz bandwidth (BW). It consumes 3.6 mW from a single 0.9-V supply. The design shows very good robustness across different tested samples, supply variations, and across temperatures from −20 °C to 80 °C. [ABSTRACT FROM AUTHOR]

Among analog to digital converters, high speed ADCs are accomplished by the time interleaved delta-sigma modulators. The block digital filtering (BDF) method is a proper method to implement the Time-interleaved Delta-sigma modulators (TIDSM). In this method, M delta-sigma modulators are placed in parallel and the sampling rate in each of the parallel channel will be f s ,whereby the effective sampling rate become M ∗ f s . The serious disadvantage of the TIDSM based on BDF is that its NTF is equal to the standard structure. The time interleaved structure described in this paper is based on Noise Coupled time interleaved delta-sigma modulator (NC-TIDSM) that uses a noise-coupled between the channels. In this modulator not only the effective sampling is increased but also the overall noise transfer function order is increased by two or more without any additional active element. For implementation of the NC-TIDSM structure, the theoretical relations are proved and then these results have been verified by implementation of the second-order two-channel NC-TIDSM in circuit level and in an 180 nm CMOS technology. Using a 1.8 V supply, the SNDR of 62 dB in a 10 MHz signal band is achieved for the second-order two-channel NC-TIDSM. [ABSTRACT FROM AUTHOR]

This article presents two novel digital predistortion (DPD) based architectures that jointly mitigate the inphase/quadrature (IQ) modulator impairments and the power amplifier (PA) nonlinear distortion in wireless transmitters. The proposed architectures are multibit cartesian and complex delta-sigma modulator-based joint DPDs, called CDSM-JDPD and CXDSM-JDPD, respectively, which enable using low-cost digital-to-analog converters (DACs) while offering versatile linearization capabilities to combat the coexisting distortions of the PA and the IQ modulator. The proposed approach alleviates the need for reverse modeling and implementation of extra hardware to separately deal with frequency-dependent IQ impairments. Moreover, the CXDSM-JDPD enhances the linearization performance and relaxes the high oversampling ratio (OSR) requirement by quantizing the signal more efficiently. Furthermore, the presented concepts inherently support the use of low-resolution DACs, which offers a tremendous advantage in designing and implementing low-cost and energy-efficient radio transmitters. Extensive set of hardware-in-the-loop RF verification measurements with a commercial PA are provided, including two timely 5G New Radio (NR) scenarios at NR bands n3 and n78, while covering channel bandwidths up to 100 MHz and varying the OSR and the DAC bit resolution. The obtained results demonstrate the excellent linearization capabilities of the proposed solutions and their superiority compared to other DSM-based DPD approaches. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of two digital noise-cancellation circuits (DNCCs) using a proposed algorithm and a Karnaugh map for a 2 + 1 multistage noise-shaping (MASH) delta-sigma modulator (DSM). The MASH architecture inherits a superior signal-to-noise-and-distortion ratio (SNDR) with the aid of an efficient noise-cancellation technique either in the analogue or digital domain. The key motivation of this study was to design an area-efficient DNCC. The first approach employed a proposed algorithm (Algorithm-based DNCC) to implement the DNCC and to construct a delay block with an inverter and transmission gate. The second approach involved a Karnaugh map (K-map DNCC) and a delay block with a pair of D flip-flops. A maximum simulated signal-to-noise ratio of 135 dB was completed with optimal analogue scaling coefficients for the proposed 2 + 1 MASH DSM with DNCC. The simulated SNDRs of the Algorithm-based DNCC and K-map DNCC were 91.04 dB and 91.16 dB, respectively. Measured results show that the SNDR of the Algorithm-based DNCC, the SNDR of the K-map DNCC, power consumption and core area are approximately 58.7 dB, 62.1 dB, 0.26 μ W and 2275 μ m2, respectively, for the designed DNCCs with an operating frequency of 10.24 MHz and supply voltage of 1.8 V. The transistor counts of the Algorithm-based DNCC are 74 transistors, while they are 106 transistors for the K-map DNCC. The proposed Algorithm-based DNCC saves 32 transistors and approximately reduces its chip area to 69.8% of the K-map DNCC. [ABSTRACT FROM AUTHOR]

Highly stable on-chip frequency references offer the possibility of replacing crystal oscillators in many cost-and form-factor-constrained applications. However, achieving good frequency stability in a power-efficient manner across process, voltage, and temperature variations possess many design challenges. This article describes these challenges and presents a method for improving the integrated RC oscillator’s frequency accuracy by overcoming them. We show that the impact of resistor temperature coefficient (TC) on the accuracy of output frequency can be mitigated by using a parallel combination of two switched resistors that are digitally controlled by pulse-density modulated sequences. By trimming at only two temperatures, a prototype frequency-locked loop (FLL)-based 32-MHz oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of 530 ppm (8.4 ppm/°C), 80-ppm/V voltage sensitivity, 2.5-ppm Allan deviation, and 1- $\mu \text{W}$ /MHz power efficiency. [ABSTRACT FROM AUTHOR]

This paper proposed an improved low-electromagnetic-interference (EMI), high-efficiency fast-transient-response buck converter suitable for wireless sensor networks with new transient accelerated techniques. The proposed second-order delta-sigma modulator used the noise-shaping technique and the oversampling theorem to reduce the electromagnetic interference of the output spectrum. And then added the transient acceleration loop to accelerate the transient response also lowers the undershoot and overshoot voltage when the load current changed. The proposed converter has been implemented with TSMC $0.18~\mu \text{m}$ 1P6M process, and the chip area is $1.19 \times 1.19$ mm2 (including PADs). The measured results show that when the output voltage is 2 V and the load current changes from 100 mA to 500 mA and from 500 mA to 100 mA, the transient responses are $4 ~\mu \text{s}$ and $3 ~\mu \text{s}$ , and transient voltages are 18 mV and 30 mV, respectively. Compared to the traditional continuous-time delta-sigma-modulation converter improved $3 ~\mu \text{s}$ and $7 ~\mu \text{s}$. The maximum output voltage ripple is 30 mV. The output-to-noise ratio (ONR) is 72.15 dB with the sampling frequency of 10 MHz. When the load current is 100 mA and the output voltage is 2.5 V, the peak efficiency is 90.8%. [ABSTRACT FROM AUTHOR]

This work describes a microphone system featuring a new MEMS transducer based on a sealed-dual membrane (SDM) design paired with the latest generation of digital read-out ASIC. State-of-the-art noise performance is achieved thanks to significant optimizations both on the MEMS as well as on the ASIC side. The SDM design reduces significantly the magnitude of one of the main noise contributors by moving the air gaps to a sealed low-pressure chamber. The ASIC features an unconventional read-out amplifier based on a power-scalable current-feedback architecture as well as a reconfigurable $\Delta \Sigma $ modulator allowing to trade-off signal-to-noise ratio (SNR) versus power consumption. The microphone system achieves an SNR of 72dB(A) supporting an acoustical overload point (AOP) of 130dB SPL. This represents a significant improvement to current state-of-the-art digital microphones. [ABSTRACT FROM AUTHOR]

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This paper presents a cascode OTA assisted by a floating inverter amplifier, which offers high gain with reduced power consumption and excellent linearity. In comparison to conventional cascode OTA, it achieves approximately 30 % power savings while maintaining the same level of linearity. To address the limited output swing of the cascode OTA, the finite impulse response (FIR) DAC technique, which is widely used in CTDSM, is introduced in the DTDSM. The FIR DAC output resembles that of a multibit DAC without requiring a mismatch shaping circuit. By incorporating FIR DAC, we effectively scale up integrator coefficients and decrease power consumption of the first-stage integrator. A prototype was fabricated in a 0.18-μm CMOS process with an active area of 0.2 mm2, achieving peak SNDR/DR values of 94.5 and 96.5 dB while consuming only 190 μW of power. [ABSTRACT FROM AUTHOR]

Abstract The bandwidth of a Δ Σ modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time Δ Σ modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time Δ Σ modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.

This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta-sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process. In view of area efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g'm3/gm1 - 1) x A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master-slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits-at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm2, and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.