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At present, differential power analysis (DPA) is one of the most important threats to the security of block ciphers in chips.When the collected power trace is insufficient, DPA is vulnerable to ghost peak caused by the difference mean value generated by the wrong key.Based on DPA, a incidence matrix differential power analysis (IMDPA) was proposed which could effectively resist ghost peak.The prediction difference mean matrix was constructed to avoid the influence of the non leaking interval on the key guessing of the leaking interval by using the weak correlation of the guessing key in the non leaking interval.The proposed IMDPA was tested in different leak intervals of AES-128 algorithm.The results show that compared with traditional DPA, IMDPA requires less (up to 85%) power trace to guess the correct key.At the same time, the key guessing efficiency of AES-128 under the implementation of protective measures by IMDPA still has obvious advantages.In order to further verify the universality of IMDPA in block ciphers, experimental verification is conducted on SM4 algorithm.Compared with traditional DPA, IMDPA requires less (up to 87.5%) power traces to guess the correct key.

Trace alignment can improve the subsequent side-channel analysis against the trace. Most current trace alignment schemes are, however, typically operated under a high signal-to-noise ratio (SNR), which demands them to be noise reduced before alignment when practical applications in the complex environment. In this paper, we propose a novel strategy for applying adaptive filtering in trace alignment preprocessing under low SNR conditions. The approach selects a trace as the reference signal of the adaptive filter, and the impulse response describing the trace offset is calculated iteratively for each trace. Different from conventional trace alignment methods, the error between the two traces in iteration determines how to eliminate the offset between trace, which eliminate most of the noise effects in the iteration process. In parallel, the filter after iterating will also function as a low-pass filter in the alignment process. Experimental studies based on three side-channel datasets demonstrate the efficacy of the proposed approach. Compared with other alignment methods, with the reasonable computational resource cost and complexity, the average number of traces required has reduced the average number of traces required by 75%, the average confidence has improved by 60%, and the success rate has increased by 72%. Our approach provides great potential for applications in trace alignment preprocessing of side-channel analysis. [ABSTRACT FROM AUTHOR]

Lightweight cryptography is an emerging field where designers are testing the limits of symmetric cryptography. We investigate the resistance against sidechannel attacks of a new class of lighter blockciphers, which use a classic substitution–permutation network with slow diffusion and many rounds. Among these ciphers, we focus on SKINNY, a primitive used up to the final round ofNIST’s recent lightweight standardisation effort. We show that the lack of diffusion in the key scheduler allows an attacker to combine leakage from the first and the last rounds, effectively pincering its target. Furthermore, the slow diffusion used by its partial key-absorption and linear layers enable, on both sides, to target S-Boxes from several rounds deep. As some of these S-boxes leak on the same part of the key, full key recovery exploiting all leakage requires a clever combining strategy. We introduce the use of cluster graph inference (an established tool from probabilistic graphical model theory) to enhance both unprofiled or profiled differential power analysis, enabling us to handle the increase of S-Boxes with their intertwined leakage. We evaluate the strength of our attack both in the Hamming weight model and against two implementations running on an STM32F303 ARM Cortex-M4 hosted on a ChipWhisperer target board, showing that our attack reduces the number of traces required to attack SKINNY by a factor of around 2.75.

The Internet of Things is a resource-constrained device that demands lightweight cryptographic solutions to achieve high performance and optimal security. In lightweight ciphers Substitution Box (S-box) plays an important role as it enables confusion property. However, it is one of the costlier operations. The design and construction of such S-boxes for Internet of Things (IoT) devices are crucial..Hence, we propose a 4-bit, highly Nonlinear, Bijective, Balanced S-box called Feather S-box to enable confusion in lightweight ciphers. The hardware performance of Feather S-Box is analysed in terms of Area and Critical Path-Delay cost. While examining the Area Delay-Product and Power-Delay Product, it shows 23% and 19% lower than PRESENT cipher and 12% lesser than GIFT and KATAN ciphers. The security analysis of the proposed S-Box is also done in terms of Nonlinearity, Bijective, Balanced, Global Avalanche characteristics, resistance to Algebraic attack, Side-channel attacks, Differential and Linear Cryptanalysis. The Feather S-box also exhibts good cryptographic properties such as Nonlinearity and immunity against Algebraic attacks. Moreover, it offers good resistance against Side-channel attack, Differential and Linear Cryptanalysis. We also observed that the Feather S-box has the highest immunity against Differential and Linear Cryptanalysis except for the SKINNY cipher. [ABSTRACT FROM AUTHOR]

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The notion of the confusion coefficient is a property that attempts to characterize confusion property of cryptographic algorithms against differential power analysis. In this article, we establish a relationship between the confusion coefficient and the autocorrelation function for any Boolean function and give a tight upper bound and a tight lower bound on the confusion coefficient for any (balanced) Boolean function. We also deduce some deep relationships between the sum-of-squares of the confusion coefficient and other cryptographic indicators (the sum-of-squares indicator, hamming weight, algebraic immunity and correlation immunity), respectively. Moreover, we obtain some trade-offs among the sum-of-squares of the confusion coefficient, the signal-to-noise ratio and the redefined transparency order for a Boolean function.

Side‐channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1‐of‐4 codes to resist differential power analysis attacks, which is the most investigated category of side‐channel attacks. The four code words of the 1‐of‐4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set‐0 and set‐1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES‐128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t‐test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively.

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

As everyone is aware that all the recently introduced networks systems are in need of significant security measures and by having a separate hardware architecture for the cryptographic function, necessary high level data protection can be achieved. Advanced Encryption Standard (AES) is one of the best cryptographic algorithms to provide such high level security but it can be exploited because of its quantifiable power consumption. Recent advancement in technology uses this power consumption value to find the secret key value with the mathematical steps used in the algorithm during encryption process. This method of obtaining secret key with the power consumption is known as Side-Channel Attacks. Even though several dedicated hardware is available for analyzing the AES weakness related to SCA, but its implantation is quite difficult because of high cost or the synchronization problem between the AES implementing architecture and the power sampling rate of Analog to Digital Convertors or bandwidth of the oscilloscopes. In this research work, we proposed a technique for the purpose of Correlation and Differential Power Analysis for the FPGA implementations of AES cryptographic hardware architecture. Results from this research are used to create a detailed model of the AES power consumption with the help of advanced mathematical and statistical measures. With this research work, it is possible to provide the scenario of SCA attacks in real time without having any additional architecture for the power sampling analysis and clock frequency synchronization. Therefore the result of this research work can be used as a preventive measure of SCA attacks in the design process itself, thereby reducing the burdening of designers. [ABSTRACT FROM AUTHOR]

Differential power analysis (DPA) is disturbed by ghost peaks. There is a phenomenon that the mean absolute difference (MAD) value of the wrong key is higher than the correct key. We propose a compressed key guessing space (CKGS) scheme to solve this problem and analyze the AES algorithm. The DPA based on this scheme is named CKGS-DPA. Unlike traditional DPA, the CKGS-DPA uses two power leakage points for a combined attack. The first power leakage point is used to determine the key candidate interval, and the second is used for the final attack. First, we study the law of MAD values distribution when the attack point is AddRoundKey and explain why this point is not suitable for DPA. According to this law, we modify the selection function to change the distribution of MAD values. Then a keyrelated value screening algorithm is proposed to obtain key information. Finally, we construct two key candidate intervals of size 16 and reduce the key guessing space of the SubBytes attack from 256 to 32. Simulation experimental results show that CKGS-DPA reduces the power traces demand by 25% compared with DPA. Experiments performed on the ASCAD dataset show that CKGS-DPA reduces the power traces demand by at least 41% compared with DPA. [ABSTRACT FROM AUTHOR]

The notion of the confusion coefficient is a property that attempts to characterize confusion property of cryptographic algorithms against differential power analysis. In this article, we establish a relationship between the confusion coefficient and the autocorrelation function for any Boolean function and give a tight upper bound and a tight lower bound on the confusion coefficient for any (balanced) Boolean function. We also deduce some deep relationships between the sum-of-squares of the confusion coefficient and other cryptographic indicators (the sum-of-squares indicator, hamming weight, algebraic immunity and correlation immunity), respectively. Moreover, we obtain some trade-offs among the sum-of-squares of the confusion coefficient, the signal-to-noise ratio and the redefined transparency order for a Boolean function. [ABSTRACT FROM AUTHOR]

This paper presents the employment of a DPA attack on the NIST (National Institute of Standards and Technology) standardized AES (advance encryption standard) protocol for key retrieval and prevention. Towards key retrieval, we applied the DPA attack on AES to obtain a 128-bit secret key by measuring the power traces of the computations involved in the algorithm. In resistance to the DPA attack, we proposed a countermeasure, or a new modified masking scheme, comprising (i) Boolean and (ii) multiplicative masking, for linear and non-linear operations of AES, respectively. Furthermore, we improved the complexity involved in Boolean masking by introducing Rebecca's approximation. Moreover, we provide a novel solution to tackle the zero mask problem in multiplicative masking. To evaluate the power traces, we propose our custom correlation technique, which results in a decrease in the calculation time. The synthesis results for original implementation (without countermeasure) and inclusion of countermeasure are given on a Zynq 7020 FPGA (Artix-7 device). It takes 424 FPGA slices when implemented without considering the countermeasure, whereas 714 slices are required to implement AES with the inclusion of the proposed countermeasure. Consequently, the implementation results provide the acceptability of this work for area-constrained applications that require prevention against DPA attacks. [ABSTRACT FROM AUTHOR]

Side‐channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1‐of‐4 codes to resist differential power analysis attacks, which is the most investigated category of side‐channel attacks. The four code words of the 1‐of‐4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set‐0 and set‐1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES‐128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t‐test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively. [ABSTRACT FROM AUTHOR]

In the past few decades, DPA-based side-channel attack strategies, such as DPA and CPA, have shown strong ability to analyze the security of the cryptographic implementations. However, the unpredictability of the leakage model and the correspondence between leakage behavior of the target device and the hypothetical leakage value make it less-effective without prior knowledge. Therefore, in this paper, we present a novel generic side-channel analysis method called Gini-impurity Index Analysis (GIA), utilizing Gini-impurity Index as the distinguisher, which can perform well even without any leakage model and is not sensitive to the existing methods’ restrictions about the leakage behavior. Firstly, we introduce the basic idea of GIA. According to the proposed GIA attack strategy, the Gini-impurity index for each key hypothesis should be calculated, determined by the clustered power consumption and the classified subsets based on the key dependent target function. Secondly, we verify the feasibility and evaluate the efficiency of GIA with different target functions by the practical experimental results against AES-128 implemented on an AT89S52 microcontroller. We present one possible multivariate extension of GIA and find the advantage of GIA on leakage information utilization. Thirdly, we present the results of comparisons. On the one hand, we compare GIA with three widely-used distinguishers under simulated traces in various leakage scenarios and practical traces with Hamming-weight-related leakage. Results confirm that GIA can always perform well with different leakage models in most situations. On the other hand, we analyze the relationship between GIA and Mutual Information Analysis (MIA). Theoretical and experimental results confirm that these two methods can obtain similar attack results. However, the guessing entropy of GIA is lower than MIA by up to 21%, and the averaged computational time overhead of GIA is lower than MIA by up to 13.3%, indicating that GIA is more efficient than MIA. Compared to traditional MIA, GIA is easier to operate and more flexible with noise. Therefore, GIA is an efficient and useful alternative to these existed strategies. [ABSTRACT FROM AUTHOR]

During the past two decades there has been a great deal of research published on masked hardware implementations of AES and other cryptographic primitives. Unfortunately, many hardware masking techniques can lead to increased latency compared to unprotected circuits for algorithms such as AES, due to the high-degree of nonlinear functions in their designs. In this paper, we present a hardware masking technique which does not increase the latency for such algorithms. It is based on the LUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) technique presented at CHES 2014. First, we show 1-glitch extended strong noninterference of a nonlinear LMDPL gadget under the 1-glitch extended probing model. We then use this knowledge to design an AES implementation which computes a full AES-128 operation in 10 cycles and a full AES-256 operation in 14 cycles. We perform practical side-channel analysis of our implementation using the Test Vector Leakage Assessment (TVLA) methodology and analyze univariate as well as bivariate t-statistics to demonstrate its DPA resistance level.

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS‐based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p–i–n forward current with an increase in negative drain‐to‐source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p–i–n forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S‐box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S‐box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET‐based circuits and systems. [ABSTRACT FROM AUTHOR]

Differential Power Analysis (DPA) attacks are known as viable and practical techniques to break the security of cryptographic algorithms. In this type of attack, an adversary extracts the encryption key based on the correlation of consumed power of the hardware running encryption algorithms to the processed data. To address DPA attacks in the hardware layer, various techniques have been proposed thus far. However, current techniques generally impose high performance overhead. Especially, the power overhead is a serious issue which may limit the applicability of current techniques in power-constrained applications. In this paper, combinational counters are explored as a way to address the DPA attacks. By randomizing the consumed power in each clock cycle of the circuit operation, these counters can enhance the resistance of the cryptographic cores against DPA attacks with low power overhead as well as zero timing overhead. Experimental results for an AES S-Box module in 45 nm technology reveal that the proposed technique is capable of achieving higher level of security in comparison to two other approaches while preserving the power and performance overhead at a same or lower level. [ABSTRACT FROM AUTHOR]

This paper presents the employment of a DPA attack on the NIST (National Institute of Standards and Technology) standardized AES (advance encryption standard) protocol for key retrieval and prevention. Towards key retrieval, we applied the DPA attack on AES to obtain a 128-bit secret key by measuring the power traces of the computations involved in the algorithm. In resistance to the DPA attack, we proposed a countermeasure, or a new modified masking scheme, comprising (i) Boolean and (ii) multiplicative masking, for linear and non-linear operations of AES, respectively. Furthermore, we improved the complexity involved in Boolean masking by introducing Rebecca’s approximation. Moreover, we provide a novel solution to tackle the zero mask problem in multiplicative masking. To evaluate the power traces, we propose our custom correlation technique, which results in a decrease in the calculation time. The synthesis results for original implementation (without countermeasure) and inclusion of countermeasure are given on a Zynq 7020 FPGA (Artix-7 device). It takes 424 FPGA slices when implemented without considering the countermeasure, whereas 714 slices are required to implement AES with the inclusion of the proposed countermeasure. Consequently, the implementation results provide the acceptability of this work for area-constrained applications that require prevention against DPA attacks.