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International audience; The WADAPT (Wireless Allowing Data And Power Transmission) consortium has been formed to identify the specific needs of different projects that might benefit from wireless communication technologies with the objective of providing a common platform for research and development in order to optimize effectiveness and cost [1]. Wireless technologies have developed extremely fast over the last decade and are now mature for being considered as a promising alternative to cables and optical links that would revolutionize the detector design. Although wireless readout has the qualities and properties to be used in many collider detectors, this article focuses on the transmission of large amount of data from vertex detectors at high rate, low power budget and in potential high radiation environment. For vertex detectors, the 60 GHz band has proven to be adequate and commercial products are already available, providing 6 Gbps data links. This technology allows efficient partitioning of detectors in topological regions of interest, with the possibility of adding intelligence on the detector to perform four-dimensional reconstruction of the tracks and vertices online, in order to attach the tracks to their vertex with great efficiency even in difficult experimental conditions, and conveniently substitutes a mass of materials (cables and connectors). Early transceiver module products have been successfully tested for signal confinement, crosstalk, electromagnetic immunity and resistance to radiation. In the long run, emerging 140 GHz bands could also be used for higher data rates (> 100 Gbps) at future high energy and luminosity hadron colliders.

To complement and ensure redundancy in the endcap muon system of the Compact Muon Solenoid (CMS) detector and to extend the Resistive Plate Chamber (RPC) system coverage, improved RPCs (iRPCs) with either orthogonal layer strips with one-end electronics or single layer strips with two-end electronics providing more precise time measurement will be installed in the very forward pseudorapidity region of $$|\eta

International audience; The WADAPT consortium (Wireless Allowing Data and Power Transfer) was created to study wireless (multi-gigabit) data transfer for high-energy physics applications (LoI, CERN-LHCC-2017-002; LHCC-I-028.-2017). Emerging millimetre wave technologies allow fast signal transfer and efficient partitioning of detectors in topological regions of interest. Large bandwidths are available at those frequencies, allowing very high data rates at short range and conveniently substituting a mass of materials (cables and connectors). The Wadapt initiative aims at building proof of concept for use in future HEP experiments. For vertex detectors at HL-LHC, the bandwidth of 60 GHz is adequate and commercial products are already available, providing 6 Gbps data links. Products have been tested for signal confinement, crosstalk, electromagnetic immunity and resistance to radiation. An HEP dedicated 60 GHz Integrated Chip is being built in Heidelberg, using 130 nm SiGe BICMOS technology. It should assess the feasibility and performance of the wireless link and establish solid foundation for designing the final reading system. At longer terms, 140 GHz bands could also be used for higher data rates (> 100 Gbps) for future FCC applications. Wireless reading could widespread to many detectors, with the possibility of adding intelligence on the detector to perform four-dimensional reconstruction of the traces and vertexes online, in order to attach the traces to their vertex with great efficiency even in difficult experimental conditions. The WADAPT project includes also a long-term step aimed at transmitting energy wirelessly. This would create a new paradigm for the transmission of data and power in particle physics detectors.

International audience; The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to the ATLAS detector at the Conseil Europeen Pour La Recherche Nucleaire large hadron collider. The system performs pattern matching (PM) using the detector hits of particles in the ATLAS silicon tracker. The AM system is the main processing element of FTK and is mainly based on the use of application-specified integrated circuits (ASICs) (AM chips) designed to execute PM with a high degree of parallelism. It finds track candidates at low resolution which become seeds for a full resolution track fitting. The AM system implementation is based on a collection of large 9U Versa Module Europa (VME) boards, named “serial link processors” (AMBSLPs). On these boards, a huge traffic of data is implemented on a network of 900 2-Gb/s serial links. The complete AM-based processor consumes much less power (~50 kW) than its CPU equivalent and its size is much smaller. The AMBSLP has a power consumption of ~250 W and there will be 16 of them in a crate. This results in unusually large power consumption for a VME crate and the need for complex custom infrastructure in order to have sufficient cooling. This paper reports on the design and testing of the infrastructures needed to run and cool the system which will include 16 AMBSLPs in the same crate, the integration of the AMBSLP inside a first FTK slice, the performance of the produced prototypes (both hardware and firmware), as well as their tests in the global FTK integration. This is an important milestone to be satisfied before the FTK production.

Journal of astronomical telescopes, instruments, and systems 5(1), 1 - (2019). doi:10.1117/1.JATIS.5.1.014001, Our contribution presents a high bandwidth platform that implements traffic aggregation and switching capabilities for the Cherenkov telescope array (CTA) cameras. Our proposed system integrates two different data flows: a unidirectional one from the cameras to an external server and a second one, fully configurable dedicated to configuration and control traffic for the camera management. The former requires high bandwidth mechanisms to be able to aggregate several 1 gigabit Ethernet links into one high speed 10 gigabit Ethernet port. The latter is responsible for providing routing components to allow a control and management path for all the elements of the cameras. Hence, a simple, efficient, and flexible routing mechanism has been implemented avoiding complex circuitry that impacts in the system performance. As a consequence, an asymmetric network topology allows high bandwidth communication and, at the same time, a flexible and cost-effective implementation. In our contribution, we analyze the camera requirements and present the proposed architecture. Moreover, we have designed several evaluation tests to demonstrate that our solution fulfills the CTA project needs. Finally, we illustrate the general possibilities of the proposed solution for other data acquisition applications and the most promising futures lines of research are discussed., Published by SPIE, [Bellingham, Wash.]

This paper presents the experimental results of $17~MeV$ proton irradiation on a $60~GHz$ low power, half-duplex transceiver (TRX) chip implemented in $65~nm$ CMOS technology. It supports short range point-to-point data rate up to $6~Gbps$ by employing on-off keying (OOK). To investigate the irradiation hardness for high energy physics applications, two TRX chips were irradiated with total ionizing doses (TID) of $74~kGy$ and $42~kGy$ and fluence of $1.4~\times$10$^{14}~ N_{eq}/cm^2$ and $0.8~\times$10$^{14}~N_{eq}/cm^2$ for RX and TX modes, respectively. The chips were characterized by pre- and post-irradiation analogue voltage measurements on different circuit blocks as well as through the analysis of wireless transmission parameters like bit error rate (BER), eye diagram, jitter etc. Post-irradiation measurements have shown certain reduction in performance but both TRX chips have been found operational through over the air measurements at $5~Gbps$. Moreover, very small shift in the carrier frequency was observed after the irradiation., Accepted on 25th March 2019, 6 pages

International audience; The readout system for the upcoming Run3 upgrade of the LHCb experiment at CERN is basedaround a common readout board called PCIe40. By reconfiguring the onboard FPGA with dedicated firmware, this common board can be used to serve very different roles within the upgradedLHCb experiment. A continuous integration pipeline was implemented in order to automaticallycross-validate the tight interaction between the different FPGA firmwares and the associated DAQand control software, all being actively developed in parallel. We present challenges and solutionsfor applying this kind of practices, traditionally limited mainly to the field of software engineering,also to hardware-in-the-loop validation of FPGA firmware and SCADA-based control systems.

This paper presents development and characterization of a 3.2 Gb/s serial link transmitter for CMOS image sensors. The transmitter incorporates Reed-Solomon code to achieve low error rate in the harsh environment of subatomic physics experiments. Pre-emphasis is implemented in the transmitter, allowing data transmission over low-mass cables. It is fabricated in a 0.18 $\mu m$ CMOS image process as a standalone chip to characterize its performance, with the core area of 1.8 $mm^2$. A frame data rate of $3\cdot10^{-12}$ with a confidence level of 94.5$\%$ was measured through an FPGA based receiver. The measured nominal power consumption is 135 mW. The transmitter functions normally after irradiated with 4.5 Mrad TID.

International audience; The LHCb experiment at CERN is undergoing a significant upgrade in anticipation of the increased luminosity that will be delivered by the LHC during Run 3 (starting in 2021). In order to allow efficient event selection in the new operating regime, the upgraded LHCb experiment will have to operate in continuous readout mode and deliver all 40 MHz of particle collisions directly to the software trigger. In addition to a completely new readout system, the front-end electronics for most sub-detectors are also to be redesigned in order to meet the necessary performance. Most front-end communication is based on a common ~5 Gb/s radiation-hard protocol developed at CERN, called GBT. MiniDAQ1 is a complete data-acquisition platform developed by the LHCb collaboration for reduced-scale tests of the new front-end electronics. The hardware includes 36 bidirectional optical links and a powerful FPGA in a small AMC form-factor. The FPGA implements data acquisition and synchronization, slow control and fast commands on all available GBT links, using a very flexible architecture allowing front-end designers to experiment with various configurations. The FPGA also implements a bidirectional 10G Ethernet network stack, in order to deliver the data produced by the front-ends to a computer network for final storage and analysis. An integrated single-board-computer runs the new control system that is also being developed for the upgrade, this allows MiniDAQ1 users to interactively configure and monitor the status of the entire readout chain, from the front-end up to the final output.

In 2015/16, the photomultiplier cameras of the H.E.S.S. Cherenkov telescopes CT1-4 have undergone a major upgrade. The entire electronics has been replaced, using NECTAr chips for the front-end readout. A new ventilation system has been installed and several auxiliary components have been replaced. Besides this, the internal control and readout software was rewritten from scratch in a modern and modular way. Ethernet technology was used wherever possible to ensure both flexibility, stability and high bandwidth. An overview of the installed components will be given. In 2015/16, the photomultiplier cameras of the H.E.S.S. Cherenkov telescopes CT1-4 have undergone a major upgrade. The entire electronics has been replaced, using NECTAr chips for the front-end readout. A new ventilation system has been installed and several auxiliary components have been replaced. Besides this, the internal control and readout software was rewritten from scratch in a modern and modular way. Ethernet technology was used wherever possible to ensure both flexibility, stability and high bandwidth. An overview of the installed components will be given.

The data acquisition system (DAQ) of the future Cherenkov Telescope Array (CTA) must be ef- ficient, modular and robust to be able to cope with the very large data rate of up to 550 Gbps coming from many telescopes with different characteristics. The use of modern middleware, namely ZeroMQ and Protocol Buffers, can help to achieve these goals while keeping the development effort to a reasonable level. Protocol Buffers are used as an on-line data for- mat, while ZeroMQ is employed to communicate between processes. The DAQ will be controlled and monitored by the Alma Common Software (ACS). Protocol Buffers from Google are a way to define high-level data structures through an in- terface description language (IDL) and a meta-compiler. ZeroMQ is a middleware that augments the capabilities of TCP/IP sockets. It does not implement very high-level features like those found in CORBA for example, but makes use of sockets easier, more robust and almost as effective as raw TCP. The use of these two middlewares enabled us to rapidly develop a robust prototype of the DAQ including data persistence to compressed FITS files., In Proceedings of the 34th International Cosmic Ray Conference (ICRC2015), The Hague, The Netherlands. All CTA contributions at arXiv:1508.05894