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This paper demonstrates the first silicon-verified FBMC encoder and decoder designed to emulate beyond $224Gb/s$ wireline communication. It also compares the performance of FBMC to PAM and DMT in three steps. First, the digital power and area consumption are compared using measured results from the manufactured test chip. Second, the data rate is determined using lab-measured results. And third, the performance when subject to notched channels is analyzed using simulation results. Finally, we present a method to emulate wireline links while reducing the emulator complexity and simulation time by one to two orders of magnitude over conventional over-sampled techniques. Our analysis indicates that given a smooth channel and an SNR which enables an average spectral efficiency of $4bits/sec/Hz$ at a bit-error rate of 10-3, both DMT and FBMC perform similarly to a conventional PAM-4 link. However, when noise is reduced and a spectral notch is applied, thereby achieving an average spectral efficiency of $4.6bits/sec/Hz$ , DMT and FBMC can outperform PAM by 2.1 and 2.3 times, respectively. In addition, we estimate FBMC’s encoder and decoder power consumption at $1.53pJ/b$ and $1.98pJ/b$ , respectively, and area requirement at $0.07mm^{2}$ and $0.17mm^{2}$ , respectively, which is similar to DMT. These values are competitive with similar $22nm$ PAM transceivers, suggesting that DMT and FBMC are viable alternatives to PAM for next-generation high-speed wireline applications.

The applications and services envisioned for the sixth Generation (6G) Internet of Things (IoT) communication systems will place different requirements on the system design. The current 5G waveform, Orthogonal Frequency Division Multiplexing (OFDM), suffers from a list of drawbacks that questions its suitability and ability to fulfill these prerequisites. Filtered multi-carrier waveforms provide viable alternatives for future mobile networks. Based on the best recent advances including contributions by the authors, this work provides a comprehensive assessment of the current status and future challenges related to the design of a next-generation Filter Bank Multi-Carrier/Offset Quadrature Amplitude Modulation (FBMC/OQAM) transceiver. We start by showing how the next-generation FBMC/OQAM waveform can overcome the drawbacks of OFDM. Furthermore, we highlight the advantages and possibilities of extending the next-generation FBMC/OQAM waveform for massive Multiple-Input-Multiple-Output (mMIMO) in well-identified 6G-IoT scenarios. Results show that the next-generation FBMC/OQAM receivers associated with short prototype filters can unleash appealing properties for 6G-IoT applications. Considered a cornerstone for grant-free spectrum and massive access, asynchronous communications are shown to be achievable. Furthermore, a largely improved robustness is observed compared to OFDM under different channel impairments such as carrier frequency offsets, timing offsets, and multipath channels. Compared to the original FBMC/OQAM associated with long filters, this next-generation transceiver achieves a reduction in complexity down to a comparable level to OFDM. Finally, open research opportunities and challenges for the next-generation FBMC/OQAM waveform are discussed.

This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a $35dB$ channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.

Future communication systems are foreseen to support several services with different requirements. Waveform designs based on filter-bank multi-carrier with offset quadrature amplitude modulation (FBMC/OQAM) can offer interesting advantages in this context, such as low out-of-band power leakage and high spectral efficiency due to the lack of guard intervals. However, downsides of FBMC/OQAM with respect to a typical orthogonal frequency-division multiplexing (OFDM) solution include higher latency, higher complexity and difficulties in adapting some existing OFDM techniques such as MIMO Alamouti. To address these issues, novel FBMC receivers suitable for short prototype filters are proposed. Based on the Overlap-Save algorithm, the proposed receivers improve error-rate performance on multipath channels and support asynchronous communication. We show that complexity can be further reduced by efficiently processing blocks of FBMC symbols jointly, and that user mobility support can be traded off for additional complexity reductions in a flexible way through polynomial decomposition of the equalizer stage. Finally, we show that a block-Alamouti scheme can be applied, and we propose a MIMO equalizer with improved error-rate performance on time-varying channels, compared to the typical FBMC block-Alamouti equalizer. [ABSTRACT FROM AUTHOR]

A semi-parallel architecture to implement a filter-bank multi-carrier system for broadband communications is presented. The signal processing schemes for both the transmitter and the receiver have been analyzed in terms of computational complexity, thus determining the corresponding requirements and constraints to be considered in the definition of architecture parameters, such as internal data rates or operation frequencies. Furthermore, the proposed design allows to achieve a real-time implementation of the whole transmultiplexer for broadband multi-carrier communications in a Field-Programmable Gate Array (FPGA) device. This implementation has been carried out by means of a System-on-Chip (SoC)-based architecture, where the specific hardware for the transmultiplexer has been integrated as an advanced peripheral. For experimental tests, all the architecture description has been particularized for a transmultiplexer configuration recommended by the IEEE 1901 working group for broadband power line communications. Nevertheless, the designed architecture can be easily adapted to other options by suitably defining some generic parameters in its HDL (Hardware Description Language) specification. [ABSTRACT FROM AUTHOR]