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The paper presents efficiency and power loss analysis in a high-frequency, seven-level diode-clamped inverter (7LDCB). The inverter is composed of four-level (4L) diode-clamped branches based on MOSFET transistors and Si Schottky diodes. The range of DC-link voltages enables the operation of the inverter in connection with a single-phase power grid. The tested inverter can be controlled using various modulation concepts that affect its parameters, but also energy losses. Carrier-based modulation, which may be useful in a few applications, is compared to selective modulation based on the state machine (SM-based) algorithm. The article demonstrates the efficiency level of the inverter as well as the influence of the modulation method and switching frequency on the efficiency and loss distribution in semiconductor devices. The article also shows the hardware implementation of a complex modulation algorithm based on selective switching states used to maintain voltage balance on three DC-link capacitors. Redundant switching states allow the generation of the same voltage but with the use of a selected DC-link capacitor. This makes it possible to balance the DC-link voltage with the load current. The article presents experimental results, which show the advantage of using the modulation method with selective switching states. First, it allows for equalizing the loading of DC-link capacitors. The second advantage is a more uniform distribution of losses in semiconductor components. [ABSTRACT FROM AUTHOR]

This paper presents a novel concept of the DC-AC system with the input voltage boost ability, seven-level output voltage modulation, and the input AC current reduction at the double frequency of the output voltage. The system integrates the NPC full-bridge inverter which is composed of four-level legs and an active input voltage balancer (AIVB). The DC-link is composed of three capacitors connected in a series. The source of the energy is connected directly to the middle capacitor while the upper and lower capacitors of the DC-link are charged by the AIVB. The operation of the AIVB leads to balancing of the DC-link voltage and a three-fold boosting of the input voltage. The AIVB utilizes a novel switched-capacitor (SC) topology and can be designed as a low-volume quasi-magneticless converter with a simple open-loop control. One of the proposed methods of the control of the AIVB allows for a double frequency reduction in the input current. The application of the AIVB allows for the use of a seven-level NPC full-bridge (FB) inverter with a simple classic carrier-based PWM which is not applicable in the typical DC-link configurations. This paper presents the converter's concept, its operation, control methods, and the results of simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper presents a direct torque control (DTC) with 6 sectors of an induction motor (IM) fed by four-level inverter using artificial neural networks (ANNs). The DTC of IM is a simple yet efficient control strategy in the field of variable speed AC motor. We proposed in this article three strategies of four-level DTC with 6 sectors. This study also presents ANN based DTC for a four-level. The validity of the proposed control scheme is verified by computer simulation using Matlab. The stator flux, torque, and THD value of stator current are determined and compared with the proposed strategies. [ABSTRACT FROM AUTHOR]

Four-level nested neutral-point clamped (NNPC) inverters experience severe voltage balancing problems under low output-frequency conditions when the conventional four-level space vector modulation (4L-SVM) technique is applied, which limits their wider application. In order to get a complete control of the flying-capacitor voltages, and to alleviate the calculation burden of conventional 4L-SVM, a simplified but effective 4L-SVM technique along with the voltage balance control (VBC) function is proposed in this paper. For low modulation indexes, zero and small vectors are selectively utilized and distributed to force the average charging and discharging time of flying capacitors to be equal to each other during every switching period, so that voltage ripples are greatly reduced to be within an acceptable level under low output-frequency conditions. For high modulation indexes, the simplification of conventional 4L-SVM for NNPC inverters into two-level SVM is proposed to reduce the computation complexity. Principles of the proposed 4L-SVM and VBC are elaborated in detail. The steady-state, transient-state, and VBC performances are investigated and compared with the case where the conventional 4L-SVM is applied. Simulation results of a 5 MVA inverter system and experimental results of a scaled-down 5 kVA inverter system are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

A new inverter topology for single-phase photovoltaic (PV) systems is proposed in this study. The proposed inverter offers a four-level voltage in its output terminals. This feature results in easier filtering in comparison with other conventional two-level or three-level inverters. In addition, the proposed four-level inverter (PFLI) has a transformer-less topology, which decreases the size, weight, and cost of the entire system and increases the overall efficiency of the system. Although the inverter is transformer-less, it produces a negligible leakage ground current (LGC), which makes this inverter suitable for PV grid-connected applications. The performance of the proposed inverter is compared with that of a four-level neutral point clamped inverter (FLNPCI). Theoretical analysis and computer simulations verify that the PFLI topology is superior to FLNPCI in terms of efficiency and suitability for use in PV transformer-less systems. [ABSTRACT FROM AUTHOR]

A four-level inverter drive could be obtained by feeding an open-end winding induction motor by two two-level inverters from either side with unequal dc-link voltages, which are in the ratio of 2:1. This inverter modulation scheme is capable of producing 64 space-vector combinations. Some of the space vector combinations could result in the overcharging of the dc-link capacitor corresponding to the inverter operating with the lower voltage. In this paper, a new power circuit topology is proposed, in which, a rectifier-inverter combination is nested within a conventional two-level inverter configuration. The output of the conventional two-level inverter feeds one end of the open-end winding induction motor, while the output of the nested rectifier-inverter combination feeds the other end. The total dc-link voltage needed in the proposed topology is only 77% of the one needed in the conventional multilevel inverters. Also, the problem of zero-sequence current, commonly encountered in open-end winding induction motor drives, is avoided by resorting to a decoupled space vector modulation PWM scheme, which eliminates the zero-sequence voltage of the dual-inverter system by forcing the sampled average of the zero sequence voltage of individual inverters to zero. [ABSTRACT FROM PUBLISHER]

In this paper, two space-vector-based pulsewidth modulation (PWM) (SVPWM) strategies named equal- and proportional-duty SVPWMs are described, which are used to synthesize a four-level waveform from an open-end winding configuration of an induction motor. Two isolated dc-link voltages, which are in the ratio of 2 : 1, are employed to achieve this objective. Both of these PWM strategies achieve the avoidance of overcharging of the dc-link capacitor of an inverter operating with lower dc-link voltage by its counterpart with higher dc-link voltage. Implementation of these PWM strategies requires only the instantaneous three-phase reference voltages, eliminating the need of sector identification or lookup tables. The numbers of samples per cycle for individual inverters are selected in such a way that the quarter-wave, half-wave, and three-phase symmetries are achieved for the dual-inverter drive despite unequal dc-link voltages for the constituent inverters. It is also shown that one of the two PWM techniques, called the proportional-duty SVPWM, results in a better spectral performance and lower switching power loss in the overall dual-inverter system compared to the equal-duty SVPWM. [ABSTRACT FROM PUBLISHER]

Multilevel diode-clamped converters with more than three levels cannot maintain voltage balance in the dc-link capacitors for some operating conditions due to the existence of dc currents in the middle points. Since capacitors are either completely charged or discharged for those conditions, this circumstance severely limits practical application of these converters. The limit explored in this paper is that the four-level converter cannot achieve voltage balance. Proper redundant vectors are selected in the space-vector diagram so that a quadratic parameter related to the currents in the middle points is minimized. [ABSTRACT FROM AUTHOR]