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Dining with people improves our lives and brings a lot of benefits. Nonetheless, many people are compelled to eat by themselves due to the current social situation. We believe that robots can be good meal partners. In this paper, we describe the developed meal partner robots called Mamoru'21 and Mamoru'22. The design of these robots is inherited from a robot for watching over elderly people. Based on previous research that robot's eating behavior expression can improve the mealtime experience, they can perform motions that mimic eating and present food images by monitors. In the first experiment, we confirmed the developed robot could improve the co-eating experience compared to a conventional small humanoid robot, and investigated the keywords for preferable hardware design, such as 'smaller than a child.' In the second experiment, we studied the effects of the robot's moving around during mealtime. As a result, no statistically significant negative effects of robot movement during meals were observed in the developed robot's capability. Though this study has some limitations such as shorter experimentation time compared to regular meals, it contributes some insights and knowledge into the behavior and design of meal partner robots. [ABSTRACT FROM AUTHOR]

In order to effectively reduce the failure rate of vibrating screens, a vibration monitoring system design was proposed based on the structure and working principle. The system should be able to monitor the operating state of the vibrating screen in real time, including vibration amplitude, frequency, axial displacement, etc., and be able to detect abnormal conditions in time and give warning prompts. The key hardware of the monitoring system was designed, including acceleration sensor, power module, signal filtering circuit, etc. The sensitivity of the acceleration sensor was measured using comparative method and accurately completed parameter calibration. The eccentric block was used to simulate different deviation of excitation force for system vibration signal test and calibration. The results show that under normal operating conditions, the amplitude of each frequency of the vibrating screen is less than 0.04 g. Under the condition of excitation force deviation, the amplitude of 16 Hz is obviously lower than that of other frequencies, which means that the vibrating screen is currently experiencing lateral oscillation. [ABSTRACT FROM AUTHOR]

To enhance compression efficiency, the AV1 video coding standard has introduced several new intra-prediction modes, such as smooth and finer directional prediction modes. However, this addition increases computational complexity and hinders parallelized hardware implementation. In this paper, a hardware-friendly rough mode decision (RMD) algorithm and its fully pipelined hardware architecture design are proposed to address these challenges. For algorithm optimization, firstly, a novel directional mode pruning algorithm is proposed. Then, the sum of absolute transform differences (SATD) cost accumulated approximation method is adopted during the tree search. Finally, in the reconstruction stage, a reconstruction approximation model based on the DC transform is proposed to solve the low-parallelism problem. For hardware architecture design, the proposed fully pipelined hardware architecture is implemented with 28 pipeline stages. This design can process multiple prediction modes in parallel. Experimental results show that the proposed fast algorithm achieves 46.8% time savings by 1.96% Bjøntegaard delta rate (BD-Rate) increase on average under all-intra (AI) configuration. When synthesized under the 28nm UMC technology, the proposed hardware can operate at a frequency of 316.2 MHz with 1113.14 K gate count. [ABSTRACT FROM AUTHOR]

High-Efficiency Video Coding (HEVC) is a video compression standard designed to improve video compression efficiency compared to its predecessor, Advanced Video Coding (AVC). HEVC provides approximately twice the compression efficiency compared to the AVC. In the HEVC system, the most computational complexity module is the Motion Estimation (ME). ME module helps reduce redundancy by compensating for motion during video compression. However, the computational complexity makes it a bottleneck in the design of high-resolution video encoders. This paper proposes an efficient architecture for the Integer ME (IME) module of the HEVC encoder. The proposed architecture introduces an efficient memory usage scheme to support the Full Search motion search algorithm. The full pipeline architecture includes 4096 Processing Elements (PE) and an adder tree to compute the Sum of Absolute Difference (SAD) for every Prediction Unit (PU) partition. The proposed architecture was designed and implemented on Xilinx Virtex-7 XC7VX550T FPGA. Our design achieved up to 275 FPS and approximately 10 FPS at 4 K video for the Search Regions of [Formula: see text] and [Formula: see text] pixels, respectively.

Information flow analysis can effectively model the security behavior and security properties of hardware design. However, the existing gate level information flow analysis methods cannot deal with large-scale designs due to computing power and verification effectiveness, and the register transfer level (RTL) information flow analysis methods require formal languages to rewrite hardware designs. This paper proposes a RTL hardware design information flow modeling and security verification method. Based on the RTL functional model, this method develops an information flow tracking logical model to model security behavior and security properties of RTL hardware designs from the perspective of information flow. This method can be integrated into EDA flows and uses EDA testing and verification tools to capture security property violations and detect security vulnerabilities based on non-interference security policy. The results on experiments with Trust-Hub hardware Trojan benchmarks show that the proposed method can effectively detect hardware Trojans.

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively. [ABSTRACT FROM AUTHOR]

Copyright of Rolling Stock (1002-7602) is the property of Rolling Stock Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Convolutional neural networks (CNNs) have demonstrated remarkable performance in many areas but require significant computation and storage resources. Quantization is an effective method to reduce CNN complexity and implementation. The main research objective is to develop a scalable quantization algorithm for CNN hardware design and model the performance metrics for the purpose of CNN implementation in resource-constrained devices (RCDs) and optimizing layers in deep neural networks (DNNs). The algorithm novelty is based on blending two quantization techniques to perform full model quantization with optimum accuracy, and without additional neurons. The algorithm is applied to a selected CNN model and implemented on an FPGA. Implementing CNN using broad data is not possible due to capacity issues. With the proposed quantization algorithm, we succeeded in implementing the model on the FPGA using 16-, 12-, and 8-bit quantization. Compared to the 16-bit design, the 8-bit design offers a 44% decrease in resource utilization, and achieves power and energy reductions of 41% and 42%, respectively. Models show that trading off one quantization bit yields savings of approximately 5.4K LUTs, 4% logic utilization, 46.9 mW power, and 147 μ J energy. The models were also used to estimate performance metrics for a sample DNN design. [ABSTRACT FROM AUTHOR]

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AI by AI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AI by AI using a 130 nm technology, marking a groundbreaking achievement as possibly the world's first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs. [ABSTRACT FROM AUTHOR]

Medical image compression is vital for preserving image quality and optimizing storage and transmission in healthcare facilities. FPGA design faces challenges in balancing compression ratios, speed, and power consumption. This study proposes a novel approach using the Selfish Herd Optimization (SHO) algorithm to cluster medical image data based on anatomical features. A hybrid deep convolutional neural network generates optimal predictors for each cluster, extracting features from the image data and generating predictions for each pixel based on its neighbors. The proposed system achieves low power and high-speed FPGA design while ensuring reliability and accuracy. Experimental results on Virtex-7 VC709 and Virtex-5QV130FX FPGAs demonstrate impressive improvements, including a 244.08% increase in frequency, 210.04% increase in speed, 200.90% increase in throughput, 61.37% increase in efficiency, and significant reductions in resource utilization and power consumption. This design promises efficient lossless medical image compression with enhanced performance. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer-Aided Design & Computer Graphics / Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao is the property of Gai Kan Bian Wei Hui and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The paper presents a practical methodology for the prediction of power consumption of a multitask real-time system. The authors briefly recall the structure of the original multitasking time-predictable system. The system has a regular and scalable architecture. It consists of many cores based on pipeline processing with threads' interleaving mechanism. In previous works, the authors have presented a number of issues related to the methodology of designing a time-predictable system and the scheduling of hardware threads with different design goals and constraints. The current article presents an accurate method for measuring the dynamic power dissipated in a system for various scenarios and the system configuration. The proposed approach is based on continuous monitoring of the power consumed by the FPGA, transmitting the measurements to the computer from the measuring device, and online analysis of the obtained results. The authors based their power estimation method on the original task frequency factor (TF). A theoretical analysis was made, and a series of practical experiments were carried out. The results obtained enable accurate estimation of the power requirements for the tasks performed in the real-time system. The presented technique can be useful during the design stage of multitasking real-time systems. [ABSTRACT FROM AUTHOR]

Echolocation is the prime sensing modality for many species of bats, who show the intricate ability to perform a plethora of tasks in complex and unstructured environments. Understanding this exceptional feat of sensorimotor interaction is a key aspect into building more robust and performant man-made sonar sensors. In order to better understand the underlying perception mechanisms it is important to get a good insight into the nature of the reflected signals that the bat perceives. While ensonification experiments are an important way to better understand the nature of these signals, they are as time-consuming to perform as they are informative. In this paper we present SonoTraceLab, an open-source software package for simulating both technical as well as biological sonar systems in complex scenes. Using simulation approaches can drastically increase insights into the nature of biological echolocation systems, while reducing the time- and material complexity of performing them.

This study explores the implementation of lightweight binary classification algorithms on low-cost Field-Programmable Gate Arrays (FPGAs) for medical image analysis. Recognizing the growing demand for efficient and accurate diagnostic tools in healthcare, we focus on applying FPGAs to process small-sized medical images, explicitly targeting the detection of malaria from blood cell images. Our approach involves the hardware designs of k-nearest Neighbors (k-NN), Convolutional Neural Networks (CNN), and Decision Tree classifiers rigorously tested on a publicly available Malaria dataset. The methodology emphasizes the integration of these classifiers on FPGA, detailing the optimization strategies that allow for enhanced processing speed and reduced resource utilization. Comparative analysis reveals that our FPGA-based implementation significantly outperforms MATLAB simulations, achieving processing speeds more than thousands of times faster. Our proposed hardware design also requires fewer Look-up Tables (LUTs) than other classification studies in the literature, showcasing decreases of 73.9% for k-NN, 57% for CNN, and 96.7% for the Decision Tree classifier. Furthermore, results highlight the Decision Tree classifier as the most effective, with an accuracy rate of 99.33%, followed by CNN at 97.67% and k-NN at 95.33%. These findings demonstrate the capability of FPGAs in medical image classification and underscore their potential to revolutionize disease diagnosis processes, particularly in resource-limited environments.

Airborne 3D imaging using ultrasound is a promising sensing modality for robotic applications in harsh environments. Over the last decade, several high-performance systems have been proposed in the literature. Most of these sensors use a reduced aperture microphone array, leading to artifacts in the resulting acoustic images. This paper presents a novel in-air ultrasound sensor that incorporates 1024 microphones, in a 32-by-32 uniform rectangular array, in combination with a distributed embedded hardware design to perform the data acquisition. Using a broadband Minimum Variance Distortionless Response (MVDR) beamformer with Forward-Backward Spatial Smoothing (FB-SS), the sensor is able to create both 2D and 3D ultrasound images of the full-frontal hemisphere with high angular accuracy with up to 70 $\mathrm { \text {dB}}$ main lobe to side lobe ratioin the array response in a single-source scenario. This paper describes both the hardware infrastructure needed to obtain such highly detailed acoustical images, as well as the signal processing chain needed to convert the raw acoustic data into said images. Utilizing this novel high-resolution ultrasound imaging sensor, we wish to investigate the limits of both passive and active airborne ultrasound sensing by utilizing this virtually artifact-free imaging modality.

We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over $GF(2^{233})$ using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation; this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles; it achieves a maximum frequency of 365 MHz and computes one point multiplication in $19.77\mu s$ . The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design’s suitability for applications requiring area and throughput-optimized cryptographic implementations.

Lossless compression of medical images can reduce data size, save storage and transmission costs, and cope with the challenge of increasing resolution demand for medical images. This paper proposes an adaptive pipeline hardware architecture for lossless compression/decompression of medical images based on joint photographic experts group-lossless (JPEG-LS), which can achieve efficient image processing on field programmable gate array (FPGA). In addition, by adding a pipeline pause mechanism, the problem of coding errors caused by parameter updates is solved. On the one hand, the binary search method is used to optimize the calculation process of the Golomb coding parameter k in the pipeline, which reduces the parameter update delay. On the other hand, the construction process of the context causal template is optimized, which effectively improves the throughput. Based on the parallel block compression architecture, a hardware module for alpha red green blue (ARGB) image block compression/decompression with customizable block size is implemented, which improves the image compression/decompression throughput and reduces the compression and decompression delay. This paper implements the hardware architecture on Zynq7000 FPGA and evaluates its performance. Compared with existing schemes, the proposed architecture uses less resources and achieves higher compression ratio and clock frequency.

This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors. [ABSTRACT FROM AUTHOR]

This paper presents a novel S-box generation scheme to enhance the security of the Advanced Encryption Standard（AES） algorithm. After analyzing the existing issues with S-boxes, a new S-box is constructed based on the principles of S-box construction and its cryptographic properties. This is achieved by selecting new irreducible polynomials and affine transformations while adjusting the order of affine transformations and multiplicative inversion operations. The newly generated S-box is compared with the S-box of AES and other improved S-boxes in terms of algebraic terms and strict avalanche criteria distance. The results demonstrate that the new S-box exhibits superior algebraic properties and effectively defends against algebraic attacks. Furthermore, the new S-box is subjected to hardware design and optimization. The DC synthesis results reveal that the optimized implementation of the new S-box in the finite field consumes 12% fewer resources compared to traditional finite field implementations and 41% fewer resources compared to lookup table methods. This paper substantiates the superiority of the new S-box in terms of security over the existing S-boxes. It also applies the new S-box to AES software and hardware designs, with the correctness of the implementation verified through simulation testing. [ABSTRACT FROM AUTHOR]

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively.

This paper reviews hardware-based protection methods for electronic devices, encompassing scientific publications and published patents. This review covers insights from the scientific community and innovative solutions patented in the industry. By combining these two sources, this paper offers a comprehensive and holistic review of electronic device security. Electronic devices are integral to modern life, but their widespread use invites security threats, both digital and physical. This paper reviews hardware-based protection methods against invasive and non-invasive attacks, emphasizing the importance of a dual approach through hardware design. Invasive attacks involve physical tampering, and we explore anti-tampering techniques such as conductive meshes, sensors and physically unclonable functions (PUFs). Non-invasive, side-channel attacks encompass various attack vectors, focusing on electromagnetic analysis. To counter these attacks, we analyze techniques like reducing and masking electromagnetic radiation. This paper bridges the gap between invasive and non-invasive attack mitigation. It underscores the necessity of a multifaceted approach to safeguard electronic devices in an interconnected world, preserving their reliability and functionality. [ABSTRACT FROM AUTHOR]

Among the stereo matching algorithms, the semi-global matching (SGM) is an efficient and high-accuracy method. However, its huge demand for memory access and high computational complexity makes it difficult to achieve a real-time and efficient processing on hardware. Based on the spatial redundancy found in the matching cost, we propose some effective techniques to reduce the requirement of on-chip and off-chip memory, while simultaneously greatly lower the computational complexity. Experimental results present that the proposed SGM algorithm reduces the computational complexity by 71%–74% and has almost the same quality of disparity map compared with the original 8-path SGM. The proposed 3-path fully-pipelined architecture is implemented on the Xilinx VCU-106 with a throughput of 1920 × 1080/54 fps. We also synthesize and layout it with TSMC 40 nm standard library, leading to an area of 8.1 mm 2 with throughput of 1920 × 1080/192 fps. The million disparity estimation per second (MDE/s) of the proposed design reaches up to 50,960, which outperforms conventional ASIC implementations. • We propose two SGM designs using the four-cycle time-sharing structure. • One is 4-path SGM, which has almost the same quality as the original 8-path SGM. • One is 3-path SGM, which completely eliminates the requirement of off-chip memory. • We aimed to lower the hardware complexity and reduce memory access requirements. [ABSTRACT FROM AUTHOR]

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over G F (2 233) . The throughput of the proposed accelerator design is optimized by reducing the total clock cycles using a bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize the hardware resources: (i) a consolidated arithmetic unit where we combine a single modular adder, multiplier, and square block instead of having multiple modular operators, and (ii) an Itoh–Tsujii inversion algorithm by leveraging the existing hardware resources of the multiplier and square units for multiplicative inverse computation. An efficient finite-state-machine (FSM) controller is implemented to facilitate control functionalities. To evaluate and compare the results of the proposed accelerator architecture against state-of-the-art solutions, a figure-of-merit (FoM) metric in terms of throughput/area is defined. The implementation results after post-place-and-route simulation are reported for reconfigurable field-programmable gate array (FPGA) devices. Particular to Virtex-7 FPGA, the accelerator utilizes 3584 slices, needs 7208 clock cycles, operates on a maximum frequency of 350 MHz, computes one ECPM operation in 20.59 μ s, and the calculated value of FoM is 13.54. Consequently, the results and comparisons reveal that our accelerator suits applications that demand throughput and area-optimized ECPM implementations. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In the sensorless control algorithm of permanent magnet synchronous motors (PMSMs), there is a significant research focus on developing a high-performance position observer and a cost-effective, high-performance processor specifically designed for PMSMs. In this paper, we first reviewed the current mainstream position observation algorithms. Subsequently, we proposed a position observation algorithm based on a fixed-point nonlinear flux linkage model that introduces a variable gain model and an observer compensation model. Furthermore, we implemented the improved position observation algorithm in the circuit and designed a System-on-Chip (SOC) suitable for the sensorless control of high-speed permanent magnet synchronous motors using the ARM Cortex-M0 core. The functionality of the proposed SOC was verified on the Field Programmable Gate Array (FPGA) platform. The results demonstrate that the improved algorithm offers an excellent angle observation accuracy and fast convergence speed. The error between the observed angle and the actual angle is less than 0.2 rad. Additionally, the designed SOC balances the high efficiency of hardware implementation with the flexibility of software implementation. When running a sensorless control algorithm for PMSM, it achieves a 30.3% increase in execution efficiency, enabling support for higher frequency output PWM switching and making it suitable for the high-precision control of high-speed PMSM. [ABSTRACT FROM AUTHOR]

As an essential protection mechanism of information security, hash algorithms are extensively used in various security mechanisms. The diverse application scenarios make the implementation of hash algorithms more challenging regarding flexibility, performance, and resources. Since the existing studies have such issues as wasted resources and few algorithms are supported when implementing hash algorithms, we proposed a new reconfigurable hardware architecture for common hash algorithms in this paper. First, we used the characteristics of symmetry of SM3 (Shang Mi 3) and SHA2 (Secure Hash Algorithm 2) to design an architecture that also supports MD5 (Message Digest 5) and SHA1 (Secure Hash Algorithm 1) on both sides. Then we split this architecture into two layers and eliminated the resource wastes introduced by different word widths through exploiting greater parallelism. Last, we further divided the architecture into four operators and designed an array. The experimental results showed that our architecture can support four types of hash algorithms successfully, and supports 32-bit and 64-bit word widths without wasting resources. Compared with existing designs, our design has a throughput rate improvement of about 56.87–226% and a throughput rate per resource improvement of up to 5.5 times. Furthermore, the resource utilization rose to 80% or above when executing algorithms. [ABSTRACT FROM AUTHOR]

Recently, specifically designed video codecs have been preferred due to the expansion of video data in Internet of Things (IoT) devices. Context Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding module widely used in recent video coding standards such as HEVC/H.265 and VVC/H.266. CABAC is a well known throughput bottleneck due to its strong data dependencies. Because the required context model of the current bin often depends on the results of the previous bin, the context model cannot be prefetched early enough and then results in pipeline stalls. To solve this problem, we propose a prediction-based context model prefetching strategy, effectively eliminating the clock consumption of the contextual model for accessing data in memory. Moreover, we offer multi-result context model update (MCMU) to reduce the critical path delay of context model updates in multi-bin/clock architecture. Furthermore, we apply pre-range update and pre-renormalize techniques to reduce the multiplex BAE's route delay due to the incomplete reliance on the encoding process. Moreover, to further speed up the processing, we propose to process four regular and several bypass bins in parallel with a variable bypass bin incorporation (VBBI) technique. Finally, a quad-loop cache is developed to improve the compatibility of data interactions between the entropy encoder and other video encoder modules. As a result, the pipeline architecture based on the context model prefetching strategy can remove up to 45.66% of the coding time due to stalls of the regular bin, and the parallel architecture can also save 29.25% of the coding time due to model update on average under the condition that the Quantization Parameter (QP) is equal to 22. At the same time, the throughput of our proposed parallel architecture can reach 2191 Mbin/s, which is sufficient to meet the requirements of 8 K Ultra High Definition Television (UHDTV). Additionally, the hardware efficiency (Mbins/s per k gates) of the proposed architecture is higher than that of existing advanced pipeline and parallel architectures. [ABSTRACT FROM AUTHOR]

The foundation of every digital system is based on hardware in which security, as a core service of many applications, should be deeply embedded. Unfortunately, the knowledge of system security and efficient hardware design is spread over different communities and, due to the complex and ever-evolving nature of hardware-based system security, state-of-the-art security is not always implemented in state-of-the-art hardware. However, automated security-aware hardware design seems to be a promising solution to bridge the gap between the different communities. In this work, we systematize state-of-the-art research with respect to security-aware Electronic Design Automation (EDA) and identify a modern security-aware EDA framework. As part of this work, we consider threats in the form of information flow, timing and power side channels, and fault injection, which are the fundamental building blocks of more complex hardware-based attacks. Based on the existing research, we provide important observations and research questions to guide future research in support of modern, holistic, and security-aware hardware design infrastructures. [ABSTRACT FROM AUTHOR]

Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated compression algorithm due to the rapid development of video compression. As a result, the next model of video compression, High-Efficiency Video Coding (HEVC), provides high-quality video output while requiring less bandwidth. However, implementing the intra-prediction technique in HEVC requires significant processing complexity. This research provides a completely pipelined hardware architecture solution capable of real-time compression to minimize computing complexity. All prediction unit sizes of 4 × 4 , 8 × 8 , 16 × 16 , and 32 × 32 , and all planar, angular, and DC modes are supported by the proposed solution. The synthesis results mapped to Xilinx Virtex 7 reveal that our solution can do real-time output with 210 frames per second (FPS) at 1920 × 1080 resolution, called Full High Definition (FHD), or 52 FPS at 3840 × 2160 resolution, called 4K, while operating at 232 Mhz maximum frequency. [ABSTRACT FROM AUTHOR]

This paper proposes the design and optimization procedure for a low cost single-phase Static Synchronous Compensator (STATCOM) based on Cascaded H-bridge Multilevel Converter (CHBMC) topology. The CHBMC consists of two series-connected identical H-bridge converters so that five voltage levels at the AC side of STATCOM are attained. After summarizing the basic STATCOM operation and the modelling of the CHBMC topology, the STATCOM model connected to a 220 V single-phase grid is simulated in order to verify closed-loop operation of the STATCOM. In this study, two PI controllers are used for reactive power control and regulating the average DC link voltage of the two H-bridge converters. The optimization of the PI controller parameters are achieved by particle swarm optimization method. Finally, the hardware design of a small power rated of single-phase STATCOM connected to 220 V grid is realized and verified experimentally. Phase shifted multi-carrier sinusoidal pulse width modulation is chosen to drive the MOSFET switches. It is shown that STATCOM is able to be operate both in capacitive and inductive mode of operation and injects the desired amount of reactive power into the grid. The advantages of the developed prototype are low-cost, easy to implement and upgradable to higher voltage/power levels. [ABSTRACT FROM AUTHOR]

The evolutionary robotics field offers the possibility of autonomously generating robots that are adapted to desired tasks by iteratively optimising across successive generations of robots with varying configurations until a high-performing candidate is found. The prohibitive time and cost of actually building this many robots means that most evolutionary robotics work is conducted in simulation, but to apply evolved robots to real-world problems, they must be implemented in hardware, which brings new challenges. This paper explores in detail the design of an example system for realising diverse evolved robot bodies, and specifically how this interacts with the evolutionary process. We discover that every aspect of the hardware implementation introduces constraints that change the evolutionary space, and exploring this interplay between hardware constraints and evolution is the key contribution of this paper. In simulation, any robot that can be defined by a suitable genetic representation can be implemented and evaluated, but in hardware, real-world limitations like manufacturing/assembly constraints and electrical power delivery mean that many of these robots cannot be built, or will malfunction in operation. This presents the novel challenge of how to constrain an evolutionary process within the space of evolvable phenotypes to only those regions that are practically feasible: the viable phenotype space. Methods of phenotype filtering and repair were introduced to address this, and found to degrade the diversity of the robot population and impede traversal of the exploration space. Furthermore, the degrees of freedom permitted by the hardware constraints were found to be poorly matched to the types of morphological variation that would be the most useful in the target environment. Consequently, the ability of the evolutionary process to generate robots with effective adaptations was greatly reduced. The conclusions from this are twofold. 1) Designing a hardware platform for evolving robots requires different thinking, in which all design decisions should be made with reference to their impact on the viable phenotype space. 2) It is insufficient to just evolve robots in simulation without detailed consideration of how they will be implemented in hardware, because the hardware constraints have a profound impact on the evolutionary space.

Electrical impedance tomography (EIT) has been used by researchers across several areas because of its low-cost and no-radiation properties. Researchers use complex conductivity in bioimpedance experiments to evaluate changes in various indicators within the image target. The diverse volumes and edges of biological tissues and the large impedance range impose dedicated demands on hardware design. The EIT hardware with a high signal-to-noise ratio (SNR), fast scanning and suitable for the impedance range of the image target is a fundamental foundation that EIT research needs to be equipped with. Understanding the characteristics of this technique and state-of-the-art design will accelerate the development of the robust system and provide a guidance for the superior performance of next-generation EIT. This review explores the hardware strategies for EIT proposed in the literature.

Polynomial multiplication is the most computationally expensive part of the lattice-based cryptography algorithm. However, the existing acceleration schemes have problems, such as low performance and high hardware resource overhead. Based on the polynomial multiplication of number theoretic transformation (NTT), this paper proposed a simple element of Montgomery module reduction with pipeline structure to realize fast module multiplication. In order to improve the throughput of the NTT module, the block storage technology is used in the NTT hardware module to enable the computing unit to read and write data alternately. Based on the NTT hardware module, a precalculated parameter storage and real-time calculation method suitable for the hardware architecture of this paper is also proposed. Finally, the hardware of polynomial multiplier based on NTT module is implemented, and its function simulation and performance evaluation are carried out. The results show that the proposed hardware accelerator can have excellent computing performance while using fewer hardware resources, thus meeting the requirements of lattice cipher algorithms in security chips. Compared with the existing studies, the computing performance of the polynomial multiplier designed in this paper is improved by approximately 1 to 3 times, and the slice resources and storage resources used are reduced by approximately 60% and 17%, respectively. [ABSTRACT FROM AUTHOR]

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) is a key technology for wireless communication systems. However, because of the problem of a high peak-to-average power ratio (PAPR), OFDM symbols can be distorted at the MIMO OFDM transmitter. It degrades the signal detection and channel estimation performance at the MIMO OFDM receiver. In this paper, three deep neural network (DNN) models are proposed to solve the problem of non-linear distortions introduced by the power amplifier (PA) of the transmitters and replace the conventional digital signal processing (DSP) modules at the receivers in 2 × 2 MIMO OFDM and 4 × 4 MIMO OFDM systems. Proposed model type I uses the DNN model to de-map the signals at the receiver. Proposed model type II uses the DNN model to learn and filter out the channel noises at the receiver. Proposed model type III uses the DNN model to de-map and detect the signals at the receiver. All three model types attempt to solve the non-linear problem. The robust bit error rate (BER) performances of the proposed receivers are achieved through the software and hardware implementation results. In addition, we have also implemented appropriate hardware architectures for the proposed DNN models using special techniques, such as quantization and pipeline to check the feasibility in practice, which recent studies have not done. Our hardware architectures are successfully designed and implemented on the Virtex 7 vc709 FPGA board. [ABSTRACT FROM AUTHOR]

NIST post-quantum cryptography standardization round 3 announced CRYSTALS-Kyber as one of the finalists. As a lattice-based cryptography scheme, CRYSTALS-Kyber performance relies on polynomial multiplication efficiency. This paper presents a high-speed and pipelined hardware number theoretic transform (NTT) and INTT accelerator for CRYSTALS-Kyber. Our work centers around designing and optimizing the NTT accelerator architecture with suitable parameter for hardware implementations of CRYSTALS-Kyber. The work includes modifying the modular arithmetic modules and butterfly units structure with an efficient low-complexity algorithm. As a result, our design achieved 237 MHz fmax when synthesized on Intel FPGA Cyclone V with Quartus. Resources utilization through combinational logic path rebalances allowed us to efficiently pipeline between hardware modules. [ABSTRACT FROM AUTHOR]