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Fingerling counting is a basic operation in fish farming and provides an important guideline for many aspects of aquaculture. However, most of the current counting methods are inefficient or computationally cumbersome. This study proposed a high-speed, non-intrusive fingerling counting method based on multiple detectors and a motion prediction model, which achieved high-accuracy counting under the condition of low-frame rate. Firstly, to effectively detect and locate the adherent fingerlings, the detector was accomplished by combining the mixture of Gaussian-based (MOG) segmentation algorithm and the local extremum-based blob detection algorithm. Secondly, three different functions were used to construct a motion prediction model to predict the approximate probability of the fingerlings at each position in the previous frame. Thirdly, the cost matrix was constructed with probability as the feature to associate the fingerlings in the consecutive frames, and the newly appeared fingerlings were counted in real-time, realising the continuous fingerling counting with high precision. Through testing and analysis on 52 collected datasets under low-frame-rate (10 fps) acquisition conditions using largemouth bass (Micropterus salmoides , 3–5 cm) and crucian carp (Carassius auratus , 2–6 cm), results indicated that the best motion prediction model with segmentation function reached over 99% average counting accuracy for both species, with a standard deviation of accuracy less than 0.7%. This method provides a low-cost, high-speed, and stable application solution for computer vision-based fingerling counting. • Combined Mixture of Gaussian segmentation and blob detection for fingerling counting. • Integration of a motion prediction model achieved over 99% average counting accuracy. • Open access to a dataset containing annotation files for fingerlings counting. [ABSTRACT FROM AUTHOR]

Researchers are currently emphasizing the development of memory design based on memristors as a solution to the challenges posed by MOSFET-based designs. In this paper, a memristor-based ternary content addressable memory (MTCAM) has been designed and analyzed that is both high-speed and energy-efficient, while also occupying minimal area. The proposed MTCAM cell has five transistors and four memristors (referred to as 5T4M). It comprises two operational units: the main unit responsible for WRITE and SEARCH functions, composed of three transistors and two memristors, and the data recall unit, which is activated when data restoration is needed. This research work has been simulated in HSPICE with a 32-word array, each containing 144-digit MTCAM cells, using PTM 32 nm 0.9 V strained Si technology. The results indicate a search time of 204.6 ps and a search energy of 0.521 fJ/digit/search for worst-case mismatches, all achieved with a 1.2 V supply voltage. Furthermore, the implemented 32 × 144 MTCAM array provides a voltage margin of 331.38 mV. The 5T4M MTCAM design occupies an estimated area of 1.4904 μm2, which is notably compact compared to existing designs. [ABSTRACT FROM AUTHOR]

The hierarchic assembly of fibrillar collagen into an extensive and ordered supramolecular protein fibril is critical for extracellular matrix function and tissue mechanics. Despite decades of study, we still know very little about the complex process of fibrillogenesis, particularly at the earliest stages where observation of rapidly forming, nanoscale intermediates challenges the spatial and temporal resolution of most existing microscopy methods. Using video rate scanning atomic force microscopy (VRS-AFM), we can observe details of the first few minutes of collagen fibril formation and growth on a mica surface in solution. A defining feature of fibrillar collagens is a 67-nm periodic banding along the fibril driven by the organized assembly of individual monomers over multiple length scales. VRS-AFM videos show the concurrent growth and maturation of small fibrils from an initial uniform height to structures that display the canonical banding within seconds. Fibrils grow in a primarily unidirectional manner, with frayed ends of the growing tip latching onto adjacent fibrils. We find that, even at extremely early time points, remodeling of growing fibrils proceeds through bird-caging intermediates and propose that these dynamics may provide a pathway to mature hierarchic assembly. VRS-AFM provides a unique glimpse into the early emergence of banding and pathways for remodeling of the supramolecular assembly of collagen during the inception of fibrillogenesis. [ABSTRACT FROM AUTHOR]

The lifespan of the guide rail is a bottleneck restricting the operational life of electromagnetic railguns. A well‐designed arc extinguishing device can reduce the arcing erosion caused by residual currents within the guide rail. The CuW alloy is widely used in the high‐pressure arc extinction field due to its excellent electrical and thermal conductivity, high strength, and hardness. Based on the theory of equilibrium state arc plasma, a finite element model of the air arc‐CuW electrode coupling in the arc extinction device was established to study millisecond‐level arc initiation, evolution, extinguishing characteristics, and distribution patterns under extreme and harsh operational conditions with a current input of 110 kA. The highest temperature in the arc column region was found to exceed 50,000 K. The study elucidated the influence of arc extinction device parameters on arc evolution, breakdown time, and breakdown voltage. Consequently, it established that the R70 spherical electrode exhibits optimal arc extinguishing characteristics. The aim of this research is to provide theoretical support for optimizing the arc suppression device. Additionally, experiments on high‐speed and high‐current arc extinction device discharges were conducted to validate the finite element analysis results regarding arc diffusion patterns and electrode erosion. [ABSTRACT FROM AUTHOR]

A self-aligned focusing schlieren (SAFS) system combines the field of view of a conventional schlieren system with the defocus blur of a focusing schlieren system away from the object plane. It can be assembled in a compact form, measuring 1.2 m (4 ft) in length in the described case. The depth of field is sufficiently shallow to distinguish specific spanwise features in a supersonic flow field within a 76.2 mm (3 in) wide test section. As a result, the boundary-layer perturbations on windows and window-material defects and surface imperfections are blurred. Analytical forms are derived for depth of field and vignetting of the SAFS system. A laser spark velocity measurement in Mach 2 flow is performed by tracking the blast wave of a laser spark using 500 kHz SAFS imaging with a 200 ns optical pulse width. The flow Mach number and stagnation temperature are measured by comparing the blast-wave dynamics to an analytical solution. Additionally, schlieren image velocimetry is performed by analyzing natural flow perturbations in 500 kHz SAFS images using a self-correlation method. Comparing the spectra of gas density perturbations from the core flow and a near-wall region reveals a significant difference, with high-frequency prevalence at the boundary-layer location. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Xi'an Jiaotong University is the property of Editorial Office of Journal of Xi'an Jiaotong University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods. [ABSTRACT FROM AUTHOR]

Pedestrian crashes at high-speed locations are a persistent road safety concern. Driving at high speeds means that the driver has less time to react and make evasive maneuvers to avoid a pedestrian crash. On top of this, other crash-contributing factors such as humans (pedestrians or drivers), vehicles, roadways, and surrounding environmental factors actively interact together to cause a crash at high-speed locations. The pattern of pedestrian crashes also differs significantly according to the high-speed intersection and segment locations which require further investigation. This study applied association rules mining (ARM), an unsupervised learning algorithm, to reveal the hidden association of pedestrian crash risk factors according to the high-speed intersection and segments separately. The study used Louisiana pedestrian fatal and injury crash data (2010 to 2019). Any crash location with a posted speed limit of 45 mph or above is classified as a high-speed location. Based on the generated association rules, the results show that pedestrian crashes at a high-speed intersection are associated with the intersection geometry (3-leg) and control (1 stop, no traffic control device), driver characteristics (careless operation, failure to yield, inattentive-distracted, older, and younger driver), pedestrian-related factors (violations, alcohol/drug involvement), settings (open country, residential, business, industrial), dark lighting conditions and so on. Most pedestrian crashes at high-speed segments are associated with roadways with no physical separation, dark-no-streetlight conditions, open country locations, interstates and so on. The findings of the study may help to select appropriate countermeasures to reduce pedestrian crashes at high-speed locations.

Traffic replay can effectively improve the fidelity of network emulation and support emerging network verification and network security evaluation. A distributed traffic replay system based on cloud platform is designed for large-scale, high-speed and highly concurrent network traffic emulation, named DTRS. Aiming at the diverse network traffic, a scalable multi-stream replay method is proposed to realize the flexible reproduction of multiple protocol traffic. A traffic replay strategy based on DPDK is proposed to achieve accurate control of the replay process and improve the timing fidelity of replay. To solve the problem of insufficient traffic replay speed, a vector packet processing strategy based on VPP is proposed to improve the throughput. The experimental results show that DTRS can realize the scalable loading of diverse network traffic, and support the flexible, realistic and controllable reproduction of massive heterogeneous network scenarios. In high- speed traffic emulation, DTRS can ensure the timing fidelity of replay. Compared with traditional methods, the traffic replay throughput of DTRS has increased by 3.71 times. [ABSTRACT FROM AUTHOR]

The letter presents a low‐windage omnidirectional antenna for high‐speed aircraft in the UHF and L bands. It combines a planar biconical antenna with a printed tape parasitic branch monopole antenna. Upgrading the traditional restricted‐length biconical antenna to a double‐layer planar design meets the compact, lightweight, and low windage requirements of airborne use. To enhance bandwidth and meet the lightweight, compact criteria of high‐speed aircraft, the planar‐printed monopole antenna integrates parasitic stubs and loop antenna concepts. Experimental results exhibit excellent isolation between antenna elements, with over 15 dB segregation and operational spectrum return loss of 27% and 18% at 10 dB. The voltage standing wave ratio is below 2, with less than 5 dB variation in the horizontal radiation pattern across frequency bands. The antenna, measuring 20 mm × 190 mm × 270 mm and weighing around 0.5 kg, holds great promise for high‐speed aircraft applications. [ABSTRACT FROM AUTHOR]

An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver. [ABSTRACT FROM AUTHOR]

To investigate the influence of structural parameters on the performances and internal flow characteristics of partial flow pumps at a low specific speed of 10000 rpm, special attention was paid to the first and second stage impeller guide vanes. Moreover, the impeller blade outlet width, impeller inlet diameter, blade inclination angle, and number of blades were considered for orthogonal tests. Accordingly, nine groups of design solutions were formed, and then used as a basis for the execution of numerical simulations (CFD) aimed at obtaining the efficiency values and heads for each design solution group. The influence of impeller geometric parameters on the efficiency and head was explored, and the “weight” of each factor was obtained via a range analysis. Optimal structural parameters were finally chosen on the basis of the numerical simulation results, and the performances of the optimized model were verified accordingly (yet by means of CFD). Evidence is provided that the increase in the efficiency and head of the optimized model was 12.11% and 23.5 m, respectively, compared with those of the original model. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H. [ABSTRACT FROM AUTHOR]

There will be adverse effects on human health while the exposure of Radio frequency (RF) waves is long term in the indoor environment. The old age people, children's and patients will be badly affected, if their immune system is weak. In such environment, the visible light communication (VLC) is the preferred communication technique which provides immunity towards the adverse effects by RF. Presently the fluorescent lamps were replaced by light-emitting diodes (LEDs) in the indoor environment. The practice of utilizing the LEDs have been penetrated in many areas in our day to day life. The device will provide lightning capabilities and also information broadcast. In VLC for the purpose of data transmission and reception, the LED light source and photodetector (PD) were used. The work presents about VLC channel model, LED characteristics, data transmission model (RPO-OFDM-vDSM model) in indoors which provides better spectral efficiency and data rate. [ABSTRACT FROM AUTHOR]

The planned missions to explore the surfaces of the Moon and Mars require high exploration efficiency, thus imposing new demands on the mobility system of planetary rovers. In this paper, a design method for a high-speed planetary rover (HPR) is proposed, and the representative configurations are modeled and simulated. First, the influence of the planetary surface environment on the design of HPRs is analyzed, and the design factors for HPRs are determined by studying a single-wheel suspension. Second, a design methodology for HPRs is proposed. The adaptive suspension mechanisms of a four-wheeled rover are synthesized using the all-wheel-attachment condition and position and orientation characteristics theory, which are expressed in the form of a graph theory for the increase in elastic components and active joints. Finally, a dynamic model is built, and a simulation is carried out for the proposed rover. The validity of the proposed method and rover is verified, thus highlighting their potential application in future planetary exploration. [ABSTRACT FROM AUTHOR]

[This corrects the article DOI: 10.3389/frobt.2022.1033715.].

In the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and subsequently, a smaller area is occupied. Replacing MOSFET transistors with FinFETs reduces the delay and power consumption of the circuit, so the overall performance is improved. The first innovation of the proposed design is that to reduce the size and power consumption, two transistors were removed and the back gates of two transistors were cross-coupled. The second innovation is the connection of back gates to other suitable points of the circuit that increase the speed of comparison. In this study, a supply voltage of 0.8 V is applied to the circuit to show that the proposed modifications with FinFET reduce the delay to 272 ps and power consumption to 6.7 µW.

Due to the inherent loss characteristics of transmission lines today, the challenges in signal transmission are increasing. Typically, the most widely used printed circuit boards (PCBs) in transmission lines employ FR-4 as the insulation material due to its advantages in electrical insulation and cost-effectiveness. Nevertheless, PCBs that rely solely on FR-4 for the entire insulation layer are unsuitable for high-speed circuits due to significant dielectric losses. Efforts have been made to reduce losses by researching hybrid-stackup PCBs that stack low loss dielectric materials vertically. However, due to the high cost of these low loss dielectric materials, they have mainly been applied in high-end and high-speed applications. Therefore, in this paper, we propose a hybrid-plane PCB structure that uses low loss dielectric materials only in the planes adjacent to high-speed signal traces, minimizing the use of expensive low loss dielectric materials while achieving similar enhancements in signal quality compared to previously researched hybrid-stackup each PCB was modeled using Ansys Q2D Extractor, and S-parameters and eye diagrams were extracted for each to compare their electrical characteristics and signal quality. The simulation results confirm that the proposed hybrid-plane PCB structure in this paper has been found to exhibit improved electrical characteristics compared to PCBs constructed solely with an FR-4 insulation layer. Furthermore, various low loss dielectric thicknesses were compared to interpret the optimal thickness of the low loss dielectric for the hybrid-plane PCB, based on the signal integrity assurance rate.

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology. [ABSTRACT FROM AUTHOR]

A ditching device has been widely used for rapeseed direct-seeding in the rice-oil rotation areas of the mid-lower reaches of the Yangtze River. However, the high-power consumption and unstable furrow shape cannot fully meet the large-scale production in recent years, when operating at the high speed (≥10 km/h). In this study, a quasi-propeller ditching device was developed with a blade-soil contact surface similar to that of a propeller suitable for high-speed no-tillage rapeseed direct seeder. The ditching blade group was also optimized. A quasi-propeller cutter group consisted of four sets of cutters. The blade layout structure was then determined using kinematics and dynamics. An optimal model of power consumption and soil throwing efficiency was established for the operation of the blade group using dynamic analysis. The key structural parameters and working factors were determined to improve the power saving and soil throwing efficiency in the ranges of parameters. Single-factor tests were conducted on the blade edge type, pitch angle, and bending angle using EDEM software. The results show that the smallest resistance was achieved in the back blade edge type; The blade resistance first decreased and then increased, as the pitch angle increased, whereas, the soil throwing performance decreased significantly; There was a decrease in the overall resistance of the blade group and the soil throwing performance, as the bending angle increased. Once the blade edge structure of the cutter-1, cutter-2, cutter-3, and cutter-4 was the back edge (BE) type, the pitch angles were 7°, 5°, 4°, and 3°, respectively, and the bending angles were 120°, 120°, 90°, and 90°, indicating the relatively small resistance of the cutter group and the better performance of soil throwing. A Box-Behnken simulation test was conducted on the pitch angle, working velocity, and cutter rotary speed, according to a single factor test. A genetic algorithm (GA) was also used for the multi-objective optimization in the power consumption and soil throwing performance. Box-Behnken results showed that the pitch angle, cutter rotary speed, and working velocity greatly contributed to the power consumption. The most significant impact was found on the working velocity, indicating the lower working velocity and the higher cutter rotary speed, while the higher efficiency of soil throwing. After optimization, the optimal pitch angles of cutter-1, cutter-2, cutter-3, and cutter-4 were 6.7°, 4.7°, 3.5°, and 2.5°, respectively; The optimal rotary speeds of the cutter were 540, 620, and 810 r/min, respectively, at the working velocity of 6, 9, and 12 km/h; The power consumption of the optimized blade group was lower than that of the control group and the international IS225 blade group; The total power consumption of the optimized cutter group was reduced by 5.51-28.99 kW, compared with the control group. The higher the working velocity was, the higher the resistance reduction rate was; The reduction rate of resistance was the highest at 12 km/h, about 41%. Field experiments showed that the total power consumption of the optimized ditching device was 15.1-41.8 kW when operating at a speed of 6-12 km/h, with a relative error of less than 10%, compared with the simulation. The width range of the furrow was 421.3-452.7 mm, the depth range was 163.7-178.7 mm, the stability coefficient range of the furrow width was 95.2%-98.6%, and the stability coefficient range of the furrow depth was 93.8%-97.5%. The working velocity also caused the furrow pattern to change from a circular arc to a V-shape. This research can provide a strong reference to improve the high-speed ditching device for the rapeseed direct-seeding in the rice-oil rotation cropping area of the mid-lower reaches of the Yangtze River. [ABSTRACT FROM AUTHOR]

Abstract Electric motors are used globally, especially in industrial applications, and achieving high energy efficiency is a major problem. Variable transmissions are effective in reducing the energy consumption of motors, but practical variable transmissions are bulky and heavy, making them unsuitable for robots. To overcome this problem, two motor-driven mechanisms have been proposed. The two motors are operated independently and assigned to the high-speed drive and high-torque drive, and one motor always becomes dead weight. Therefore, we propose a coupled-driven switchable transmission system that can switch the high-speed and high-torque drives by combining the rotation directions and utilizing the output of both motors. The developed device uses two 22-W motors and can switch the reduction ratio from 1/15 to 1/375. The maximum torque, maximum rotation speed, and weight are 10 Nm, 500 rpm, and 905 g, respectively. The experimental results show that the relative speeds of two motors are significant for the coupled drive; nevertheless, this device can be controlled by conventional voltage control without precise speed control.

A self-aligned focusing schlieren (SAFS) system combines the field of view of a conventional schlieren system with the defocus blur of a focusing schlieren system away from the object plane. It can be assembled in a compact form, measuring 1.2 m (4 ft) in length in the described case. The depth of field is sufficiently shallow to distinguish specific spanwise features in a supersonic flow field within a 76.2 mm (3 in) wide test section. As a result, the boundary-layer perturbations on windows and window-material defects and surface imperfections are blurred. Analytical forms are derived for depth of field and vignetting of the SAFS system. A laser spark velocity measurement in Mach 2 flow is performed by tracking the blast wave of a laser spark using 500 kHz SAFS imaging with a 200 ns optical pulse width. The flow Mach number and stagnation temperature are measured by comparing the blast-wave dynamics to an analytical solution. Additionally, schlieren image velocimetry is performed by analyzing natural flow perturbations in 500 kHz SAFS images using a self-correlation method. Comparing the spectra of gas density perturbations from the core flow and a near-wall region reveals a significant difference, with high-frequency prevalence at the boundary-layer location.

Electric motors are used globally, especially in industrial applications, and achieving high energy efficiency is a major problem. Variable transmissions are effective in reducing the energy consumption of motors, but practical variable transmissions are bulky and heavy, making them unsuitable for robots. To overcome this problem, two motor-driven mechanisms have been proposed. The two motors are operated independently and assigned to the high-speed drive and high-torque drive, and one motor always becomes dead weight. Therefore, we propose a coupled-driven switchable transmission system that can switch the high-speed and high-torque drives by combining the rotation directions and utilizing the output of both motors. The developed device uses two 22-W motors and can switch the reduction ratio from 1/15 to 1/375. The maximum torque, maximum rotation speed, and weight are 10 Nm, 500 rpm, and 905 g, respectively. The experimental results show that the relative speeds of two motors are significant for the coupled drive; nevertheless, this device can be controlled by conventional voltage control without precise speed control. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an innovative concept of a high‐speed and higher order adaptive filter. A fully analog artificial neural network handles the adaption by using a filter bank for filtering and learning through analog feedback inspired by backpropagation. There is no clock control used in this concept, which makes real‐time adaption possible even for high frequencies. Its functionality is shown by several electrical circuit simulations involving component inaccuracies as well as a commonly used filter example. [ABSTRACT FROM AUTHOR]

The emergence of organic electrochemical transistors (OECTs) has opened a new era of printable electronics and bioelectronics, due to their unique advantages including innately superior transconductance and biocompatibility. Despite the foreseeable advancements available from their further implementations in fundamental logic circuitry, however, insufficient operation speeds and short compatibilities to scaling‐down have so far hindered advanced integrations other than biosensing and biosignal amplifications. Here, a 3D‐construction‐dependent operational analysis of OECTs is reported, with which an all‐vertical architectural design enabled unprecedentedly high operating speed and a facile expansion to large‐area and high‐density 3D crossbar arrays. A simple vertical channel architecture completed with solid‐state Ag/AgCl top‐gate electrodes enables an ultrafast redistribution of ions within channels, yielding a state‐of‐the‐art operation frequency reaching 12 MHz V−1. Various printed logic circuit arrays, including NOT, NAND, and NOR gates, with high stability and reproducibility. [ABSTRACT FROM AUTHOR]

The development of deep space exploration has led to new exploration demands that cannot be met by traditional planetary rovers. This paper proposes a new wheeled rover that combines the advantages of passive all-wheel attachment and vibration reduction at high speeds. This rover can achieve vibration reduction in the vertical direction from ground excitation, preventing the instability of pitch and roll. Flexible wheels were used to reduce the high-frequency excitation of the ground on the rover. The design concept and mechanical principle of the proposed rover were comprehensively analyzed. A quasi-static kinematic model was developed to analyze the overstepping performance of the rover with this new design. Further, the response characteristics of the system to the ground excitation were investigated by vibration equations established using the Lagrangian method. The optimal parameters were obtained using a genetic algorithm to optimize the system with multiple objectives. Furthermore, the overstepping performance, all-wheel attachment, and vibration reduction of the planetary rover were verified through multi-body simulation. The proposed rover has considerable potential for missions such as the Mars sample return and planetary station construction. • A planetary rover with adaptive suspension for high-speed driving is proposed. • The theoretical analysis of the climbing ability of a planetary rover is provided. • A vibration modeling and evaluation method for proposed rover is established. • A variety of objective functions are proposed and optimized accordingly. [ABSTRACT FROM AUTHOR]

Direct seeding has been one of the most efficient cultivation modes for a wide range of plants, such as rapeseed. Among them, the existing ditching device cannot fully meet the practical direct seeding in recent years, due to the low stability of the furrow shape and the seedbeds on both sides of the furrow. In this study, a propeller-type ditching device was designed to actively open the furrows at high speed (≥10 km/h) and simultaneously distribute the soil in the middle and lower reaches of the Yangtze River. A quasi-propeller ditching blade was then proposed, according to the working mode of propellers. The blade arrangement was determined using kinematic and dynamic analysis. The critical parameters (the pitch and edge structures) were also determined to reduce the cutting resistance. A simulation experiment of the blade cutting was carried out using the discrete element model of the blade cutter-soil system. The simulation results indicated that the cutting resistance first decreased and then increased with the increase of the pitch angle, whereas, the rear grinding edge reduced the soil cutting resistance. The quasi-propeller blade group with the optimal combination of pitch angle and edge structure achieved a resistance torque of 176.6 N·m and a traction resistance reduction of 447.7 N, compared with the straight spoon-blade group with a travel speed of 12 km/h and rotation speed of 810 r/min. The dynamic analysis was implemented to determine the curved structure parameters of the soil homogenizing plate. Furthermore, a soil-distributing simulation experiment was carried out using the ditching cutter-soil distributing plate-soil interaction model. The better performance of soil distributing was achieved, when the camber of the left and right distributing plates was 0.19 and the down-inclination angle was 10° and 7°, respectively. The field experiment indicated that the work quality of the overall device fully met the requirements of direct rapeseed seeding when operating at a high speed of 9-12 km/h. An optimal combination was achieved: the furrow depth was 169.1-188.6 mm, the furrow depth stability coefficient was 92.5%-95.6%, the flatness of the furrow surface was 22.2-23.0 mm, the coefficient of variation of soil distributing on both sides was 14.3% and 17.2%, and the stubble burying rate was 81.96%-87.46%, the operating power consumption at the operating speed of 12 km/h was 66.84 kw. This finding can provide a strong reference for the high-speed no-tillage, ditching, and high-quality seedbed preparation for rapeseed in the rice-oil rotation areas of the mid-lower Yangtze River. [ABSTRACT FROM AUTHOR]

The access network is developing towards large capacity, wide-coverage, and low delay, which puts forward higher requirements for network structure and data exchange performance of optical access network equipment. In this paper, we have designed a high-speed optical network device with 40/10G TDM-PON. To effectively solve the problem of network switching capability in high-speed data transmission, we propose a low delay large capacity switching algorithm, which minimizes the network switching delay. We model the network by integer linear programming and simulate the network based on OMNeT++. The simulation results show that the algorithm can effectively solve the problem of network switching delay in the high-speed network environment. [ABSTRACT FROM AUTHOR]

ABSTRACT During high-speed seeding operations, collisions between seeds and seed guide tubes are very significant, resulting in poor seed spacing uniformity. To solve this problem, a high-speed seed guide device with conical spiral airflow was designed, which can use high-speed positive pressure airflow to move seeds smoothly. To improve the uniformity of the airflow field in the device, a single-factor test was carried out to determine the reasonable range of each factor. Then, the four-factor and five-level central composite test was carried out. The four main factors were screw pitch, cone angle, width of gap, and angle of air-tube, and the evaluation index was the mean variance of airflow velocity. The test results showed that the optimal parameters of the high-speed seed guide device with conical spiral airflow were a screw pitch of 24.98 mm, cone angle of 7.47/55, width of gap of 5.31 mm, and angle of air-tube of 25.09º. The verification test showed that the relative error between the verification test value and the predicted value was less than 5%, indicating that the model had high reliability. This research can provide references for the research of high-speed seed guide technology and the innovative design of seed guide devices.

This paper introduces an enhanced Hardware-Software Co-Design implementation of Connect6 game solver compared to a prevalent implementation by using novel data communications and enhanced tree-searching algorithms. Hardware-software communication is improved by transferring the current board position from the Processing System to the Programmable Logic through a 21-bit change board instead of the complete 722-bit board. Tree-search, to find the next best move, is enhanced by using Negascout algorithm, Iterative Deepening, Node Ordering and Memoization. The proposed design demonstrates 50 % improvement in the overall performance and 92 % in communication overhead compared to the prevalent implementation. Further, it is around 4 times faster than its software implementation on the same platform. The analysis was carried on Xilinx Zedboard SOC using the GNU GCC Compiler with the Maximum Optimisation Flag (O3) activated.

We present QUaRTM - a novel quadcopter design capable of tilting the propellers into the forward flight direction, which reduces the drag area and therefore allows for faster, more agile, and more efficient flight. The vehicle can morph between two configurations in mid-air, including the untilted configuration and the tilted configuration. The vehicle in the untilted configuration has a higher pitch torque capacity and a smaller vertical dimension. The vehicle in the tilted configuration has a lower drag area, leading to a higher top speed, higher agility at high speed, and better flight efficiency. The morphing is accomplished without any additional actuators beyond the four motors of a quadcopter. The rigid connections between the quadcopter frame and the quadcopter arms are replaced with sprung hinges. This allows the propellers to be tilted when high thrusts are produced, and recover to the untilted configuration when the thrusts are brought low. The effectiveness of such a vehicle is demonstrated by running experiments on a prototype vehicle with a shape similar to a regular quadcopter. Through the use of tilting, the vehicle is shown to have a 12.5% higher maximum speed, better high-speed agility as the maximum crash-free cruise speed increased by 7.5%, and a better flight efficiency as the power consumption has dropped by more than 20% in the speed range of 15-20 m s-1.

An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver.

In human motion capture systems, reflective markers attached to the body have been widely used to track motion using optical cameras. However, when the speed of motion increases, because the brightness and angle of view of the camera are limited, and the markers often fall off, particularly of detailed body parts such as fingers in full-body movements, other parts of the body (palms) have been investigated. This study attempted to acquire finger movements during a high-speed throwing task without attaching markers using automatic image recognition technology based on deep learning (DeepLabCut) and verified its accuracy compared to conventional methods. As a result, the absolute distance between the 3D coordinates obtained from the two motion capture systems was an average of 15.5 to 29.4 mm depending on tracked points, and the correlation coefficients between them ranged from 0.932 to 0.999. Therefore, the shapes of the time-series profiles of the 3D coordinates obtained from the two motion- capture systems were similar. These results suggest that motion measurement using markerless motion capture is possible in environments where conventional motion capture systems are difficult to use.

The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10 − 6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving. [ABSTRACT FROM AUTHOR]

This article introduces a new fault-tolerant design approach based on approximate computing, called FAC, for designing redundant circuits and systems. Traditionally, triple modular redundancy (TMR) has been used to ensure complete tolerance to any single fault or a faulty processing unit, where the processing unit may be a circuit or a system. However, TMR incurs more than 200% overhead in terms of area and power compared to a single processing unit. Alternative redundancy approaches have been proposed in the literature to mitigate these overheads associated with TMR, but they provide only partial or moderate fault tolerance. Among the alternatives, majority voting-based reduced precision redundancy (MVRPR) may be useful for error-resilient applications such as digital signal processing. While MVRPR guarantees only moderate fault tolerance, the proposed FAC is well-suited for error-resilient applications and ensures 100% tolerance to any single fault or a faulty processing unit, like TMR. In this work, we evaluate the performance of TMR, MVRPR, and FAC for a digital image processing application. The image processing results obtained demonstrate the effectiveness of FAC. Moreover, when the processing unit is implemented using a 28-nm CMOS technology, FAC achieves significant improvements over TMR, including a 15.3% reduction in delay, a 19.5% reduction in area, and a 24.7% reduction in power. Compared to MVRPR, FAC exhibits notable enhancements, with an 18% reduction in delay, a 5.4% reduction in area, and an 11.2% reduction in power. When considering the power-delay product, which reflects energy efficiency, FAC demonstrates a 36.2% reduction compared to TMR and a 27.2% reduction compared to MVRPR. When considering the power-delay-area product, which represents design efficiency, FAC achieves a 48.7% reduction compared to TMR and a 31.1% reduction compared to MVRPR. [ABSTRACT FROM AUTHOR]

By setting textures on the side walls of a rotor, based on SST k-ω turbulence and the mixture model, the effects of depth-to-diameter ratio, shape, and rotational speed on interface temperature are analyzed. Local Nu number, flow field in textures, and gas distribution are used to verify the conclusion. When rotational speed increases, there are three different stages on the surface: liquid-dominated, mixed two-phase, and gas-dominated. This leads to a big difference in heat transfer on the side wall and causes the temperature on the seal face to increase when cavitation is considered. The distribution of the gas phase is explained through drag reduction, which has a high correlation with the velocity gradient near the surface. For several common shapes, heat transfer enhancement of textures is compared under high speed. The key influencing factor is the depth-to-diameter ratio, which causes flow stratification and reduces heat transfer. Flow stratification leads to different results of maximum temperature on the seal face when cavitation is considered. Results show that at high speed, a deep, circular texture is better when cavitation does not occur, and a shallow triangular texture is recommended when cavitation occurs; a textured side wall can reduce the maximum temperature of the seal face by about 10 °C. [ABSTRACT FROM AUTHOR]

• Characteristics of non-uniform pressure in a twin-screw compressor are revealed. • A new phenomenon of pressure waves inside a twin-screw compressor is discovered. • A fast method to estimate the influence of pressure waves is proposed. • A novel direction for the compressor design is suggested. To achieve higher efficiency of twin-screw compressors for refrigeration, the non-uniform internal pressure distribution in the rotor chamber and the flat section in the p-θ diagram were investigated in this paper. A three-dimensional CFD model of a twin-screw refrigeration compressor for chillers was established to analyze the generating mechanism of the flat section in the p-θ diagram. The p-θ diagrams of the compressor were compared under different rotational speeds and working fluids. Analysis results showed that the flat section in the p-θ diagram is caused by the periodic pressure wave propagation and reflection along the working chamber, and the pressure along the chamber is non-uniform when the sound speed is relatively slow compared with the chamber length in one compression cycle. A dimensionless ratio of chamber length and pressure wave travel distance is proposed to estimate the pressure distribution in the working chamber, based on which the flat section is prone to appear in large-scale compressors with low sound speed refrigerants like R134a. Some improvement directions were put forward to avoid efficiency losses, i.e., appropriately delaying the suction end angle and modifying the discharge port to match the pressure distribution. [ABSTRACT FROM AUTHOR]

During the conceptual and preliminary ship design stages, designers must ensure that the selected principal dimensions and parameters are good enough to deliver a stable ship (statically and dynamically), besides deadweight and speed. To support this, the initial intact stability of the proposed ship must be calculated, and for that, the lightship weight and its detailed breakdown are necessary to be known. After hull (steel) weight, machinery weight, mainly marine diesel propulsion and power generation machinery, plays a vital role in the lightship weight estimate of a ship directly. It also affects the deadweight, displacement, draft, and trim, which finally influence stability. The correct estimation of respective weights improves calculating a ship's initial stability, typically designed and built. Hence, it would be advantageous for the ship designer to convince the shipowner. Weight control is not easy, especially since its consequences in terms of deadweight and stability could be disastrous. It should start right at the beginning and control throughout the design and construction phases. Marine diesel main engines (MEs) and auxiliary engines (AEs) of various power output (generators output for AEs), engine speed, and cylinder number of different engine manufacturers are collected. These are analyzed and presented in tabular and graphical forms to demonstrate the possible relationship between propulsion engine weight and power generation engine weight, and their respective power, speed, and power-speed ratio. In this article, the authors have attempted to investigate the appraisal behavior of ME weight and AE weight regarding engine power, generator power, engine speed, and power-speed ratio (independent variables). Further attempts have been made to identify those independent variables that influence the weight of the propulsion engine and power generation engine (dependent variables) and their interrelationships. A mathematical model has thus been developed and proposed, as a guiding tool, for the designer to estimate the weight of main and AEs more accurately during the conceptual and preliminary design stages. [ABSTRACT FROM AUTHOR]

To 1) examine the periods in which maximal intensity sprints occurred during professional soccer matches and 2) analyze the maximal intensity sprints registered in match play considering the effect of playing position and other contextual variables. A total of 1252 match observations were collected from 277 male professional players. Sprinting actions at maximal intensity were analyzed during 30 matches, and both contextual and performance variables were collected using performance tracking systems. Maximal intensity sprints were more frequent in the first and last periods of the match (0'-15'; 75'-90'), regardless of the playing position (χ2=23.01; p=0.29; ES=0.07). These sprints were usually non-linear actions without possession of the ball and had different tactical purposes depending on the position. The mean sprint duration ranged from ~4.9 s to ~9 s, the mean distance covered ranged from ~30 m to ~55 m, while the mean maximum velocity was between ~30.12 and ~32.80 km/h depending on the tactical purpose and playing position. Professional soccer players need to be prepared during warm-ups for maximal intensity sprints in the first period of the match as well as maximal intensity sprints under high fatigue conditions given the frequency of sprints in the last period of the match. Also, training drills should be designed with a special focus on non-linear sprints without possession of the ball, based on the main tactical purpose of each position (e.g., CD: interceptions; MF: recovery runs; FB, WMF and FW: run the channel). [ABSTRACT FROM AUTHOR]