Search

Pseudo-random number generators are predominantly utilised as entropy sources in encryption and seeding processes, however, they are deterministic by nature. This paper presents the analysis and design methodology of an on-chip quantum noise source that may suitably be used as an entropy source in true random number generators. Quantum tunnelling is achieved through the strong biasing of a MOS structure to generate gate-referred shot noise. Structures are fabricated in a commercial 40 nm process and the sampled noise is tested against the NIST SP800-90B and SP800-22 test suites, showing a maximal entropy of 0.985 at a bias current of 1500 µA with a consistent pass rate across all NIST tests. [ABSTRACT FROM AUTHOR]

Abstract In Ultra‐Low‐Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time‐consuming Spice simulations are used to measure the static power consumption. Herein, a technology‐independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%–4%, while static power consumption of an FPGA system with an error of 1%–15%.

Abstract This study investigates the possibility of the carbon nanotube (CNT)‐based through‐silicon vias (TSVs) for improving power integrity of 3‐D integrated circuits (3‐D ICs). The circuit model is developed for 2‐bit CNT TSV and validated through the full‐wave electromagnetic simulator HFSS simulations. The 2‐bit CNT TSV is applied to power distribution networks (PDNs) by combining the validated equivalent‐circuit model and that TSV‐based PDN impedance is compared with the traditional one. By virtue of the large capacitance and low inductance of the 2‐bit CNT TSV, the PDN impedance of the 3‐D IC can be suppressed significantly and the anti‐resonant frequency can be increased.

Abstract The use of counterfeit integrated circuits (ICs) in electronic products decreases its quality and lifetime. Recycled ICs can be detected by the method of aging analysis. Aging is carried out through reliability analysis with the effect of hot carrier injection and bias temperature instability (BTI). In this work, three machine learning methods, namely K‐means clustering, back propagation neural network (BPNN) and support vector machines (SVMs), are used to detect the recycled IC aged for a shorter period (1 day) with minimum data size. This work also distinguishes the effects of degradation due to process variations and reliability effects. The reliability and Monte Carlo simulation are performed on benchmark circuits such as c17, s27, b02 and fully differential folded‐cascode amplifier using the Cadence Virtuoso tool, and the parameters such as minimum voltage, delay value, supply current, gain, phase margin and bandwidth are measured. Machine learning methods are developed using MATLAB to train and classify the parameters. From the results obtained, it is observed that the classification rate for the benchmark circuits is 100%, and using BPNN, K‐means clustering and SVM and the proposed method, recycled IC or used IC is detected even if it was used for 1 day.

In this letter, a structural analysis attack is explored as the first kind of attack to disclose the secret key of the circuit encrypted by the latest obfuscation technique JANUS‐HD. By extracting the finite state machine (FSM) diagram from the circuit and converting structural traces into constraints, the secret key can be deduced by the CP‐SAT solver within a few minutes or even seconds in most cases. Incorrect keys can be further pruned by sequential equivalence checking with several oracles in case more than one key is obtained. The entire attack procedure lasts no longer than a few hours even for an FSM with 4096 states. [ABSTRACT FROM AUTHOR]

The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub‐micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on‐chip interconnects has been demonstrated. Subsequently, a novel time‐efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through‐silicon‐via (TSV), which is used to connect different dies vertically in a 3D IC. Under high‐frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work. [ABSTRACT FROM AUTHOR]

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel‐metal‐oxide‐semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post‐layout are commensurate with pre‐layout. Post‐layout simulation results show that when temperature changes from − 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from − 78 to −72dB at 1 MHz for 0.2 VPP input signal, −3 dB bandwidth changes from 2.5 to 5 GHz, input‐referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW. [ABSTRACT FROM AUTHOR]

The study discusses selected issues of modelling and designing current‐mode devices. The authors propose the design flow that covers abstract behavioural models, the schematic and SPICE‐level netlists and the post‐layout parasitic parameters. The considerations related to the analogue functional blocks with a dual‐stage complexity. The theoretical backgrounds of the current‐mode basic building blocks are introduced. Special attention has been paid to a new current‐mode active component, digitally programmable modified current differencing transconductance amplifier (MCDTA). Based on the idea of an MCDTA, the authors have developed their own cell, which integrates the digital control feature (programmability) into current‐mode analogue devices. This original solution enables the dual control techniques, coarse digital control and precise analogue control to be used. The presented examples of continuous‐time active filters show that such a solution enables flexibility in the digital control of the parameters of analogue blocks. In order to facilitate the integration of the analogue and mixed‐signal models in a single environment, VHSIC Hardware Description Language ‐ Analogue Mixed Signal (VHDL‐AMS) language was selected for the behavioural modelling methodology. The authors have used the back annotating mechanism to update behavioural models based on an estimation of the post‐layout parameters. The approach is presented on examples that were implemented in TMSC 40 nm complementary metal–oxide–semiconductor technology. [ABSTRACT FROM AUTHOR]

This study presents two configurations to realise the behaviour of a floating memristor and an inverse memristor. The modified version of VDCC (voltage differencing current conveyor) termed as MVDCC (modified VDCC) is used to develop the presented emulators. The floating memristor emulator uses a single MVDCC and two grounded passive elements while the configuration of floating inverse memristor emulator is based on two MVDCCs, two grounded resistances and single grounded capacitance. The behaviour of both the circuits can be controlled through applied bias voltage as well as the employed grounded resistances. Both the presented circuits do not employ any external analogue multiplier circuit/IC, which can be considered as the most notable feature of these circuits. This study also describes the mathematical properties of memristor and inverse memristor taking both symmetrical and non‐symmetrical models into account. PSPICE simulation tool is used to verify the working of realised emulation circuits using 0.18 μm CMOS process technology. The implementations of realised emulators, employing commercial ICs like AD844, CA3080 and LM13700, have also been presented and validated. [ABSTRACT FROM AUTHOR]

This study reports an analysis of noise figures (NFs) in a reflection‐type microwave amplifier using resonant tunnelling diodes (RTDs). The minimum NF for the RTD amplifier based on 0.9 μm InP process technology, featuring a power gain (S21) of 10.4 dB and a dc‐power consumption of 133 μW at a centre frequency of 5.7 GHz, is measured to be 5.08 dB at a bias voltage of 0.355 V. The estimated NF characteristic based on an equation of the noise factor caused by the shot noise (FSH) and a simulation of the noise factor generated by the thermal noise (FTH) closely matches the measured NF characteristic, in the high‐gain bias range of 0.32–0.38 V and near the centre frequency. It is found that the measured NF value of 5.08 dB originates mostly from the FSH of 1.88 and the FTH of 2.02. Additionally, the effect of the RTD parameters on the achieved NF is investigated, indicating that the negative resistance (RD) magnitude had a dominant effect on the NF by changing the FTH as well as the FSH. [ABSTRACT FROM AUTHOR]

This study introduces a new approach for realising a sinusoidal oscillator with three outputs, using an active‐resistor‐capacitor (RC) approach. Using the proposed approach, a new circuit employing three current feedback operational amplifiers and passive components is further introduced. The circuit employs two grounded capacitors and four resistors, out of which one is grounded. The new circuit based on the proposed generalised approach is relatively insensitive to the parasitic effects of active elements, and easy to design, by way of non‐interaction of frequency and condition of oscillations. The proposed approach and the new proposed circuit provide three outputs, two of which are at low impedance nodes. The proposed generalised approach and the new circuit are verified through simulation and experimental results, using commercially available AD‐844s integrated circuits and passive components. Thus, the work advances the existing knowledge on the active‐RC oscillator design. [ABSTRACT FROM AUTHOR]

Electronic enclosures often require ventilation and electromagnetic shielding, which have conflicting design requirements. This study proposes a hybrid model, based on circuit model and full‐wave method, for estimating the shielding effectiveness of empty metallic enclosures with ventilation apertures of arbitrary shape or aperture arrays of arbitrary distribution on one side of the enclosures. Such perforated enclosures are split into a perforated plate and semi‐enclosed waveguide that is shorted at the end. The S parameters of the perforated plate are calculated by a full‐wave method and used to estimate the aperture impedance. An equivalent circuit model of a perforated enclosure is established, considering arbitrarily‐positioned apertures, arbitrarily‐chosen observation points, and higher‐order modes. A modified plane wave decomposition technique is adopted to solve the problem of plane waves with arbitrary incident and polarisation directions. In particular, the effects of the electric field components perpendicular to the perforated plate are considered. The efficiency and accuracy of the hybrid model are evaluated by the transmission line matrix method, finite integration technique, experimental observations and existing circuit models. The hybrid model requires much less simulation time than pure full‐wave methods such as the transmission line matrix method. [ABSTRACT FROM AUTHOR]

This article presents a review of physical, analytical, and compact models for oxide-based RRAM devices. An analysis of how the electrical, physical, and thermal parameters affect resistive switching and the different current conduction mechanisms that exist in the models is performed. Two different physical mechanisms that drive resistive switching; drift diffusion and redox which are widely adopted in models are studied. As for the current conduction mechanisms adopted in the models, Schottky and generalised hopping mechanisms are investigated. It is shown that resistive switching is strongly influenced by the electric field and temperature, while the current conduction is weakly dependent on the temperature. The resistive switching and current conduction mechanisms in RRAMs are highly dependent on the geometry of the conductive filament (CF). 2D and 3D models which incorporate the rupture/formation of the CF together with the variation of the filament radius present accurate resistive switching behaviour.

Cryogenic characterisation and modelling of 0.18μm CMOS technology (1.8 and 5 V) is presented in this Letter. Several P‐type MOS and N‐type MOS transistors with different width to length ratios were extensively characterised under various bias conditions at temperatures ranging from 300 K down to 4.2 K. The authors extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. A simple subcircuit was built to correct the kink effect. The RMS error of test results and modelling results is <3%. [ABSTRACT FROM AUTHOR]

This article presents a review of physical, analytical, and compact models for oxide-based RRAM devices. An analysis of how the electrical, physical, and thermal parameters affect resistive switching and the different current conduction mechanisms that exist in the models is performed. Two different physical mechanisms that drive resistive switching; drift diffusion and redox which are widely adopted in models are studied. As for the current conduction mechanisms adopted in the models, Schottky and generalised hopping mechanisms are investigated. It is shown that resistive switching is strongly influenced by the electric field and temperature, while the current conduction is weakly dependent on the temperature. The resistive switching and current conduction mechanisms in RRAMs are highly dependent on the geometry of the conductive filament (CF). 2D and 3D models which incorporate the rupture/formation of the CF together with the variation of the filament radius present accurate resistive switching behaviour. [ABSTRACT FROM AUTHOR]

Cell signalling plays a vital role in development, sustaining, differentiation, and reproduction of cells. Pathways involved in signalling networks are quite interwoven and complex. Complexity encountered in understanding these pathways is often reduced with the help of Boolean circuit representation. In this study, the authors provide communication aspect of the signalling pathways that have two input Boolean logic AND/OR implemented at the rear effector protein. Communication is assumed to be taking place in extracellular and intracellular environment. The two environments are connected using a receptor protein acting as relay between a molecular source and effector protein. Each relay detects molecules from outside environment and stimulates the production of signals in the intracellular space. These signals/molecules further activate the effector protein which acts as a Boolean switch driven by AND/OR logic. Assuming Poisson reception at the relay as well as at the receiver, the authors provide probability of error of the AND and OR Boolean logic communication systems. Furthermore, reliability and some capacity bounds are deduced for the given Boolean communication system. [ABSTRACT FROM AUTHOR]

Some neurons like neocortical pyramidal neurons adapt with multiple time‐scales, which is consistent with fractional‐order differentiation. The fractional‐order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer‐order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer‐ and fractional‐order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low‐voltage and low‐power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal‐oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional‐order and integer‐order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software. [ABSTRACT FROM AUTHOR]

Optimal design of digital rational approximations with α‐dependant coefficients to model the fractional order integrator of any arbitrary order α, where α ε (0, 1), is presented in this work. The analytical expressions of the coefficients for the proposed fractional order digital integrators (FODIs) are derived by a two‐step method: (a) the coefficients of FODIs for α varying from 0.01 to 0.99 in steps of 0.01 are determined by a meta‐heuristic optimisation algorithm called symbiotic organisms search (SOS) and (b) curve fitting is applied on the SOS‐optimised coefficients to obtain their generalised expressions. Previous works dealing with the design of FODI based on various meta‐heuristic optimisers have considered only a few specific fractional orders; hence, the practical usability of such designs is restricted. This gap provides the motivation for conducting this research. Design quality robustness and convergence consistency of SOS are extensively compared with three other well‐known meta‐heuristic algorithms. The superior modelling accuracy of the proposed designs is justified by comparing with the recent literature. Simulation results validate the effectiveness of the proposed models as a fractional order proportional–integral controller. [ABSTRACT FROM AUTHOR]

Implementation of basic ternary logic gates is more complex than binary gates in quantum‐dot cellular automata (QCA) technology. Several models have been presented for designing ternary logic gates. Most of these models are different solutions and are based on manual calculations. It seems that no simulation tool for designing ternary QCA (tQCA) logic gates has been presented. Unlike previous works, this study is an attempt to introduce an alternative model and the related software for tQCA logic gates. Prominent basic ternary logic gates – such as Min gate, Max gate and inverter – are proposed and simulated in the newly designed TQCAsim software which is an accurate simulation and design tool and is based on the algorithm proposed in this study. Unlike QCA designer software, which has been designed for binary QCA, TQCAsim is designed exclusively for tQCA. Thus, this software can be used to verify and implement the proposed tQCA gates and even earlier designs. [ABSTRACT FROM AUTHOR]

This study proposed an application of symbolic technique on the characterisation of a ring voltage controlled oscillator (VCO) for optimum performance. Here nullor‐based symbolic noise modelling and analysis of the CMOS ring VCO is carried out. Circuit equations are processed through modelling of all the metal–oxide–semiconductor field‐effect transistors with their nullor equivalent. The closed‐form expressions for the total output noise density and phase noise of VCO are obtained. With this technique, the total output noise density and phase noise calculated are compared with the results obtained from the transistor‐level simulation. From the comparison, it has been observed that the nullor‐based modelling and analysis simplifies the noise expression as well as reduces CPU execution time. The performance enhancement of the VCO is carried out using two different optimisation techniques. These are particle swam optimisation and non‐dominated sorting genetic algorithm. The results obtained for the optimised VCO are then tested using SPICE. The SPICE result shows a significant improvement in phase noise, power consumption and tuning range for the optimised VCO. [ABSTRACT FROM AUTHOR]

In this work, performance of dielectric inserted side contact multilayer graphene nanoribbon (Di‐side‐GNR) coupled interconnects using unconditionally stable finite‐difference time‐domain (USFDTD) technique has been investigated. The model developed for the same, overcomes the limitation of Courant stability criterion prevalent in the conventional finite‐difference time‐domain (FDTD) technique. The proposed model accurately analyses the crosstalk effect in copper (Cu), side contact multilayer graphene nanoribbon and Di‐side‐GNR interconnects. It is found that the crosstalk effect is least in Di‐side‐GNR amongst the three types of interconnect considered in this study. The proposed model and HSPICE simulation results match closely. Further, for transient analysis USFDTD technique based proposed model takes nearly 1.5 times lesser CPU runtime compared to the conventional FDTD technique. [ABSTRACT FROM AUTHOR]

This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high‐speed data links. A new modelling technique, with several important advantages is described. All the requirements of black‐box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this study provides a straightforward solution to modelling the input–output behaviour. Good model performance in overclocking conditions is an important advantage. This study also investigates the possibility of accounting for power‐supply voltage variations and provides a simple solution. [ABSTRACT FROM AUTHOR]

A semi‐passive charge‐sharing complex bandpass filter employing positive feedback technique is proposed to control bandwidth at different centre frequencies. In contrast to the previous arts, bandwidth can be changed independent of centre frequency without any rise in the number of clock phases and switches. Also, insightful continuous‐time model and block diagram of the proposed filter have been presented. The results of simulation carried out with 0.18 µm CMOS technology at 200 MHz reference frequency for centre frequencies of 10 and 20 MHz and bandwidth of 1, 3 and 7 MHz indicate the filter's ability to control the quality factor excellently. [ABSTRACT FROM AUTHOR]

On‐orbit processors generally require reinforcement due to the harsh space radiation environment. Although the traditional full triple modular redundancy (TMR) method can effectively reinforce circuits, it requires excessive physical footprints and energy consumptions. To address this problem, this Letter proposes a general partial TMR method that can effectively reinforce a circuit. The method is based on the PageRank algorithm for sorting the importance of the triggers in a circuit, and the mean time between failure based on the dual logic cone model is used as the criterion to determine triggers that require redundancy under the partial TMR method. The arithmetic module of an optical image processing platform is tested to verify the effectiveness of the partial TMR method proposed in this Letter. [ABSTRACT FROM AUTHOR]

This paper presents a new time‐efficient modelling approach for UHF Dickson rectifiers. Due to the very low computation time, the approach can provide a quick and effective alternative to the standard transient simulations. The presented approach results in better estimation of the generated DC voltage and power conversion efficiency compared with the similar works in the literature. For the first time, an accurate mathematical relationship, including the non‐zero reverse current, is expressed for finding the open load voltage of the Dickson rectifier while covering the broad range of RF amplitudes. The model uses the relation between the peak forward current and the load current to develop an input‐to‐output formula. Unlike the previous works, the channel length modulation is taken into consideration for the first time making the proposed model ideal for UHF Dickson rectifiers implemented with submicron CMOS transistors. Moreover, the proposed model takes secondary effects, such as the body effect and short‐channel effects into account resulting in a more accurate estimation of the generated output DC voltage. Using the presented approach, a Dickson rectifier working at 900 MHz is implemented in a 0.18 µm CMOS process. Good agreement between simulation results, predicted results, and measurement results is observed. [ABSTRACT FROM AUTHOR]

The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system‐on‐chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on‐chip power net by combining vector network analyser measurements with an on‐chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst‐case condition of 1.2 V. [ABSTRACT FROM AUTHOR]

This study presents a novel approach to estimate the maximum power point (MPP) of a photovoltaic (PV) array on an hourly basis using meteorological data. The estimation of MPP of a PV array based on its characteristic equation is done by using Levenberg–Marquardt (LM) method. The monthly averaged daily and hourly global solar irradiation during sunshine hours of Guwahati city is estimated by taking relative humidity and ambient temperature data using empirical relations. The actual and estimated maximum powers of a PV array of monthly averaged daily and hourly basis is calculated using MATLAB. It is demonstrated that each of the estimated maximum power of a PV array on an hourly basis is nearly equal to each of the actual maximum power. The MPP of a PV module estimated by the LM method is validated with the actual and experimental results. A comparative study of MPP of a PV module estimated from the proposed method with perturb‐and‐observe based on proportional–integral, genetic algorithm and Gauss–Seidel is performed. The performance of the proposed algorithm for estimation of MPP of a PV array ensures the accuracy and faster convergence. [ABSTRACT FROM AUTHOR]

This paper presents a successive approximation register analog-to-digital converter (SAR-ADC) design optimization platform. A novel ADC modeling approach, design partitioning method (DPM), is used in the proposed platform. It uses lookup tables along with conventional behavioral modeling technique, which captures the design parameters and process nonidealities. An individualistic as well as collective study of the impact of these parameters and nonidealities on the performance of SAR-ADC has been carried out. The proposed platform aims to achieve a perfect balance between architecture evaluation time (3.2% with respect to SPICE netlist) and accuracy in performance estimation (98% with respect to SPICE netlist). A comparative study between SPICE model, structural modeling, and the proposed modeling scheme (DPM) is reported here. As a case study, a 14-bit, 4.2MSPS SAR-ADC architecture is evaluated, designed, and verified. [ABSTRACT FROM PUBLISHER]

A complementary passive mixer with feedback followed gate bias generation scheme is proposed. The gate voltage of the switches follows the common‐mode voltage (VCM) of the signal paths, so that the proposed mixer achieves constant switching gate‐to‐source bias voltage and coherent performances while VCM changes over a certain range. Furthermore, a dc offset cancelation method based on the bias generation circuit is proposed. The dc component of the intermediate frequency is feedbacked to the bias generation input to form a cancelation path. A behavioural model is deduced to prove the effect of the offset cancelation and second intercept point (IIP2) improvement. The proposed mixer is implemented in a 0.13 μm CMOS process, and measurement results show that robust performance with the VCM range of 0.5–0.7 V and 16 dB IIP2 improvement are obtained. [ABSTRACT FROM AUTHOR]

Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solutions in current nanoscale VLSI interconnects. From fabrication point of view, it is difficult to control the growth of a densely packed bundle having MWCNTs with similar diameters. A realistic bundle is combination of MWCNTs with different number of shells. Thus, this research work focuses on the analytical model of a bundle having the MWCNTs with different number of shells or in turn different diameters [mixed MWCNT bundle (MMB)]. Based on the multi-conductor transmission line theory, an equivalent single conductor (ESC) model is employed for the proposed MMB arrangements. The ESC model of MMB is used to compare the dynamic crosstalk delay with conventionally arranged bundle containing MWCNTs with similar diameters [MWCNT bundle (MB)] under different input transition time and spacing conditions. It is observed that a realistic MMB correctly estimates the crosstalk delay for the different transition time that overestimates the delay of a conventionally arranged MB by 1.35 times. Moreover, the MMB arrangement reduces the overall crosstalk delay by 47.26% compared with the conventional MB arrangements for an inter-bundle spacing ranging from 5 to 30 nm.

This paper proposes a technique to accurately estimate radio frequency behaviour of low-power 90 nm amplifier circuits with geometry scalable discrete complementary metal oxide semiconductor (CMOS) modelling. Rather than characterising individual elements, the scheme is able to predict gain, noise and reflection loss of low-noise amplifier (LNA) architectures made with bias, active and passive components. It reduces number of model parameters by formulating dependent functions in symmetric distributed modelling and shows that simple fitting factors can account for extraneous (interconnect) effects in LNA structure. Equivalent-circuit model equations based on physical structure and describing layout parasites are developed for major amplifier elements like metal–insulator–metal (MIM) capacitor, spiral symmetric inductor, polysilicon (PS) resistor and bulk RF transistor. The models are geometry scalable with respect to feature dimensions, i.e. MIM/PS width and length, outer-dimension/turns of planar inductor and channel-width/fingers of active device. Results obtained with the CMOS models are compared against measured literature data for two 1.2 V amplifier circuits where prediction accuracy for RF parameters (S(21), noise figure, S(11), S(22)) lies within the range of 92–99%.

This investigation describes novel automatic test equipment for verifying the electric contact of radio frequency (RF) traces between RF devices by, for example, the opens and shorts test. An equivalent circuit for modelling the RF device incorporating RF traces with contact impedance is applied for theoretical analysis of the prototype design. The effectiveness of the proposed novel test methodology is then validated. The measured data from experimental testing of RF devices attained in production runs precisely address the contact issue using the novel methodology presented here. [ABSTRACT FROM AUTHOR]

This study presents a full methodological approach to designing and verifying differential sample and hold switched‐capacitor circuits generally used in analogue‐to‐digital converters (ADCs). It provides a step‐by‐step process for translating system requirements such as signal‐to‐noise ratio and sampling frequency into ADC requirements and subsequently into operational amplifier topology and specifications. It also includes the design process of a switched‐capacitor common mode feedback circuit to control the common mode output voltage. Furthermore, this study discusses the noise aspects of the switched‐capacitor circuits. It also provides practical methods for verifying the stability of the system by using step voltage and step current techniques. A design and simulation example for a differential sample and hold switched‐capacitor circuit operating in a system requiring a 5 MHz sampling frequency and a 6‐bit ADC is provided. Mentor Graphics CAD tools were used in the design and the simulations process by using 180 nm complementary metal oxide semiconductors (CMOS) device models. This study can be used as a resource for the design engineers in the industry as well as the universities teaching graduate level advanced electronics and data converter courses. [ABSTRACT FROM AUTHOR]

A method that aims at analyzing the dynamic behavior of some two-phase switched-capacitor charge pump circuits is proposed. A recurrence relation on the voltages across the charging capacitors of a given two-phase charge pump circuit is developed. The output voltage and the accumulated charge of a charge pump circuit after any clock cycle were found by solving some basic matrix equations, with a specific loading current and some required initial conditions. The validation of the proposed method was done by SPICE simulations based on a 8 × linear, Fibonacci, and an exponential charge pump. The analysis results were also verified with the simulation results obtained from some charge pump circuits designed with the 0.18 μm CMOS process. Results show that the proposed method can yield a close estimation on the dynamic behavior of a charge pump circuit in most of the designs. We further found that the rising times for the exponential and Fibonacci charge pumps are shorter, especially when the conversion ratio is high, than that of the linear one. [ABSTRACT FROM AUTHOR]

Continuous and aggressive scaling of semiconductor technology has led to persistent and dominant nanoscale effects on analogue/mixed‐signal (AMS) circuits. Design space exploration and optimisation costs using conventional techniques have increased to infeasible levels. Hence, growing research for alternative design and metamodelling techniques with a much reduced design space exploration and optimisation cost and high level of accuracy, continues to be very active. This study presents a geostatistical inspired metamodelling and optimisation technique for fast and accurate design optimisation of nano‐complementary metal oxide semiconductor (CMOS) circuits. The design methodology proposed integrates a simple Kriging technique with efficient and accurate prediction characteristics as the metamodel generation technique. A gravitational search algorithm (GSA) is applied on the generated metamodel (substituted for the circuit netlist) to solve the design optimisation problem. The proposed methodology is applicable to AMS circuits and systems. Its effectiveness is illustrated with the optimisation of a 45 nm CMOS thermal sensor. With six design parameters, the design optimisation time for the thermal sensor is decreased by 90% and produces an improvement of 36.8% in power consumption. To the best of the authors' knowledge this is the first work to use GSA for analogue design optimisation. [ABSTRACT FROM AUTHOR]

Defining a power management solution for a system‐on‐chip imposes the design of a low power architecture composed of multiple power domains and a power management strategy for power domain state control. If these two elements are energy‐efficient, an energy‐efficient power management solution can be obtained. Transaction‐level of modelling allows a rapid exploration of different power management solutions, hence a fast decision‐making of the most energy‐efficient one. The authors' previous work proposed an abstraction of the unified power format (UPF) standard semantics to enable fast evaluation of different UPF‐like power architectures at transaction‐level (TL). However, a fast evaluation of different power domain management strategies requires a unique and flexible hardware interface to organise transfers of inter‐power‐domain transactions according to a well‐defined protocol. The proposal of a new hardware protocol interface for power domain state management, called power domain management interface (PDMgIF), and its TL simulation model represents the main contribution of this study. This proposal separates functional and power management communications. It represents a potential extension of existing low power standards (such as UPF) that already miss power domain management semantics.The PDMgIF concepts are demonstrated through an audio application TL platform illustrating a high flexibility and reduced overhead of the TL PDMgIF model. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage on-chip oscillator which can compensate process, voltage, and temperature (PVT) variation in an all-digital manner. The relative reference modeling applies a pair of ring oscillators as relative references and estimates period of the internal ring oscillator. The period estimation is parameterized by a second-order polynomial. Accordingly, the oscillator compensates frequency variations in a frequency division fashion. A 1-20 MHz adjustable oscillator is implemented in a 90-nm CMOS technology with 0.04 mm area. The fabricated chips are robust to variations of supply voltage from 0.9 to 1.1 V and temperature range from 0°C to 75°C. The low supply voltage and the small area make it suitable for low-cost and low-power systems. [ABSTRACT FROM AUTHOR]

This paper proposes a general circuit model and design method for resonant gate drivers. Topologies in the literature are analyzed by dividing each switching transient into up to five energy transfer stages, for which general analytical equations are derived. A general resonant gate driver circuit model is presented. Several reviewed topologies are identified as unique combinations of current paths within this circuit model, providing a basis for classification. This establishes a relationship between topology performance and architecture, which is verified experimentally using a reconfigurable test circuit. [ABSTRACT FROM AUTHOR]

It is demonstrated, using the example of a T‐junction, that not every multiport structure can be accurately described by a discrete and separated modelling approach at millimetre and sub‐millimetre wavelengths. It is shown that especially stub‐networks, which are typically used in RF‐matching networks, are affected. In this case, the discrete modelling approach predicts a different resonance frequency than the S‐parameter measurement as well as the 3D electromagnetic field simulation (3D‐EMFS) of the whole structure. However, these resonances are of particular importance for the design of a RF matching network and should be predicted by the model as precisely as possible. Therefore, the reason for the mismatch by accurate 3D‐EMFS is investigated and a possible solution on how to model the so‐called complex interactions in passive multiport structures at millimetre and sub‐millimetre wavelengths is provided. [ABSTRACT FROM AUTHOR]

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 muA and 0.7 muA drain currents, 14 muA/V and 8 muA/V transconductances, 400 kOmega and 1.1 MOmega output resistances, 36 THz and 25 THz unity-current-gain cutoff frequencies, and 120 THz and 100 THz maximum frequency of oscillations, respectively. A single-stage CMOS SGFET amplifier dissipates 1.64 muW power and provides 500 GHz bandwidth with -6.5 gain and -24 dBm third-order intermodulation distortion tones for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The large-signal operation of the amplifier with 1 V output swing exhibits 2.2 ps delay, 5.4 ps rise time, and 4.7 ps fall time while oscillating at 30 GHz. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next-generation very-large-scale integration (VLSI) technology. [ABSTRACT FROM PUBLISHER]

As feature size goes below 70 nm, process variation introduced device mismatch may cause over 40% performance variations and circuit failures especially for analog/mixed-signal designs. The location dependent correlations among devices and the large number of devices in some practical designs make it difficult to predict performance corners accurately and efficiently. This paper aims to provide an overview of possible methodologies and approaches that model and analyze device mismatch. In particular, the paper describes a new finite point device modeling technique that can speed up the analysis procedure, a new parametric reduction method and a novel Chebyshev Affine Arithmetic (CAA) based performance bound estimation approach. [ABSTRACT FROM PUBLISHER]

Bump shear is widely used to characterize the interfacial strength of Cu/low-k structures. In this paper, the blanket low-k structure was used to evaluate the reliability and strength of Cu/low-k structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-k interfaces with different low-k structures, to understand the failure mechanism, and to improve low-k structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-k structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-k structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-k structure. An Sn-Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low-k structure reliability. [ABSTRACT FROM PUBLISHER]

Advances in the microelectronic design implicate a reduction of device dimensions requiring a better understanding of the microscopic processes involved. One of these processes concern charging and discharging of defects via tunneling, which is supposed to constitute a grave contribution to various ongoing reliability issues. A deep understanding and a correct modeling of this mechanism are of utmost importance in this context. Conventionally, tunneling levels are believed to remain at fixed positions within the oxide bandgap regardless whether they are occupied or not. From a theoretical point of view, defect energy levels undergo shifts within the silicon dioxide bandgap after charging or discharging. As a result, defect levels for tunneling into and out of traps have to be distinguished. Based on this understanding of trapping, defects can be characterized as fixed charges, switching oxide charges, interface traps, or other types of defects. In this study, we conduct first-principle investigations on the energetics for a series of individual defects encountered in the context of reliability. In order to deduce their tunneling dynamics, a new model, which accounts for the effects of shifting tunneling levels, has been established. On the basis of the E gamma ' center, the main discrepancies between the model relying on trap level shifts and the model with coinciding trap levels have been highlighted. [ABSTRACT FROM PUBLISHER]

It is now well established that the negative bias temperature instability (NBTI) mechanism alters both the mean and variance of the distribution of the PFET under stress. This effect has reliability implications to balanced analog circuits (e.g., current mirrors, differential pairs, etc.), as well as to SRAM cell stability. This paper presents a brief review of the understanding and models to date of the statistics and impacts of the NBTI-induced variation. This is followed by a critical examination of the actual NBTI-induced distributions and the accuracy of the normal approximations that have been used to date. [ABSTRACT FROM PUBLISHER]

This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit off currents under 1 pA while producing highest on currents. DC characteristics of the optimum n and p-channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2- and 3-input nand, nor, and xor gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 mum2 [ABSTRACT FROM PUBLISHER]

Carbon nanotubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, issues associated with crosstalk among bus lines implemented by CNTs are investigated in detail. CNT-based interconnects are modeled and the effects of crosstalk on performance and correct operation are evaluated by simulation. Existing models are modified to account for geometries in bus architectures made of parallel single-walled nanotubes and a single multiwalled nanotube. New RLC equivalent circuits are proposed for these bus architectures. A novel bus architecture with low crosstalk features is also proposed. This bus architecture is made of dual-walled nanotubes arranged in parallel. In this architecture, the crosstalk-induced delay and corresponding uncertainty (as well as crosstalk-induced peak voltage) are significantly reduced; a modest area penalty is incurred. Reductions up to 59% for the crosstalk-induced delay and up to 81% for the crosstalk-induced peak voltage are reported. These results confirm that the proposed bus arrangement noticeably improves performance and provides reliable operation [ABSTRACT FROM PUBLISHER]

Noise parameter measurements of submicrometer scaled-CMOS devices are error prone. These errors can propagate to a device model affecting the performance of low-noise amplifiers (LNAs) designed with them. In this paper, measurement errors in noise parameters of submicrometer scaled-CMOS devices are quantified. The sensitivity of different noise parameters to measurement and modeling errors is examined, showing that some parameters (NFmin,Rn) are more immune to such errors than others (Gopt,Bopt). We propose a modeling and design approach (desensitization by Rn-optimization) that can greatly alleviate the impact of such errors on the noise figure of LNAs. Measured results from a 90-nm LNA show substantial (ges 2.5 dB) improvement in its noise figure as a result of desensitization [ABSTRACT FROM PUBLISHER]