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This article presents a multilayer graphene nanoribbon (MLGNR)‐based single‐tier on‐chip nanoscale via‐interconnect scheme (VIS), which combines the vertical MLGNR via and horizontal MLGNR interconnect, as a prospect for monolithic 3D (M‐3D) integrated circuits (ICs). To go beyond the simplifying assumptions of perfect MLGNR and conventional skin‐effect, this study incorporates the impact of edge‐ and substrate‐induced scatterers in a realistic MLGNR and considers the 1D skin depth formula for MLGNR‐based on‐chip interconnect and via. A combined equivalent circuit model is developed to analyze the challenges induced by scatterers, skin‐effect, and crosstalk effect in perfect MLGNR VIS (P‐VIS) and realistic MLGNR VIS (R‐VIS). The results show that for width in the range of 5–30 nm, P‐VIS outperforms R‐VIS in terms of crosstalk delay. Moreover, at high frequencies ranging from 1 to 104 GHz with a width of 16 nm, R‐VIS demonstrates a performance decline of 243.18% (5.3934 × 103%) for L = 4.8 μm (1 mm), respectively, in comparison with P‐VIS. Hence, in order to leverage the potential of MLGNR‐based VIS for M‐3D ICs at high frequencies, it is imperative to integrate Li‐intercalation doping and mitigate the impact of edge and substrate scatterers in MLGNR. [ABSTRACT FROM AUTHOR]

Heterogeneous integration on flexible substrates has been explored in recent years to meet the high‐performance and flexible form factors requirements of several emerging applications. Reliable interconnects, in both 2D and 3D layouts, are critical for the effective use of these systems. But it is challenging to employ conventional bonding and interconnect technology due to considerable mismatches in mechanical and thermal properties. For example, the ultra‐thin chips (UTCs) are too fragile to withstand the static or oscillating forces applied during conventional bonding. In this regard, printing of metal tracks on flexible substrates is a promising alternative to access the contact pads on integrated circuits (ICs), as the interconnects on diverse substrates can be realized at room temperature processing using as much materials as needed. Further, it is easier to attain step coverage. Considering the above attractive features, and the challenges associated with conventional bonding techniques, this article focuses on the development of high‐resolution printing interconnects in both 2D and 3D layouts and explores various printing routes available for high density integration. The article also discusses major conventional interposers/interconnects forming methods and their limitations for flexible hybrid electronics along with few examples of printed interconnects to highlight the opportunities for future. [ABSTRACT FROM AUTHOR]

The electrophoretic deposition of a mixture of copper-manganese spinel oxide matrix with perovskite oxide dispersion phase and subsequent two-step sintering was investigated as a means of obtaining a new spinel/perovskite composite coating for application in metallic interconnects for solid oxide cell (SOC) technologies. The effect of a number of factors was examined, including electrophoretic deposition parameters such as solvent type, time, voltage, and dispersant content as well as different heat treatment conditions on the quality of the matrix of the coating material. A solution of ethanol-acetone (25/75 v/v) and 2.0 g L−1 of iodine dispersant with a deposition time of 60 s and a voltage of 60 V provided the thickest, most uniform coating as deposited. SEM observations showed that a dense coating of Cu–Mn spinel was obtained after 8 h of reduction at 1000 °C followed by 6 h of oxidation at 850 °C. Selected preparation parameters were applied to deposit composite coatings with a Cu–Mn spinel matrix and the addition of LNF, LSC and LSCF perovskites. [Display omitted] • EOH25/75ACT was determined to be the most suitable mixture for the deposition. • Mass gain of the deposit generally correlates with particle mobility. • Reduction in Ar–10%H 2 at 1000 °C and re-synthesis in air at 850 °C is optimal. • Morphology of composite coatings depend on type of perovskite additive. [ABSTRACT FROM AUTHOR]

Flexible hybrid electronics (FHE) is an emerging area that combines printed electronics and ultra‐thin chip (UTC) technology to deliver high performance needed in applications such as wearables, robotics, and internet‐of‐things etc. The integration of UTCs on flexible substrates and the access to devices on them requires high resolution interconnects, which is a challenging task as thermal and mechanical mismatches do not allow conventional bonding methods to work. To address this challenge, the resource‐efficient, area‐efficient, and low‐cost printing routes for obtaining vertical interconnection accesses (VIAs) are demonstrated here. It is demonstrated how high‐resolution printers (electrohydrodynamic and extrusion‐based direct‐ink writing printers) can be used for patterning of high‐resolution, freeform, vertical conductive structures. To access the transistors on UTCs, the VIAs, obtained using conventional photolithography and plasma etching steps, are filled with conductive silver nanoparticle‐based ink/paste using high‐resolution printers. Comprehensive studies are performed to compare and benchmark in terms of: i) the printing speed and throughput of the printers, ii) the electrical performance of vertically connected transistors in UTCs, and iii) the electrical performance stability of FHE system (interconnects and UTCs) under mechanical bending conditions. This in‐depth study shows the potential use of printing technologies for development of high‐density 3D integrated FHE systems. [ABSTRACT FROM AUTHOR]

Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated circuits. Metal interconnects in their current form struggle to follow the size downscaling due to materials limitations at the nanoscale, causing severe performance losses. Next‐generation interconnects need new materials, and molybdenum (Mo) is considered the best choice, offering low resistivity, good scalability, and barrierless integration at a low cost. However, it requires annealing at temperatures far exceeding the currently accepted limit. In this work, the challenges of high‐temperature annealing of patterned Mo nanowires are looked into, and a new approach is presented to overcome them. It is demonstrated that while a conventional annealing process improves the average grain size, it can also reduce the cross‐section area, thus increasing the resistivity. Using high‐resolution transmission electron microscopy (TEM) with in situ heating, the evolution of structural features in real time is directly observed. Using insights from these experiments, a cyclic pulsed annealing method is developed, and it is shown that the desired grain structure is achieved in only a few seconds, without forming the surface grooves. These findings can radically facilitate Mo integration, boosting the efficiency of future integrated circuits. [ABSTRACT FROM AUTHOR]

This study reports the effects of post-annealing on the electrical reliability of a NiAl/SiO2 interconnect structure for potential use as post-Cu interconnect. Our materials characterization using transmission electron microscopy and secondary ion mass spectrometry discloses that annealing at elevated temperatures induced the diffusion of Al into SiO2: Al, for a 400 °C-annealed sample, diffused only to a few nanometers from the interface, forming a thin aluminum-rich oxide layer, while samples annealed at higher temperatures show an extensive Al diffusion and interfacial reactions. In a voltage ramp dielectric breakdown test, the 400 °C annealed sample shows the lowest breakdown voltage, possibly, due to the aluminum-rich oxide layer serving as a self-forming barrier while the samples annealed at higher temperatures display a drastic reliability degradation with the annealing temperature increasing. In addition, analyzing data acquired from time-dependent dielectric breakdown tests using the E-model helps us predict the lifetime of the 400 °C sample to be longer than 105 h at 1 MV/cm.

The high-temperature stability of RuAl-based electrodes for application in microelectronic devices is analyzed for long-term duration. The electrodes are prepared on Ca3TaGa3Si2O14 (CTGS) substrates using SiO2 and Al-N-O cover and barrier layers as oxidation protection. The samples are annealed at 600, 700, or 800 °C in air for 192 h. Minor degradation is observed after thermal loading at 700 °C. The annealing at 800 °C for 192 h leads to a partial oxidation of the Al in the extended contact pad and to a complete oxidation of the Al within the structured interconnect electrodes. The different degradation of the interconnect electrodes and the contact pads is caused by their different lateral dimensions. In summary, long-term high-temperature stability is demonstrated up to at least 700 °C in air. Less oxidizing atmospheres should allow the application at higher temperatures and for a significantly longer duration. [ABSTRACT FROM AUTHOR]

Abstract Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated circuits. Metal interconnects in their current form struggle to follow the size downscaling due to materials limitations at the nanoscale, causing severe performance losses. Next‐generation interconnects need new materials, and molybdenum (Mo) is considered the best choice, offering low resistivity, good scalability, and barrierless integration at a low cost. However, it requires annealing at temperatures far exceeding the currently accepted limit. In this work, the challenges of high‐temperature annealing of patterned Mo nanowires are looked into, and a new approach is presented to overcome them. It is demonstrated that while a conventional annealing process improves the average grain size, it can also reduce the cross‐section area, thus increasing the resistivity. Using high‐resolution transmission electron microscopy (TEM) with in situ heating, the evolution of structural features in real time is directly observed. Using insights from these experiments, a cyclic pulsed annealing method is developed, and it is shown that the desired grain structure is achieved in only a few seconds, without forming the surface grooves. These findings can radically facilitate Mo integration, boosting the efficiency of future integrated circuits.

In the realm of parallel and distributed computation, All-gather operation, a process where each node in a distributed system gathers data from all others, is pivotal. This operation underpins various high-performance computing (HPC) applications, notably in distributed deep learning (DL), by enabling model and hybrid parallelisms. Although optical interconnection networks promise unmatched bandwidth and reliability for data transfers between distributed nodes, most current All-gather algorithms remain optimized for electrical interconnects, leading to suboptimal performance in optical contexts. This paper proposes “OpTree”, an advanced scheme distinctly designed for All-gather operation in optical interconnect systems. OpTree constructs an optimal $m$ -ary tree that minimizes communication time by determining the optimal number of communication stages. A comprehensive comparison between OpTree’s communication steps and existing All-gather algorithms is provided. Theoretical insights reveal that OpTree substantially curtails communication steps within optical interconnects. Constraints imposed by OpTree on optical communication are also elaborated. Empirical evaluations, through rigorous simulations, establish that: 1) OpTree is effective in generating an optimal m-ary tree for minimizing communication time. 2) For a 1024-node optical ring system, OpTree cuts communication time by 72.97%, 93.15%, and 86.32% against WRHT, Ring, and Neighbor Exchange (NE) schemes, respectively, tested over different message sizes. 3) With varying node counts, the reductions stand at 42.27%, 92.74%, and 85.49% against the same counterparts. 4) As the number of wavelengths increases, communication time further diminishes.

As ICs scale up, a problem that arises at the lower levels of the plating system is that the resistance of the copper traces increases rapidly as the size decreases. This is due to the increase in the contribution of electron scattering on the surface and at grain boundaries. In addition, copper lines require fixed-thickness barrier layers to prevent copper from diffusing into the low-k dielectric. When the cross section of the tracks is reduced, the contribution of the barrier layers to the track resistance is excxii essively high. In addition, when the track width is less than 10 nm, the resistance of copper to electromigration is insufficient. Therefore, it is necessary to look for alternative materials to replace copper, which will provide strong resistance to electromigration and low track resistance. The most promising candidates are Ru, Mo, Rh, and Ir. The advantages and disadvantages of these materials are discussed in this study. [ABSTRACT FROM AUTHOR]

Ruthenium thin films were deposited by plasma enhanced atomic layer deposition (PEALD) using Ru(EtCp)2 and oxygen plasma on the modified silicon surface and SiO2/Si substrates. The substrate temperature has a significant impact on film growth. The GXRD and SIMS analysis have shown that at the substrate temperature T = 375°C there is a sharp change in the mechanisms of surface reactions, which leads to a change in the film composition from RuO2 at low temperatures to a pure Ru film at higher temperatures. This was confirmed by measurements of the electrical resistivity of Ru-based films. The lowest surface roughness ~1.5 nm was obtained at a film thickness of 29 nm deposited at 375°C on a SiO2/Si-substrate. The measured resistivity of the Ru film was 18–19 μΩ cm. Issues regarding the plasma-chemical etching of ruthenium and the spin-on of a low-k dielectric onto arrays of lines are taken into account. [ABSTRACT FROM AUTHOR]

The integration of carbon nanostructures with semiconductor nanowires holds significant potential for energy-efficient integrated circuits. However, achieving precise control over the positioning and stability of these interconnections poses a major challenge. This study presents a method for the controlled growth of carbon nanofibers (CNFs) on vertically aligned indium arsenide (InAs) nanowires. The CNF/InAs hybrid structures, synthesized using chemical vapor deposition (CVD), were successfully produced without compromising the morphology of the pristine nanowires. Under optimized conditions, preferential growth of the carbon nanofibers in the direction perpendicular to the InAs nanowires was observed. Moreover, when the CVD process employed iron as a catalyst, an increased growth rate was achieved. With and without the presence of iron, carbon nanofibers nucleate preferentially on the top of the InAs nanowires, indicating a tip growth mechanism presumably catalysed by a gold-indium alloy that selectively forms in that region. These results represent a compelling example of controlled interconnections between adjacent InAs nanowires formed by carbon fibers. [ABSTRACT FROM AUTHOR]

Plasmonic materials exhibit localized plasmon resonances that collect light and concentrate electric fields around nanostructures. The field enhancements are useful for applications such as spectroscopy, catalysis, and photodetection. Electric field enhancements are dependent on the materials, geometric designs, and positioning of nanostructures. Plasmonic dimers are especially effective to concentrate electric fields between nanostructures, and there is significant interest to develop nanofabrication strategies to control interparticle distances with subnanometer precision for arbitrary designs. In this work, we investigate arrays of interconnected plasmonic dimers with sub-10 nm nanogaps achieved by Cu area-selective atomic layer deposition (ALD). Nanostructures are made by conventional nanofabrication methods and subsequently coated with conformal layers of Cu to control the interparticle distances. Au and Pd layers are used to activate Cu deposition for homodimer and heterodimer combinations with and without interconnects. Optical extinction measurements before and after growth experiments show how plasmon resonances change when Cu layers expand nanostructures and reduce nanogaps formed between dimer pairs. Finite difference time domain simulations are used to model experiments and study how modifications of nanostructure sizes, thicknesses, and shapes affect plasmonic properties. Our findings show that Cu ALD can reduce nanogaps below 10 nm for both interconnected and unconnected nanorods and that interconnected plasmonic dimers have optical properties similar to unconnected dimers. Moreover, the ALD process can scale to large arrays of nanostructures. Results are promising for achieving subnanometer control of interparticle distances for devices that combine electrical and optical functions with intense electric fields generated by localized surface plasmon resonances. [ABSTRACT FROM AUTHOR]

When carbon nanotubes (CNTs) are used in interconnects, their electrical properties are appealing as they are not affected by surface scattering when the feature size decreases. After almost two decades of research on CNT-based interconnects, it is still a question which type of CNT bundle performs better than the other. There are many contradictory reports in this regard. So, it is very important to study the frequency response of these interconnects to ascertain their actual performance and compare them. HSPICE-based circuit simulations at 20 nm and 14 nm technology nodes are carried out. Furthermore, the analysis for local, semi-global and global interconnect lengths is carried out. Results show that single-walled CNT (SWCNT) bundles have higher voltage gain and higher current gain for all lengths at both the technology nodes. These results are significant in understanding the best choice of interconnects among SWCNT bundle, MWCNT bundle and mixed CNT bundle interconnects. [ABSTRACT FROM AUTHOR]

Gallium is one of the most desirable, yet less known, interconnects considered in the semiconductor industry. Good electrical conductivity and high stretchability of the liquid metal makes it very attractive for many applications. It allows components to be assembled or disaggregated like Lego blocks without any external forces or energy. The focus of this article is to shed light on intrinsic reliability degradation mechanisms for components that use liquid metal interconnects. As a starting reference to field reliability risk evaluations, the authors focus on common/controlled use conditions. Environments studied include standard test evaluation procedures like thermal aging (sustained exposure to high temperature over time), thermal cycling, current carrying capability, and finally functional product life cycle testing. Studies reveal that the interconnect has very distinct failure mechanisms and unique advantageous/disadvantageous over existing interconnects. Fundamental knowledge gained in this study is expected to help 1) drive future architectures, 2) material/design changes to address any limitations, and 3) finally new qualification methods/standards that account for the unique failure mechanisms. [ABSTRACT FROM AUTHOR]

With the continuous shrinkage of integrated circuit (IC) dimensions, traditional copper interconnect technology is gradually unable to meet the requirements for performance improvement. Carbon nanotubes have gained widespread attention and research as a potential alternative to copper, due to their excellent electrical and mechanical properties. Among various methods for producing carbon nanotubes, chemical vapor deposition (CVD) has the advantages of mild reaction conditions, low cost, and simple reaction operations, making it the most promising approach to achieve compatibility with integrated circuit manufacturing processes. Combined with through silicon via (TSV), direct application of CVD-grown carbon nanotubes in IC interconnects can be achieved. In this article, based on the above background, we focus on discussing some of the main challenges and developments in the application of CVD-grown carbon nanotubes in IC interconnects, including low-temperature CVD, metallicity enrichment, and contact resistance. [ABSTRACT FROM AUTHOR]

The influence of the method applied to synthesize Cu-Mn-O spinel was evaluated. The methods selected for the investigation were EDTA gel processes and solid-state reaction synthesis. From the obtained powders, sinters were prepared and assessed in terms of their properties as potential coating materials. Additionally, the influence of Ni and Fe dopants was evaluated. The results show that the EDTA gel processes method seems to be more suitable for spinel synthesis. This method yields spinels that exhibit electrical conductivity above the required threshold (>50 S/cm) over a temperature range of 400–850 °C, and it also ensures continuous spinel matrices and high spinel content. Spinels obtained via solid-state reactions exhibit inferior properties. A higher concentration of Ni allows electrical conductivity to be improved further, while the opposite tendency is observed for Fe. Finally, it was shown that spinels obtained via EDTA gel processes are promising protective-conducting coating materials for SOEC/SOFCs steel interconnects. • Cu-Mn-O spinel microstructure can be engineered via appropriate powder synthesis. • EDTA-powder-based spinels exhibit electrical conductivity > 50 S/cm above 400 °C. • Solid-state-reaction-based spinels have low electrical conductivity over 300–850 °C. • Higher Ni content improves the conductivity of spinels, whereas Fe decreases it. • Cu-Mn-O spinels are suitable coating materials for SOEC/SOFCs metallic interconnects. [ABSTRACT FROM AUTHOR]

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 nJ energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.

Complementary Oxide Semiconductor (CMOS) integrated circuits (IC’s) technology is emerging as a means for realization of capable and affordable systems that operate at frequencies near 300 GHz and higher. This is lowering a key barrier for utilizing the submillimeter electromagnetic waves in everyday applications. Despite the fact that the unity maximum available gain frequency, f max of $N$ -channel MOS (nMOS) transistors (with connections to the top metal layer) has peaked at ~320 GHz, signal generation up to 1.33 THz, coherent detection up to 1.2 THz, and incoherent detection up to ~10 THz have been demonstrated using CMOS IC’s. Furthermore, highly integrated rotational spectroscopy transceivers operating at frequencies up to near 300 GHz, and 400-GHz concurrent transceiver pixels and arrays for high-resolution radar imaging, and 300 and 390-GHz transmitters, and 300-GHz receivers for high data-rate communication have been demonstrated in CMOS. The performances of these CMOS circuits are sufficient or close to being sufficient to support electronic smelling using rotational spectroscopy that can detect and quantify concentrations of a wide variety of gases; imaging that can enable operation in a wide range of visually impaired conditions; and high-bandwidth communication. Finally, techniques for affordable packaging and testing submillimeter-wave systems are suggested based on experimental demonstrations.

Epidermal electronics have been attracting considerable attention due to their various potential applications in human‐computer interaction and health monitoring. However, because of the lack of a self‐adhesive and stable interconnect method between epidermal electronic sensors and rigid circuit boards, there remain difficulties in detecting body signals accurately by epidermal electronic sensors in daily life. Here, a 3D helical on‐skin interconnect is first introduced for epidermal electronics sensors. Inspired by the structure of the accordion lantern, the interconnect is composed of two electrospinning polyurethane (PU) fiber films and a helical metal fiber. The helical metal fiber acts as a stable conductor with stretchability, and the PU fiber film with polydimethylsiloxane provides a self‐adhesive substrate. Mechanical simulations and tests prove that the proposed interconnect can laminate conformally and unobtrusively onto human skin with excellent electrical stability (less than 0.5% electrical resistance change upon 100% elongation). Furthermore, based on the proposed interconnect, an all‐in‐one sensor‐interconnect design is presented, which endows the epidermal electronic systems with anti‐motion interference capability. A gesture identification wristband system realized by a single all‐in‐one strain sensor is demonstrated. Besides, a wireless on‐skin system that accurately monitors dynamic 12‐lead electrocardiographic is successfully built using all‐in‐one electrodes. [ABSTRACT FROM AUTHOR]

Low-cost Ni-Co alloy coating was performed by electroplating technique to improve the high-temperature corrosion resistance of stainless steel interconnects in solid oxide fuel cells (SOFCs). The effect of plating on the surface morphology, microstructure and composition of Ni-Co alloys was investigated by scanning electron microscopy (SEM), X-ray diffraction (XRD) and atomic force microscopy (AFM). The Ni-Co coatings were fabricated at thickness of around two microns and compared at different Ni-Co molar ratios. Corrosion performance of Ni-Co coating was evaluated in a muffle furnace under ambient atmosphere at 800℃ for 110 h. Co2NiO4 spinel oxides and Cr2O3 were found on the Ni-Co coated samples after the oxidation test. Results indicated that steel substrate corrosion protection improved with a low parabolic rate constant of 20 times after Ni-Co alloy electrodeposition coating. A smooth coating layer containing Co2NiO4 oxide with fewer defects promoted high oxidation resistance of the steel samples. [ABSTRACT FROM AUTHOR]

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection. [ABSTRACT FROM AUTHOR]

UV-induced photoluminescence of organosilica films with ethylene and benzene bridging groups in their matrix and terminal methyl groups on the pore wall surface was studied to reveal optically active defects and understand their origin and nature. The careful selection of the film's precursors and conditions of deposition and curing and analysis of chemical and structural properties led to the conclusion that luminescence sources are not associated with the presence of oxygen-deficient centers, as in the case of pure SiO2. It is shown that the sources of luminescence are the carbon-containing components that are part of the low-k-matrix, as well as the carbon residues formed upon removal of the template and UV-induced destruction of organosilica samples. A good correlation between the energy of the photoluminescence peaks and the chemical composition is observed. This correlation is confirmed by the results obtained by the Density Functional theory. The photoluminescence intensity increases with porosity and internal surface area. The spectra become more complicated after annealing at 400 °C, although Fourier transform infrared spectroscopy does not show these changes. The appearance of additional bands is associated with the compaction of the low-k matrix and the segregation of template residues on the surface of the pore wall. [ABSTRACT FROM AUTHOR]

Electromigration (EM)-induced diffusional transport of metal atoms, which can manifest as the defects of grain boundary slits and voids in a metal line, often fail an entire electronic component. Formulating preventive strategies and their efficient implementation involves the analysis of failure mechanisms in 4D microstructures via tedious in situ x-ray tomography characterization as well as large-scale phase-field simulations, both of which are resource-intensive. Given this limitation, we report a data-driven emulation (DDE) technique, which couples machine learning with microstructure modeling, to enable a high-throughput and accurate prediction of grain boundary slit evolution in progressively degrading Cu interconnects under EM. In this context, the effectiveness of the stepwise linear regression approach which is the cornerstone of DDE has been quantified. We also analyze the importance of training dataset choice that significantly impacts the convergence between emulated and the phase-field simulated slit evolution dynamics. Finally, we also discuss the DDE-based insights related to the predominance of one or more descriptors in determining the slit evolution dynamics, which cannot be otherwise obtained directly from phase-field simulations. [ABSTRACT FROM AUTHOR]

Mo(001) and Mo(011) layers with thickness d = 4–400 nm are sputter-deposited onto MgO(001) and α-Al2O3(11 2 ¯ 0) substrates and their resistivity is measured in situ and ex situ at room temperature and 77 K in order to quantify the resistivity size effect. Both Mo(001) and Mo(011) layers are epitaxial single crystals and exhibit a resistivity increase with decreasing d due to electron surface scattering that is well described by the classical Fuchs and Sondheimer model. Data fitting yields room temperature effective electron mean free paths λ*= 14.4 ± 0.3 and 11.7 ± 0.3 nm, respectively, indicating an anisotropy with a smaller resistivity size effect for the Mo(011) orientation. This is attributed to a smaller average Fermi velocity component perpendicular to (011) surfaces, causing less surface scattering and a suppressed resistivity size effect. First-principles electronic structure calculations in combination with Boltzmann transport simulations predict an orientation dependent transport with a more pronounced resistivity increase for Mo(001) than Mo(011). This is in agreement with the measurements, confirming the effect of the Fermi surface shape on the thin-film resistivity. The predicted anisotropy λ 001 * / λ 011 * = 1.57 is in reasonable agreement with 1.66 and 1.23 measured at 77 and 295 K. The overall results indicate that the resistivity size effect in Mo is relatively small, with a measured product of the bulk resistivity times the effective electron mean free path ρoλ* = (7.7 ± 0.3) and (6.2 ± 0.2) × 10−16 Ωm2 for Mo(001) and Mo(011) layers. The latter value is in excellent agreement with the first-principles-predicted ρoλ = 5.99 × 10−16 Ωm2 and is 10% and 40% smaller than the reported measured ρoλ for Cu and W, respectively, indicating the promise of Mo as an alternate conductor for narrow interconnects. [ABSTRACT FROM AUTHOR]

Based on the classical theory of microstructure evolution, we develop a finite element method to simulate the evolution of isotropic conductive inclusions in interconnects due to electromigration-induced interface diffusion. The validity of the method is verified by the agreement of the numerically simulated migration behavior of a circular inclusion with that predicted theoretically. The results indicate that the evolution behavior of the elliptical inclusion depends on the electric field intensity, the linewidth ratio, the initial aspect ratio and the resistivity ratio of the matrix to the inclusion. And the four governing parameters have corresponding critical values. When the electric field intensity or the initial aspect ratio is greater than the corresponding critical value, the linewidth ratio, or the resistivity ratio is less than the corresponding critical value, and inclusion splitting occurs at the low potential end. Otherwise, the inclusions migrate along the direction of the electric field with relatively stable morphology. An intense electric field or a large aspect ratio accelerates the inclusion evolution and is also beneficial to the inclusion splitting. The increase of the linewidth ratio or the resistivity ratio can inhibit inclusion splitting, but when the electric field intensity is large enough, neither can hinder the inclusion splitting. The effect of the linewidth ratio is negligible when it is larger than its critical value. [ABSTRACT FROM AUTHOR]

This research paper presents a novel circuit modeling and analysis of ternary logic for MWCNT bundle interconnects with active shielding under the influence of temperature variations. The far end crosstalk-induced noise and propagation delay of MWCNT bundle interconnects has been analyzed with and without the effect of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at output. The temperature-dependent analysis is also carried out at different temperatures such as 300, 400 and 500 K. The temperature-dependent comparative analysis for MWCNT bundle, SWCNT bundle and copper interconnects with and without shielding is also performed. It has been observed that MWCNT bundle with active shielding outperforms the SWCNT and Cu by 75.7% and 84.4%, respectively. Similarly, the power dissipation is substantially reduced in the case of MWCNT bundle with respect to the Cu and SWCNT interconnects. It is also reported that the noise margin is marginally stable in ternary interconnects under the influence of temperature variation. [ABSTRACT FROM AUTHOR]

This paper proposes a method for extracting transmission characteristics of interconnects in printed circuit boards (PCBs) from near-field emission. A wideband microstrip line electric probe is used to measure the near-field emission. There are two key technologies in the extraction principle, obtaining the transfer function and the input signal estimation, and they are explained in detail. To validate the method, one-trace structures, including a corner trace and a via trace, and a multi-trace structure were measured. The transmission characteristics extracted by the proposed method agrees well with the standard vector network analyzer (VNA) measurements up to frequency of 12 GHz. The error caused by the distance and the disturbance signal is investigated. [ABSTRACT FROM AUTHOR]

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated. [ABSTRACT FROM AUTHOR]

Transient analysis, limited by the variability of process-induced physical and geometrical parameters in the capacitively coupled Li-doped MLGNR interconnects operating at the subthreshold mode, is the subject of this paper. An analytical approach based on transmission-line theory is presented here to model crosstalk-induced noise in the subthreshold regime of capacitively coupled MLGNR interconnects. The effect of the underlying dielectric material's surface roughness on the performance characteristics of MLGNR interconnects is examined by deriving an equivalent mean free path (MFP) that accounts for surface roughness scatterings. Moreover, in order to understand the variability effect of MLGNR on-chip interconnects, the impact of the process-induced physical parameters (temperature and Fermi energy levels) and geometric parameters (dielectric thickness, interconnect length, and width) is being investigated. As temperature or interconnect length increases, crosstalk-induced delay (XTID) increases, while XTID decreases with increased fermi energy level, dielectric thickness, and width. It is worthwhile noting that the average error values obtained are not greater than 5% and 18% for the obtained Vmax and Vtime-duration, respectively. [ABSTRACT FROM AUTHOR]

Because of their unique properties, different varieties of carbon nanotubes (CNTs), either pure or hybrid, have been proposed as a promising substitute for interconnects in several industrial applications. In this study, a new FDTD-based method was validated with LTSPICE results and then used for the propagation delay calculation inside copper, carbon nanotube, and hybrid copper-carbon nanotube interconnects. The performance of the proposed algorithm was compared with the CN-FDTD and ABCD-MATRIX methods. The best performance was obtained using the θ-FDTD algorithm. The results achieved in this work show the superiority of the proposed method for transient analysis to obtain accurate results. [ABSTRACT FROM AUTHOR]

This publication reports self‐aligning metallic via microlensing gas phase electrodeposition formation. Key operational parameters to fabricate vertical ruthenium and rhodium interconnects (via) with a diameter of 100 nm are discussed. Moreover, airgaps are implemented during the deposition process, which utilizes spark discharge to generate a flux of charged nanoparticles. An inert gas flow transports the nanoparticles through a reactor chamber close to the target substrate. The substrate uses a pre‐patterned resist with openings to a silicon/silicon dioxide/metal stack to direct the deposition of the nanoparticles to form localized self‐aligning vertical interconnects. Five process parameters were identified, which impact the morphology and conductance of the resulting interconnects: spark discharge power, gas flow rate, microlens via dimensions, substrate surface potential, and in situ flash lamp power. This parameter set enables a controlled adjustment of the via interconnect morphology and its minimum feature size. Gas flow rate in combination with spark discharge power contribute significantly to the morphology of the interconnect. Spark power and microlens via dimensions have the largest influence on the surface potential of the insulating resist cover, which enables a localized microlensing gas phase electrodeposition of a via with a controlled ratio between conducting diameter and airgap. [ABSTRACT FROM AUTHOR]

A frequency-domain model is developed to analyze isolated interconnects of multilayer graphene-nanoribbon (MLGNR) and mixed carbon-nanotube bundle (MCB) driven by CMOS gates. The model derived is founded on an equivalent-single-conductor model of MLGNR and MCB that takes thermal considerations into account (i.e. TD-ESC). The model includes the derivation of transfer function of interconnect to estimate its delay and bandwidth performance. The attained results, reveals that among the neutral MLGNR (N-MLGNR), intercalation doped MLGNR (ID-MLGNR) intercalated with FeCl 3 , MCB and Cu interconnects, FeCl 3 ID-MLGNR achieves the best bandwidth efficiency. At a global interconnect length of 1 mm, FeCl 3 ID-MLGNR outperforms N-MLGNR, MCB, and Cu in terms of bandwidth with an improved bandwidth value of 12.2 GHz, 7 GHz, and 61.4 GHz, respectively. Further, employing the proposed CMOS-gate-driven model, for FeCl 3 ID-MLGNR, bandwidth is improved by nearly 7.52 × at global length (∼1 mm) in relation to the linear resistance model. Additionally, TD-ESC dependency of the proposed model reveals that FeCl 3 ID-MLGNR becomes more stable as interconnect resistance increases. • CMOS-driven interconnects of multilayer graphene-nanoribbon(MLGNR) and mixed CNT bundle(MCB) analysed in frequency-domain. • A temperature-dependent equivalent-single-conductor (TD-ESC) approach estimates interconnect performance accurately. • The derived transfer function for interconnects allows for the estimation of delay and bandwidth performance. • At global interconnect domain, FeCl3 intercalation-doped MLGNR (ID-MLGNR) outperforms neutral-MLGNR (N-MLGNR), MCB and Cu. [ABSTRACT FROM AUTHOR]

Fault detection and diagnosis of the interconnects are crucial for prognostics and health management (PHM) of electronics. Traditional methods, which rely on electronic signals as prognostic factors, often struggle to accurately identify the root causes of defects without resorting to destructive testing. Furthermore, these methods are vulnerable to noise interference, which can result in false alarms. To address these limitations, in this paper, we propose a novel, non-destructive approach for early fault detection and accurate diagnosis of interconnect defects, with improved noise resilience. Our approach uniquely utilizes the signal patterns of the reflection coefficient across a range of frequencies, enabling both root cause identification and severity assessment. This approach departs from conventional time-series analysis and effectively transforms the signal data into a format suitable for advanced learning algorithms. Additionally, we introduce a novel severity rating ensemble learning (SREL) approach, which enhances diagnostic accuracy and robustness in noisy environments. Experimental results demonstrate that the proposed method is effective for fault detection and diagnosis and has the potential to extend to real-world industrial applications. • Root cause analysis is challenging with previous signal-based methods. • We obtain frequency-domain reflection coefficients of the interconnects with defects. • Reflection coefficient shows distinguishing patterns according to the defect states. • A non-destructive fault diagnosis method is proposed by learning signal patterns. • Severity rating ensemble learning improves diagnostic accuracy in noisy conditions. [ABSTRACT FROM AUTHOR]

In recent years, the application of deep learning (DL) models has sparked considerable interest in timing prediction within the place-and-route (P&R) flow of IC chip design. Specifically, at the pre-route stage, an accurate prediction of post-route timing is challenging due to the lack of sufficient physical information. However, achieving precise timing prediction significantly accelerates the design closure process, saving considerable time and effort. In this work, we propose pre-route timing prediction and optimization framework with graph neural network (GNN) models combined with convolution neural network (CNN). Our framework is divided into two main stages, each of which is further subdivided into smaller steps. Precisely, our GNN-driven arc delay/slew prediction model is divided into two levels: in level-1, it predicts net resistance (net R) and net capacitance (net C) using GNN while the arc length is predicted using CNN. These predictions are hierarchically passed on to level-2 where delay/slew is estimated with our GNN based prediction model. The timing optimization model utilizes the precise delay/slew predictions obtained from the GNN-driven prediction model to accurately set the path margin during the timing optimization stage. This approach effectively reduces unnecessary turn-around iterations in the commercial EDA tools. Experimental results show that by using our proposed framework in P&R, we are able to improve the pre-route prediction accuracy by 42%/36% on average on arc delay/slew, and improve timing metrics in terms of WNS, TNS, and the number of timing violation paths by 77%, 77%, and 64%, which are an increase of 32%/35% on arc delay/slew and 30%, 20% and 31% on timing optimization compared with the existing DL prediction model. • We proposed a net and arc GNN (Graph Neural Network) model that considers the relationships with neighboring nets and arcs. • Our model takes into account the surrounding environment with precision by considering the relationships with neighboring nets and arcs in terms of architecture and also reflecting routing resources in terms of features. • We propose a novel deep-learning model which hierarchically connects two levels of prediction for higher delay prediction accuracy. • In the initial stage, which is a combined model of GNN and CNN, predictions are made for net R, net C, and arc length, which form the foundation for delay estimation. • By incorporating GNN along with CNN, we were able to amplify the representation of relationships with neighboring elements, which was challenging task to express solely using CNN. • Subsequently, the more refined predictions from the previous step are passed on to the next stage, enabling the use of more sophisticated features for delay prediction through another GNN. • Unlike previous research that solely compared values of multiple features and routing congestion, the utilization of GNN's graph formulation in this study allows the reflection of relationships with the surrounding elements. • We improve the prediction on arc delay, which in turn leads to accurate path delay prediction. Ultimately, this reduces unnecessary additional design iterations in design optimization and facilitates faster convergence in timing closure. [ABSTRACT FROM AUTHOR]

The integration of carbon nanostructures with semiconductor nanowires holds significant potential for energy-efficient integrated circuits. However, achieving precise control over the positioning and stability of these interconnections poses a major challenge. This study presents a method for the controlled growth of carbon nanofibers (CNFs) on vertically aligned indium arsenide (InAs) nanowires. The CNF/InAs hybrid structures, synthesized using chemical vapor deposition (CVD), were successfully produced without compromising the morphology of the pristine nanowires. Under optimized conditions, preferential growth of the carbon nanofibers in the direction perpendicular to the InAs nanowires was observed. Moreover, when the CVD process employed iron as a catalyst, an increased growth rate was achieved. With and without the presence of iron, carbon nanofibers nucleate preferentially on the top of the InAs nanowires, indicating a tip growth mechanism presumably catalysed by a gold-indium alloy that selectively forms in that region. These results represent a compelling example of controlled interconnections between adjacent InAs nanowires formed by carbon fibers.

With the continuous shrinkage of integrated circuit (IC) dimensions, traditional copper interconnect technology is gradually unable to meet the requirements for performance improvement. Carbon nanotubes have gained widespread attention and research as a potential alternative to copper, due to their excellent electrical and mechanical properties. Among various methods for producing carbon nanotubes, chemical vapor deposition (CVD) has the advantages of mild reaction conditions, low cost, and simple reaction operations, making it the most promising approach to achieve compatibility with integrated circuit manufacturing processes. Combined with through silicon via (TSV), direct application of CVD-grown carbon nanotubes in IC interconnects can be achieved. In this article, based on the above background, we focus on discussing some of the main challenges and developments in the application of CVD-grown carbon nanotubes in IC interconnects, including low-temperature CVD, metallicity enrichment, and contact resistance.