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A novel device structure with gate engineered recessed double gate junctionless field-effect-transistor (R_DGJLFET) has been investigated for variations in effective oxide thickness (EOT) and the optimum structure is utilized for the low power biosensing application. The device with 20 nm gate length has been designed and analyzed using ATLAS tool of SILVACO TCAD. With extensive simulation several physical parameters such as field and potential distribution, carrier concentration and conduction band energy have been analyzed along with drain current and gate-to-source capacitance. Several FOM of R_DGJLFET and conventional junctionless FET (C_DGJLFET) have been compared. It has been found that for EOT of 0.8 nm the R_DGJLFET reduces IOFF by ~ 10− 4 and the subthreshold slope is also improved. Moreover, for EOT ≤ 1 nm, the R_DGJLFET outperforms the C_DGJLFET with improved analog parameters. Furthermore, a low power biosensing application has been implemented with the proposed device. Dielectric modulation is utilized to realize the different type of biomolecules inside the cavity region of the structure. Biosensor is tuned at low voltage for better performance, which presents it as a promising contender for the future CMOS based low power sensor applications. [ABSTRACT FROM AUTHOR]

The synergistic effect of ferroelectric and HfO2/SiO2 (Hafnium dioxide/ Silicon dioxide) hetero dielectrics in double gate Junctionless Field Effect Transistor is investigated using TCAD Tool. The study encompasses a wide range of parameters, allowing for a detailed examination of the impact of hysteresis on the overall functionality of the double gate Junctionless FET. One crucial aspect of the investigation involves examining the analog and RF performance of the device. The high transconductance (gm) of 5.42 mS, a gain of 95 dB (decibel), a cut‐off frequency of 553.9 GHz (gigahertz), a gain transconductance frequency product (GTFP) of 50.9 THz (terahertz), and a gain bandwidth product (GBW) of 188 GHz shows its great potential for analog and RF signal processing applications as well as for other high data rate wireless applications such as Machine Learning (ML), Artificial Intelligence (AI) and Internet‐of‐Thing (IoT). The low transit time of 17 ns (nano second), with high ION/IOFF ratio range of 107 shows that the device has good switching behavior also. This aspect of the research aims to unveil the device's viability for analog and high‐frequency applications, contributing valuable insights to the emerging electronic technologies field. [ABSTRACT FROM AUTHOR]

Abstract For the first time, a new configuration of label-free junctionless semiconductor device is proposed to boost sensitivity in the identification of biomolecule specifies. Instead of creating the nanocavity inside the gate oxide, the nanocavity is created in the channel region which is very useful for the SOI junctionless technology based biodevice having a high current in all operating modes. For better control of the conduction mechanism, a hole trench is created under the channel region just inside the buried oxide. This will help to modulate the energy bands terminating in enhancing the sensing performance. Unlike the conventional biosensors needing a large-scale gate oxide thickness for trapping the biomolecules, the proposed biosensor can work for very low gate oxide thickness. The different biomolecules such as Biotin, Protein A, Bacteriophage T7, and Apomyoglobin have been utilized as targeted biomolecules for evaluating the sensitivity. Comparing the proposed biosensor with the conventional and other biosensors showed an enhanced sensing performance. Practical related issues during the process of sensing in terms of fill factor percentage, steric hindrance of biomolecules, and the charges of biomolecules have been focused in the recommended biodevice. All the results exhibited high superiority of performance of the suggested biodevice as compared to the conventional biosensor.

For the first time, a new configuration of label-free junctionless semiconductor device is proposed to boost sensitivity in the identification of biomolecule specifies. Instead of creating the nanocavity inside the gate oxide, the nanocavity is created in the channel region which is very useful for the SOI junctionless technology based biodevice having a high current in all operating modes. For better control of the conduction mechanism, a hole trench is created under the channel region just inside the buried oxide. This will help to modulate the energy bands terminating in enhancing the sensing performance. Unlike the conventional biosensors needing a large-scale gate oxide thickness for trapping the biomolecules, the proposed biosensor can work for very low gate oxide thickness. The different biomolecules such as Biotin, Protein A, Bacteriophage T7, and Apomyoglobin have been utilized as targeted biomolecules for evaluating the sensitivity. Comparing the proposed biosensor with the conventional and other biosensors showed an enhanced sensing performance. Practical related issues during the process of sensing in terms of fill factor percentage, steric hindrance of biomolecules, and the charges of biomolecules have been focused in the recommended biodevice. All the results exhibited high superiority of performance of the suggested biodevice as compared to the conventional biosensor. [ABSTRACT FROM AUTHOR]

A Rectangular core–shell (RCS), employed to three fins vertically stacked with gate oxide stack junctionless nanosheet, along with doping and gate/dielectric engineering, is explored. This paper proposes an N-type three fins vertically stacked with gate oxide stack junctionless nanosheet with opposite core doping in the channel referred to as RCS. The simulation results show that three fins vertically stacked with gate oxide stack with RCS junctionless nano-sheet exhibit reduced Ioff is 6.913E-21, increased Ion is 2.408E-07, Ion/Ioff ratio is 0.418×106, DIBL is 6.9mV and SS is 60.65 mV/dec, respectively. Furthermore, the P-type of three fins vertically stacked with gate oxide stack junctionless nanosheet and combined -type and P-type three fins vertically stacked with gate oxide stack junctionless nano-sheet were stimulated to construct the inverter circuit. The Voltage Transfer Characteristics (VTC) of three fins vertically stacked with gate oxide stack junctionless nano-sheet with RCS have HfO2 as the gate-oxide based inverter has been notably improved compared to SiO2, al2O3 as a gate oxide and conventional three fins vertically stacked with gate oxide stack junctionless nano-sheet inverter. [ABSTRACT FROM AUTHOR]

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability. [ABSTRACT FROM AUTHOR]

The gate-all-around junctionless field-effect transistor (GAA JL FET)-based biosensor has recently attracted worldwide attention due to its good sensitivity to gate-all-around architecture and overall conduction mechanism. The effect of temperature usually affects the performance of transistors and sensors. Therefore, the impact of temperature on the 3D GAA JL FET-based biosensor has been investigated in this work. The dielectric modulation (DM) approach has been considered for including biomolecules. Consequently, the main proprieties of this biosensor have been investigated by ranging the temperature from 77 K to 400 K. The simulated results showed that the on-state current lowers as the temperature rises, but the off-state current increases. The off-current variation concerning the temperature is higher than the on-current change. Also, this type of biosensor appears to have a finer threshold voltage. Furthermore, the obtained results reveal that the current sensitivity is increased when ranging from temperature from 200 K to 400 K, and deteriorates for lower temperature values, like 100 K and 77 K. In addition, the GAA JL FET-based biosensor is more reliable for the detection of neutral biomolecules at high temperatures. [ABSTRACT FROM AUTHOR]

In this paper, the junctionless Fin Field Effect Transistor (FinFET) and nanosheet Field Effect Transistor (NSFET) with a gate length of 12 nm are implemented using the Sentaurus Technology Computer-Aided Design (TCAD) tool. To compare the junctionless FinFET and NSFET, simulations are done at constant threshold voltage. The NSFET outperformed FinFET in terms of current driving capabilities, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), and intrinsic voltage gain (AV). Further, the device design guidelines are presented for FinFET and NSFET in terms of geometrical parameters. The simulation indicates that downscaling the gate length from 16 to 8 nm leads to an increase in SS and DIBL by 21 and 68.49 % in FinFET whereas 19 and 70.14 % in nanosheet FET. The height variation of FinFET seems to make the least impact on short channel effects (SCEs) while scaling the thickness of NSFET from 9 to 5 nm improves the DIBL and SS by 61.9 % and 15.54 % respectively. In the case of scaling the width of FinFET from 10 to 5 nm, DIBL and SS increase by 55.4 % and 14 % whereas scaling of nanosheet width from 24 to 12 nm gives 19.44 % and 1.37 % improvement in DIBL and SS, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a multi-gate junctionless field-effect transistor with a quad gate and multiple channels has been proposed and thoroughly simulated. The proposed device offers a lower Ioff current of 4.34 × 10−19 A, an Ion current of 4.17 × 10−06 A with an Ion/Ioff current ratio of 9.65 × 1012, a threshold voltage of 0.86 V, a transconductance of 5 × 10−05 S, a drain-induced barrier lowering (DIBL) of 22 mV/V, and a subthreshold slope (SS) of 61.51 mV/dec. The visual contour plots of the device are also included in this study to understand the working mechanism. The larger tunneling width between the channel drain and barrier height between the source–channel interface exhibits a lower leakage current and better performance. The performance of the proposed device is also studied when the work function between the semiconductor and gate material is altered. The work function difference improves the performance metrics. Aside from that, the effects of temperature variation on the device's performance characteristics are also being studied. When the temperature varies by 33% the threshold voltage of the proposed device drops by only 7% which shows a minimum variation in the proposed device. The results obtained from the proposed device exhibit the potential of using multi-gate multi-channel junctionless field effect transistor (MCMG) device in low-power logic circuits and memory devices. [ABSTRACT FROM AUTHOR]

The design and analysis of a gate stack gate-all-around junctionless nanowire field-effect transistor (GAA-JL-NWFET) with a catalytic metal as gate contact for oxygen gas sensing is presented in this study. An n-channel GAA-JL-NWFET design using gold (Au) as the gate metal electrode is employed for oxygen sensing by utilizing appropriate work function values, which interact with oxygen gas and change the device's electrical properties. This work focuses on changes in temperature (300–500 K) and Au metal gate work function (5.05–5.20 eV) to investigate the presence of oxygen molecules and their impact on the GAA-JL-NWFET gas sensor performance. Changes in the surface potential, threshold voltage, hole concentration, electron concentration, subthreshold voltage, electric field, and drain current using the ATLAS TCAD simulator are investigated for the adsorption of gas molecules to determine the electrical characteristics of the proposed device. Changes in threshold voltage (Vth), switching ratio, and subthreshold current sensitivity ( S I OFF ) can be considered as sensitivity parameters for sensing oxygen gas molecules. The results reveal that as the Au work function shifts at the gate by 100 mV, the sensitivity ( S I OFF ) enhancement using gate stack GAA-JL-NWFET-based oxygen gas sensors compared to GAA-MOSFET and conventional MOSFET are 15.13% and 88.31%, respectively. Based on our simulation results, the proposed device offers excellent sensitivity, low power consumption, and a fast response time, making it an appropriate candidate for oxygen gas sensing, including environmental monitoring, medical diagnosis, and industrial safety. [ABSTRACT FROM AUTHOR]

In this work, we have presented an analytical model for a recently proposed symmetrical recessed double gate junctionless field‐effect transistor (R_DGJLFET) operating in subthreshold region. The model has been developed by solving a two‐dimensional Poisson's equation in three continuous rectangular silicon regions, resulting in explicit expressions for surface potential, center potential, and eventually the subthreshold drain current. The model provides deeper physical insights by successfully incorporating the effect of various design parameters such as doping concentration, gate length, gate work function, and effective oxide thickness on the subthreshold drain current. Moreover, the effect of variations in gate length on the subthreshold slope has also been presented. The model results have been validated with the simulation results obtained from the Silvaco Atlas tool and found reasonably close. [ABSTRACT FROM AUTHOR]

A Rectangular core-shell (RCS) is analyzed on vertically stacked gate oxide junctionless nanosheet along with doping and gate/dielectric engineering. This paper also proposes an N-type three fins vertically stacked with gate oxide stack junctionless nanosheet with opposite core doping in the channel known as RCS. The simulation results show that gate oxide stack with RCS junctionless nanosheet exhibit reduced $I_{\mathrm {OFF}}$ is 6.913E-21, increased $I_{\mathrm {ON}}$ is 2.408E-07, $I_{\mathrm {ON}}$ / $I_{\mathrm {OFF}}$ ratio is $0.418\times 10^{6}$ , DIBL is 6.9mV and SS of 60.65 mV/dec respectively. The core shell width variations with various gate oxide dielectric towards better $I_{\mathrm {ON}}$ , $I_{\mathrm {OFF}}$ and $I_{\mathrm {ON}}$ / $I_{\mathrm {OFF}}$ are analyzed. Interestingly, it is noted that for smaller shell thickness, the thickness of core should be equivalent to shell thickness and for larger shell thickness, thicker core is required. The device robustness towards analog and RF metrics are also evaluated with varied gate dielectrics. It has been observed that RCS architecture with opposite doping with HfO2 as gate oxide material has given outstanding outcomes compared to other gate oxide materials and without RCS method. Further, simulated the P-type of three fins vertically stacked with gate oxide stack junctionless nanosheet and combined both N-type and P-type three fins vertically stacked with gate oxide stack junctionless nanosheet to construct the CMOS inverter circuit. The voltage transfer characteristics (VTC) characteristics of junctionless nanosheet with RCS having HfO2 as gate-oxide based inverter has been notably improved as compared to the SiO2, Al2O3 and conventional three fins vertically stacked with gate oxide stack junctionless nanosheet inverter.

This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar gate stack and state-of-art process, in the temperature range from 300 K to 580 K. The comparative analysis is performed through the main electrical parameters of the devices, such as the threshold voltage, subthreshold current and slope, DIBL, conduction current, mobility, and maximum transconductance extracted from experimental data. Devices with different fin widths are compared. It is demonstrated that the inversion-mode nanowire transistors present higher performance with three times higher maximum transconductance and conduction current and twice higher low field mobility than the junctionless’ with a fin width of 10 nm at a fixed temperature. On the other hand, the junctionless nanowire transistors presented higher thermal stability of their electrical parameters with a 75% lower variation of maximum transconductance with temperature, 77% lower maximum transconductance variation with temperature, and 22% lower temperature coefficient of mobility.

A gate engineered ferroelectric junctionless field-effect transistor biosensor (BioFET) is proposed and investigated for label-free detection of various biomolecules. A nanocavity is created by etching a part of the gate oxide material on the top and bottom of the device, which allows biomolecules to get immobilized. The immobilization of biomolecules in the cavity causes changes in electrostatic characteristics such as surface potential, input and output characteristics, transconductance, output conductance, gate capacitance, and cutoff frequency used as sensing metrics. The biosensor is also examined at different biomolecule concentrations (−1 × 1012 cm−2, 0 cm−2, and 1 × 1012 cm−2). The transistor's sensitivity is then understood by looking at the fluctuation in threshold voltage, subthreshold swing, and switching ratio. The performance is compared between the ferroelectric junctionless BioFET and the gate engineered ferroelectric junctionless BioFET. The results indicate that the gate engineered ferroelectric junctionless BioFET shows the maximum improvement for protein (1202.4%, 111%, and 565%) and DNA (787.5%, 117.3%, and 600%). The gate engineered ferroelectric junctionless BioFET is shown to be suitable for ultrasensitive bio-sensing applications. [ABSTRACT FROM AUTHOR]

This research presents a biosensor based on a dielectrically modulated (DM) silicon on insulator (SOI) junctionless fin-shaped field-effect transistor (FinFET) (DM-SOI-JL-FinFET) for the detection of biomolecules. This biosensor is integrated with a label free detection of neutral biomolecules such as biotin (k = 2.53), APTES (k = 3.57), ferro-cyt C (k = 4.7), bacteriophages (k = 6.3), and keratin (k = 8). By etching the gate oxide, a nanocavity with a thickness of 5 nm and a height of 35 nm is created for immobilized biomolecules. The presence of biomolecules is determined by observing variations in the dielectric constant. Various important parameters including threshold voltage, the ratio of on-state and off-state current (ION/IOFF) sensitivity, drain current, transconductance, and surface potential are thoroughly investigated for different biomolecules with a function of dielectric constant, fin height, and fin width. The study demonstrates a threshold voltage sensitivity (Sv) of 0.1552 (biotin, k = 2.53) and 0.5628 (keratin, k = 8), as well as an ION/IOFF current sensitivity (SI) of 1.1609 (biotin, k = 2.53) and 3.9774 (keratin, k = 8) for the simulated structure. [ABSTRACT FROM AUTHOR]

In this paper, an analytical, detailed two-dimensional potential profile model of a newly proposed rectangular core-shell-based double-gate junctionless metal oxide semiconductor (RCS-DGJLMOS) is presented. A detailed numerical solution of the model is presented for conventional n-type double-gate junctionless MOS (DGJLMOS), and the changes made in the model for RCS-DGJLMOS are extensively presented. While solving 2-D Poisson equations, a parabolic potential is assumed along the silicon thickness for both devices. The characteristics of the potential profile are studied on varying doping concentrations, dielectric constants, silicon thickness, and gate oxide thickness in conventional DGJLMOS, whereas the thickness of the core, total silicon thickness, dielectric constants, and core doping are varied in RCS-DGJLMOS. The detailed study on potential profile reveals the huge depletion of RCS-DGJLMOS as compared to conventional DGJLMOS due to the presence of oppositely doped core and, therefore, improves the device performance. Furthermore, the transfer characteristics are also presented for both devices. The analytical results for DGJLMOS and RCS-DGJLMOS have been assessed with Technology Computer Aided Design (TCAD) software. The analytical results obtained from the proposed model are verified with the simulation data. [ABSTRACT FROM AUTHOR]

The evolution trend of wireless communication systems tends to ultra-high data rate, ultra-low latency, and high bandwidth systems. It is foreseen that 6G wireless communication systems will be developed in the range of 100–300 GHz (upper mmWave band) and 300–3000 GHz (terahertz band). In such frequencies, the performance of junctionless field effective transistors is limited due to the reduction of carrier mobility in the device channel. In this paper, for the first time, a shell doped device is proposed to improve RF merit parameters and high-frequency noise performance of GaN junctionless double surrounding nanotube FET device with dual material outer gate (SD-GaN-JNFET). Simulation results show that the doping engineering in the proposed device reduces scattering caused by phonon and doping and increases electron mobility significantly. Parameters gmmax and ƒT of the SD-GaN-JNFET device in channel length of 15 nm are 666 μS and 8.47 THz, respectively, and NFmin<0.025 dB is satisfied in the frequency range of 0-500 GHz. The effect of shell doped area on the linearity performance is evaluated. Moreover, the device shows excellent reliability in terms of trap charges. A non-quasi-static small signal model is developed for the device and incorporated into a low noise amplifier (LNA) design. The LNA with S21 = 22.10 dB and NF = 0.032 dB in central band frequency (140 GHz) was attained. This article opens up an opportunity to achieve high-performance LNA for D-Band 6G applications with the reliable SD-GaN-JNFET device. [ABSTRACT FROM AUTHOR]

Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged as a promising alternative to conventional MOSFETs, offering simplified fabrication and potential performance improvements. The novelty of this research lies in the selection of hetero‐dielectric material to optimize the performance of junctionless transistors under the misaligned gate and high‐temperature conditions, and the aim is to explore its capability for low‐power high‐frequency application. The results reveal that the proposed junctionless field effect transistor exhibits increased transconductance (17 mS), which enables higher gain (311 dB) and diminishes capacitive effects, leading to a broader range of cutoff frequencies (154 GHz) with gain frequency product and gain transconductance frequency product are 31 and 95.9 THz, respectively. Moreover, this research article investigates critical reliability issues related to junctionless MOSFET, focusing on gate misalignment and thermal stability. The study reveals that gate misalignment reduces on‐current and degrades device performance. Additionally, the study examines thermal stability over a wide temperature range (300 to 500 K), exploring the impact of temperature on performance. These valuable findings provide crucial insights to overcome fabrication challenges and drive the practical adoption of junctionless MOSFETs in future integrated circuits. To assess device performance in high‐frequency applications, Silvaco ATLAS TCAD tools are employed. [ABSTRACT FROM AUTHOR]

An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in $15 \leqslant {P_r} \leqslant 30\,\mu C/c{m^2}$ and $0.8 \leqslant {E_c} \leqslant 1.5\,MV/cm$, which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field Pr/Ec. As Pr/Ec increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to Pr/Ec is more severe.

A proposed core–shell gate all-around junctionless field-effect transistor (CS GAA JLFET) is studied using extensive simulations. An oppositely doped core is sandwiched between the shells to achieve lesser leakage current due to an increase in tunneling width at the channel/drain interface and an increase in source/channel barrier height. The core doping is initially optimized, followed by the variation of channel length. Different gate dielectric is studied and investigated. The best performance parameters are obtained for channel length 20 nm with k = 15. The OFF current of ∼10−16 A/µm, ON current of ∼10−4 A/µm, ON/OFF current ratio ∼1012, subthreshold slope of 60.61 mV/decade, and drain-induced barrier lowering of 8.5 mV/V are obtained. The study is done using contour plots, surface potential, and central potential to better understand the proposed CS GAA JLFET device. The better control over the carriers in GAA configuration and the advantage of core–shell architecture helps achieve significant improvement in performance parameters. [ABSTRACT FROM AUTHOR]

An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in 15 ⩽ P r ⩽ 30 μ C / c m 2 and 0.8 ⩽ E c ⩽ 1.5 M V / c m , which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field P r / E c . As P r / E c increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to P r / E c is more severe. An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in and , which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field P r / E c . As P r / E c increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to P r / E c is more severe. [ABSTRACT FROM AUTHOR]

This research investigates the virtually doped dual gate junctionless impact ionization MOS (DG-JL-IMOS). Virtually doped source and drain regions are realized through the genesis of charge plasma using different work-functions for their electrodes, easing the process complexity with simultaneous reduction of process-induced variations to implant uniform doping. The proposed DG-JL-IMOS device exhibits two order increase in I ON / I OFF ratio at a lower source bias of - 4.5 V with respect to - 5 V required for a single gate JIMOS device. This work further examines the breakdown behavior of the proposed DG-JL-IMOS by analyzing carrier density distribution, impact ionization, and electric field profile through extensive TCAD simulations. The proposed device exhibits a super steep sub-threshold swing (SS) of 0.6 mV/dec over several orders of drain current, which is not achieved by any other counterpart steep-slope technologies. The effect of interface traps on the proposed DG-JL-IMOS is studied and investigated for hysteresis in the transfer characteristics. Furthermore, analog parameters such as transconductance ( g m ), unity gain cutoff-frequency ( f T ), and current gain of the proposed device are evaluated and compared with conventional DG-IMOS. It is observed that the proposed device shows a 2.6 × increase in I ON , 1.7 × higher g m , 1.6 × higher f T , and a 5 dB improvement in current gain compared to conventional DG-IMOS. The proposed DG-JL-IMOS device breakdowns at a voltage, ( V BD ) of - 4.21 V, whereas DG-IMOS breakdowns at - 4.75 V. The enhanced performance metrics of DG-JL-IMOS elucidate its suitability for high-speed and high-performance analog applications. [ABSTRACT FROM AUTHOR]

The impression of gate dielectric and spacer dielectric on the performance of rectangular core shell double gate junctionless transistor (RCS-DGJLT) using extensive simulations is studied. The RCS-DGJLT brings captivating response in terms of the performance of the device. The effect of gate dielectric and spacer dielectric is studied for the first time in RCS-DGJLT. The performance of the device gets improve on increasing the dielectric constant till core thickness (tcore) = 3 nm for shell thickness (tshell) = 4 nm. However, beyond core thickness 3 nm, the performance degrades much for high k dielectric. Further, the performance is enhanced for tcore > 3 nm and higher k dielectric on reducing the core doping. The device performance is also studied by incorporating the spacers. It has been shown that the device performance is best at tcore = 4 nm with low k gate dielectric however, the device performance degrades when high k spacer dielectric is used on the same device which is an interesting and different outcome as compared to conventional DGJLT. The ON current and ON/OFF current ratio are improved by ∼3 orders of magnitude using highly doped source/drain region(HD-S/D) with high k spacers. The results show that the core is the integral part of the device, any engineering like spacers, gate dielectrics applied to RCS-DGJLT requires the optimization of the core carefully for better device performance. [ABSTRACT FROM AUTHOR]

In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current ( $I_{\mathrm {ON}}$ ) rises with an increase in temperature compared to the downfall trend in INV mode. In addition, compared to JL mode, the INV mode exhibits a better negative temperature coefficient of threshold voltage ( $\text{d}V_{\mathrm {th}}$ /dT). Further, the mixed mode circuit simulations are carried out using the Cadence Virtuoso platform through the Verilog-A model. From the analysis, it is observed that an increase of 20% gain in INV mode compared to JL mode for a common source (CS) amplifier. The JL mode NS-FETs achieve higher CMOS inverter switching current ( $I_{SC}$ ) and lower energy-delay products (EDP) as temperature rises. A three-stage ring oscillator (RO) is designed, and the oscillation frequencies ( $f_{\mathrm {OSC}}$ ) of 43.39 GHz and 38.8 GHz are obtained with INV and JL modes. Although JL NS-FET offers less intrinsic capacitances, the $f_{\mathrm {OSC}}$ is high for INV mode due to higher $I_{\mathrm {ON}}$ . Furthermore, reducing supply voltage ( $V_{\mathrm {DD}}$ ), the $f_{\mathrm {OSC}}$ falls by 67% with INV and 62.6% with JL modes. These results will give a better understanding of this emerging NS-FET at both device and circuit levels at advanced technology nodes.

We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO2 used as an insulator decreases.

Vertically stacked Nanosheet Field Effect Transistor (NSFET) is considered the most promising substitution for FinFET. In order to prevent making metallurgical junctions, based on the nanosheet, junctionless(JL) NSFET has been proposed. However, since the channels of JL-NSFET are stacked and highly doped, JL-NSFET is more vulnerable to random variability. In this article, to optimize the structure of JL-NSFET and reduce the impact of random variability on JL-NSFET, some process variability in JL-NSFET is investigated simultaneously. The process variability discussed in this paper includes Oxide Thickness Variation (OTV), Random Doping Fluctuation (RDF), and Work Function Variation (WFV). Using the statistical impedance field method (sIFM), the impacts of the random variability on device characteristics, such as threshold voltage and subthreshold slope, are analyzed. Simulations of JL-NSFET indicate that lower doping concentration, more stacks, smaller average grain size, bigger sheet spacing, and choosing a suitable value of sheet width can help produce JL-NSFET with less influence from WFV, RDF, and OTV. [ABSTRACT FROM AUTHOR]

In this paper, the performance of a junctionless carbon nanotube field-effect diode in the presence of electron–phonon scattering is examined. A self-consistent mode-space simulation approach based on non-equilibrium Green's function is used. We have studied the influence of incoherent transport on electrical characteristics such as on-current ( I ON ), off-current ( I OFF ), on/off current ratio (ION/IOFF), intrinsic delay (τ), energy-delay product, and sub-threshold power dissipation (SPD ) at various gate lengths. We have shown that phonon-assisted tunneling dominates the band-to-band tunneling regime under off-state conditions. Therefore, this phenomenon deteriorates I OFF and, as a result, SPD . Furthermore, the scattering results in an increase in the intrinsic delay and energy consumed per switching event. Finally, in the on-state, acoustic phonons interaction is the overriding scattering mechanism and causes about a 35% reduction in I ON . [ABSTRACT FROM AUTHOR]

This paper presents Gate Stacked junctionless nanotube gate all around MOSFET (GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS architecture, high-k material as dielectrics was placed over SiO2 which is deposited around the silicon nanotube (for inner and outer surface of silicon nanotube). GS JL NT GAA MOSFET is also compared with non-stacked junctionless nanotube (JL-NT MOSFET) for performance analysis. GS JL NT GAA MOSFET provides a reduced leakage current (~10−16) and high ION/IOFF ratio (~1011) as compared to non-stacked device. Side spacer of suitable material needs to be selected for enhancing the performance metrics such as ION/IOFF ratio, SS, DIBL. Furthermore, the spacer length and diameter of core gate also plays vital role for device design. Therefore, GS JL NT GAA MOSFET has low leakage and high switching speed, which leads it for low power circuit applications. [ABSTRACT FROM AUTHOR]

We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO2 used as an insulator decreases. [ABSTRACT FROM AUTHOR]

This work presents a new junctionless device called Workfunction Modulated Dual Metal Gate Junctionless FinFET (WFMDMG-Junctionless FinFET) to minimize the short channel effects, and to achieve improved dc performance. The result is analyzed by dividing the workfunction of the gate metal electrode in two equal halves and further dividing the source end of the electrode in five equal parts with linear variation in workfunction, keeping the drain end at constant workfunction. The 3-D TCAD simulations are carried out by SILVACO TCAD tool. And the results are compared with the Single Metal Gate (SMG)-junctionless FinFET, and Dual Metal Gate (DMG)-junctionless FinFET. The new proposed junctionless device shows improved subthreshold characteristics, i.e., minimum subthreshold swing (SS) of 60.1 mV/decade, and high ION/IOFF current ratio of 1.48e13. [ABSTRACT FROM AUTHOR]

We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO2/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO2/ZrO2, La2O3, and TiO2 with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.

The performance of junctionless ringFETs under heavy ion irradiation is investigated utilizing 3D TCAD simulations. The vulnerable location of the ringFET device is identified by conducting a single-event transient analysis on the interaction of an ionizing particle, particularly a heavy ion, with various LET values. The analysis focused on both the inner and outer drain configurations. The drain region is the most vulnerable location in an inner drain configuration, whereas the channel near the drain region is the most vulnerable location in an outer drain configuration of a junctionless ringFET. The source region of a junctionless ringFET is the least vulnerable location in both the inner and outer drain configurations. An Inverter circuit built using junctionless ringFETs utilizing inner and outer drain configurations is also subjected to single-event transient analysis. The junctionless ringFET with an inner drain configuration is better for use in areas where radiation is a concern since its collected charge is lower than that of the outer drain configuration. • This study investigates the effects of heavy ion radiation on Junctionless ringFET structures, comparing the performance of both outer drain and inner drain configurations using 3D TCAD simulations. • Furthermore, Single Event Transient analysis is conducted on inverter circuits constructed using Junctionless ringFETs using both outer drain and inner drain configurations, allowing for the selection of the most reliable device for use in radiation-prone environments. [ABSTRACT FROM AUTHOR]

This work investigates into the potential application of an improved N+ pocket Vertical Junctionless TFET (V-JL-TFET) as a label free biosensor. To calculate the sensitivity of the biosensor, an analytical model based on device physics was developed that accounts for the impact of both charged and uncharged biomolecules on the threshold voltage (V th). As a result, the developed model offers a solution that is applicable for both uncharged and charged biomolecules. This model demonstrates a strong agreement with the experimentally determined threshold voltage (V th) obtained from simulation results. Furthermore, sensitivity is obtained by assessing the shift in threshold voltage (V th) resulting from changes in the dielectric constant. It's observed that V th increases with decrease in dielectric value. The V th value with empty nanogaps has been used as a reference point. Finally, the sensitivity of gate threshold voltage was calculated, and the obtained values are high enough to detect both charged and uncharged biomolecules. A detailed analysis of Selectivity, Linearity, stability and reliability of the proposed Biosensor is also presented. [ABSTRACT FROM AUTHOR]

This work presents the SOI Junctionless Fin-FET characterization in Deep Cryogenic behavior (DC-JLFET). Results show that the JLT device is well-suited for various operations, such as computation, sensing, and communication in the quantum field. The cryogenic transfer characteristics, including bias, and interface trap density, are analyzed over a broad temperature range (300 Kelvin down to 4.2 Kelvin). Cryogenic DC and RF analyses were done on the conventional double-gate JL-FET structure, operating at 300 K and below 4.2 K for different geometries. The suggested study illustrates that cryogenic status in the new technology CMOS can be correctly anticipated by calibrating data using an experimental device.

We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL) current in erase operation of FeFETs with a floating body. We also introduced a novel gate stack process for low voltage operation by inserting a Ti layer in the metal gate. The Ti layer insertion can suppress the growth of an interfacial layer (IL) by controlling oxygen intrusion into the IL during the rapid thermal anneal (RTA) process. We demonstrated an efficient erase operation at shorter and lower pulse voltage with GIDL current in the overlap structure than in the underlap structure. A compact FeFET retention model is developed based on the surface-potential based FET model, the nucleation-limited-switching (NLS) model, and the retention model of ferroelectric (FE) capacitor. Faster degradation of the program state observed in the experiment can be explained by electron detrapping according to the modeling and simulation.

An analytical Subthreshold Swing (SS) model is presented to observe the change in the SS when a stacked SiO2-metal-ferroelectric structure is used as the oxide film of a JunctionLess Double Gate (JLDG) MOSFET. The SS of 60 mV/dec or less is essential to reduce power dissipation while maintaining transistor performance. If a ferroelectric material with Negative Capacitance (NC) effect is used, the SS can be reduced below 60 mV/dec. The analytical SS model of the ferroelectric NC FET presented to analyze this was in good agreement with the SS derived from the relation between the drain current and gate voltage, using 2D potential distribution. As results were derived from the analytical SS model, it was found that it is possible to obtain an SS of 60 mV/dec or less even at 15 nm channel length by adjusting the thicknesses of the silicon channel, SiO2, and ferroelectric. In particular, the change in SS according to the ferroelectric thickness was saturated as the thickness of SiO2 increased and was almost constant as the thickness of the silicon channel decreased. ABSTRAK: Model Ayunan Subambang (SS) analitikal dibentangkan bagi melihat perubahan pada SS apabila struktur feroelektrik-logam-SiO2 bertindan digunakan sebagai filem oksida bagi MOSFET Dua Get Tanpa Simpang (JLDG). SS 60 mV/dec atau kurang adalah penting bagi mengurangkan pelesapan kuasa sambil mengekalkan prestasi transistor. Jika bahan feroelektrik dengan kesan Kapasitans Negatif (NC) digunakan, SS dapat dikurangkan bawah 60 mV/dek. Model SS analitikal feroelektrik NC FET yang digunakan bagi kajian ini adalah sesuai dengan SS yang diperoleh daripada hubungan antara arus serapan dan voltan get, menggunakan edaran potensi 2D. Dapatan terbitan melalui model SS analitikal, mendapati bahawa adalah mungkin bagi mendapatkan SS pada 60 mV/dek atau kurang walaupun panjang laluan adalah 15 nm dengan melaraskan ketebalan saluran silikon, SiO2, dan feroelektrik. Terutama apabila perubahan ketebalan feroelektrik SS adalah tepu ketika ketebalan SiO2 meningkat, dan hampir malar apabila ketebalan saluran silikon berkurang.

The recently proposed recessed double gate junctionless field-effect-transistor (R_DGJLFET) based circuit performance has been investigated with emphasis on designing various digital logic standard cells. Symmetric inverter circuit (NOT gate) has been designed and analyzed extensively using mixed-mode simulator in Silvaco TCAD. The proposed device-based inverter reflects lesser overall power consumption with static leakage component (~0.104 nW), switching power dissipation (~11.613 μW), and short-circuit power dissipation (~0.472 nW). The static analysis of the proposed device-based symmetric inverter features steeper voltage transfer characteristics, better noise margins and smaller short-circuit current relatively while the excellent transient delay response with rise time (~9.3 ps), fall time (~9.0 ps), and propagation delay of (~6.5 ps) for load capacitance of 10 fF. Moreover, the proposed device based 2-input logic cells namely NAND, NOR, and XOR gate has also been implemented and their transient response with a different load capacitance of 10 fF and 0.1 pF has been presented. The simulation results show that increasing the load capacitance results in a longer propagation delay of the circuits. Furthermore, the transient performance of all R_DGJLFET based digital logic gates has also been investigated with equal gate width for PMOS and NMOS devices. It has been found that designing the asymmetric logic gates weakens the pull-up characteristics which eventually elongates the delay values. [ABSTRACT FROM AUTHOR]

Herein, the authors suggest a junctionless field effect transistor with an embedded p‐type layer (EPL‐JLT) near the drain channel side, employing calibrated structure simulations to obtain a complete depletion region in a 6 nm channel length. The incorporation of a p‐type layer improves leakage current (IOFF) and subthreshold swing (SS) for a 6 nm regime structure at 5.9 eV work function (WF) while the ON current (ION) diminishes a little. This considerable achievement in the leakage current enables obtaining multiple threshold voltages (VTH) by adjusting the gate WF. The goal aids in creating optimized structures, which is impossible in silicon JLFETs (Si‐JLT) due to their requirement for large WFs to obtain a depletion region even at higher channel lengths. The proposed device has a leakage current of 1 nA μm−1 even at a 5.1 eV WF. The scaling of the EPL‐JLT for different channel lengths is investigated. [ABSTRACT FROM AUTHOR]

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator. [ABSTRACT FROM AUTHOR]

This paper investigates the various device dimensions such as gate length (Lg), nanosheet thickness (TNS), and nanosheet width to optimize the design space for vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The optimization has been carried out by considering several analog/RF parameters that include On-current (ION), Off-current (IOFF), Transconductance Efficiency (gm/Id), Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), ION/IOFF ratio, Transconductance (gm), gate capacitance (Cgg), Output conductance (gds), and Cutoff-frequency (fT), Intrinsic gain (Av) are explored here. It is found that the downscaling of Lg from 16 nm to 8 nm resulted in an increase in SS and DIBL. However, scaling down of TNS (WNS) from 10 nm to 5 nm (from 18 nm to 10 nm) resulted in a decrease in SS by ~30.5% (~16.39%) and in DIBL by ~44.23% (~78.59%) respectively. The short channel effects (SCE) are greatly suppressed by upscaling of Lg and downscaling of TNS and WNS. The transconductance (gm) is improved by decreasing the Lg and TNS but a significant degradation is found for WNS. Further, the gain (Av) is improved by an amount of ~22.86% by upscaling the Lg and ~ 7.07%, ~31.75% with the downscaling of TNS and WNS respectively. The gate capacitances (Cgg) are reduced with the downscaling of Lg and WNS, however the same is increased for TNS. Moreover, the cutoff frequency (fT) is improved with scaling down of Lg and TNS in comparison with the WNS. [ABSTRACT FROM AUTHOR]

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give the highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths. [ABSTRACT FROM AUTHOR]

In this work, a Core–Shell Junctionless MOSFET is proposed as a RADFET dosimeter for possible radiation-sensitive applications. The analytical models of the surface potential, drain current, and the threshold voltage is developed to investigate the electrostatic behaviors of the proposed device under post-irradiation condition. The sensitivity is measured through the threshold voltage shift for a long-range of applied doses. The results compared with contemporary literature reveal a superior sensitivity performance of our proposed device. It exhibits a linear sensitivity profile with a sensitivity of 2.03 mV/Gy over a wide radiation dose range, from 300 Gy to 30,000 Gy. Furthermore, the analytical model accurately captures the device's characteristics compared to the simulation results, carried out SILVACO TCAD 3D device simulator. Therefore, we propose the Core–Shell Junctionless RADFET dosimeter as a promising candidate for future VLSI CMOS technology. [ABSTRACT FROM AUTHOR]

Advances in microelectronics have enabled smaller technical nodes, lower threshold voltages, and greater working frequencies. Even though VLSI circuit performance and power consumption have improved as a result, the reliability of the designs has suffered. A fall in noise resistance and an increase in uncertainty from multiple sources of variability make circuits more vulnerable as technology scales down. Fault tolerant techniques are commonly used in safety-critical applications. Three-dimensional electrical devices like double gate, tri-gate, and nanowire field-effect transistors (FETs) give an alternative approach since they regulate the device channel better electrostatically. In this paper, a new form of FinFET with asymmetric gate and source/drain connections is developed, and its simulation results are shown. Asymmetric FinFETs exhibit better short-channel behavior when the current density is increased, according to the results of the benchmarking. High aspect ratio FinFETs give greater current per area while demanding significantly fewer horizontal geometry constraints, making them ideal for situations where conventional scaling has hit its physical limits. The suggested multigate FinFET provides improved performance in low-power and high-frequency applications, according to the experimental results. The work report also includes an evaluation of the proposed multigate FinFET's dependability. [ABSTRACT FROM AUTHOR]

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (ION/IOFF) = ~106 shows a higher level of electrostatic integrity. At 5 nm LG with optimized spacer dielectric the device exhibits ~5 orders of improvement in IOFF and the improvement is less than ~2 orders at 20 nm LG. Thus, from the result analysis, the spacer dielectrics are essential at lower LG for better performance. For continued scaling, the HfO2 spacer dielectric ensures high performance with the lowest downfall in ION with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si3N4 respectively. With SiO2, Si3N4, and HfO2 spacers the asymmetric spacer ensures an ION/IOFF of ~106 which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes. [ABSTRACT FROM AUTHOR]