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Submicrometer‐thick AlGaN/GaN high‐electron‐mobility transistor (HEMT) epilayers grown on silicon substrate with a state‐of‐the art vertical buffer breakdown field as high as 6 MV cm−1 enabling a high transistor breakdown voltage of 250 V for short gate‐to‐drain distances despite such a thin structure are reported. HEMTs with a gate length of 100 nm exhibit good DC characteristics with a low drain‐induced barrier, going as low as 100 mV V−1 for a VDS of 30 V. Breakdown voltages of each epilayer from the decomposed heterostructure reveals that the outstanding breakdown strength is attributed to the insertion of Al‐rich AlGaN in the buffer layers combined with an optimized AlN nucleation layer. As a result, large signal measurements at 10 GHz could be reliably achieved up to VDS = 35 V despite the use of a 100 nm gate length. These results demonstrate the potential of submicrometer‐thick buffer GaN‐on‐Si heterostructures for high‐frequency applications. [ABSTRACT FROM AUTHOR]

The design of a continuous broadband Doherty power amplifier (DPA) based on an X‐parameter model is presented in this work. The broadband load‐pull X‐parameter model is extracted at both the package plane and current generate plane of the device under test. The model cannot only predict the fundamental and harmonic nonlinear behavioral accurately, but also find the optimal output power and drain efficiency (DE) region of the Smith chart precisely, thereby assisting DPA design. A 10‐W gallium nitride packaged transistor from Wolfspeed is utilized in this design. The fabricated DPA reached a saturation output power of 44.3 dBm, with a saturation DE over 68% and a 6 dB output power back‐off efficiency over 51% in the frequency range of 1.1–1.8 GHz, verifying experimentally the effectiveness of the proposed design methodology. [ABSTRACT FROM AUTHOR]

This article presents an empirical investigation of calibration effects on load-pull measurements collected on wafer and at W-band frequencies. An analysis of scattering parameter (S-parameter) measurements provides insight into how small-signal metrics germane to load pull are affected by choice of the calibration technique. It is found that off-wafer line-reflect-reflect-match (LRRM) calibrated measurements of the same transistor with different probes exhibit drastically different maximum small-signal gains compared to equivalent on-wafer multiline thru-reflect-line (mTRL) calibrated measurements. Load-pull measurements are heavily influenced by choice of calibration algorithm, and LRRM calibrated large-signal measurements collected with different waveguide probes yield variations in large-signal gain of over 2 dB and variations in peak PAE of over 24 percentage points. The equivalent on-wafer mTRL calibrated load-pull measurements collected with different waveguide probes are consistent to within 0.1 dB for large-signal gain and 1 percentage point for peak PAE. This work provides quantitative evidence that on-wafer mTRL calibration with well-designed calibration structures is preferred for large-signal measurements collected at millimeter-wave frequencies. If utilization of on-wafer mTRL calibration is not possible, this work suggests using similar measurement setups, i.e., waveguide probes, calibration standards, etc., for evaluating on-wafer unmatched transistors in a consistent manner.

This paper presents a novel and accurate procedure for designing a Doherty power amplifier (DPA) for wireless systems. The method is based on a systematic approach to designing the matching networks of both Main and Auxiliary devices, which employs an optimization process to set their input impedance in the corresponding optimal regions obtained from the standard load- and source-pull simulations. To import the optimum regions of each device into the optimization algorithm, mathematical expressions are derived and graphically reported on the Smith chart. Besides this, we have developed an accurate method to account for the loading effect of the Auxiliary amplifier on the Main one at back-off when designing the Main PA. As a proof of concept, a symmetric DPA is designed, fabricated, and tested. The measurements showed a working frequency band of 3.3–3.9GHz (aimed at n78 band of 5G-NR), a minimum peak output power of 36W, drain efficiency between 48%–53.2% at peak and 34.6%–44.5% at 6dB back-off.

This paper presents the design procedure of an efficient compact monolithic microwave integrated circuit power amplifier (MMIC PA) in a 0.1 μm GaN-on-Si process for 5G millimeter-wave communication. Load/source-pull simulations were conducted to correctly create equivalent large-signal matching models for stabilized power cells and to determine the optimal impedance domain. The shorted stub with bypass capacitors minimizes the transistor's output reactance, simplifying the matching objective to an approximate real impedance transformation (IT). With miniaturization as the implementation guide, explicit formulas and tabulated methods based on mathematical analysis were applied to synthesize the filtering matching networks (MNs) for the input and output stages. In addition, a CAD-dependent numerical optimization approach was used for the interstage MN that needs to cope with high IT ratio and complex loads. The continuous-wave (CW) characterization for the proposed two-stage PA demonstrated 19.8 ± 0.7 dB of small-signal gain, very flat output power (Pout) and power-added efficiency (PAE) at 4 dB gain compression of 32–32.4 dBm and 34–34.6%, respectively, over 24–30 GHz, with 37.1% of peak PAE at mid-frequency. [ABSTRACT FROM AUTHOR]

In this paper, we report on an enhancement of mm-wave power performances with a vertically scaled AlN/GaN heterostructure. An AlGaN back barrier is introduced underneath a non-intentionally doped GaN channel layer, enabling the prevention of punch-through effects and related drain leakage current under a high electric field while using a moderate carbon concentration into the buffer. By carefully tuning the Al concentration into the back barrier layer, the optimized heterostructure offers a unique combination of electron confinement and low trapping effects up to high drain bias for a gate length as short as 100 nm. Consequently, pulsed (CW) Load-Pull measurements at 40 GHz revealed outstanding performances with a record power-added efficiency of 70% (66%) under high output power density at VDS = 20 V. These results demonstrate the interest of this approach for future millimeter-wave applications. [ABSTRACT FROM AUTHOR]

This paper presents a broadband GaN microwave monolithic integrated circuit driver amplifier (MMIC DA) with compact dimensions of 1.65 mm × 0.78 mm for 5G millimeter-wave communication. The optimal impedance domain satisfying the preset goals was first acquired using the simplified load-pull procedure and small-signal simulations, followed by a weighted average method to determine the reference center matching point from which the optimal intrinsic load can be deduced. By means of de-embedding load-pull contours, modeling based on theoretical analysis, and simulation fitting for parameter identification, the nonlinear output capacitance and a series RLC model circuit approximating the input impedance response of the stabilized transistor were extracted. Under the design principle of fully absorbing the parasitic parameters of the device, explicit formulas and tabulated methods related to the Chebyshev impedance transformer were applied to construct filter-based synthesized matching networks at each stage and finally convert them into an implementable mixed-element form via the single-frequency equivalence technique. Measured on-wafer pulsed results for the proposed two-stage DA across 24–30 GHz demonstrated up to 31.1 dBm of saturated output power (Psat) with less than 1 dB total fluctuation, 19.3 ± 1 dB of small-signal gain, and 39.8% of peak power-added efficiency (PAE) at the mid-frequency. [ABSTRACT FROM AUTHOR]

This paper proposes a new time-domain multi-tone distortion (TD-MTD) model suitable for accurately predicting the non-linear behavior of packaged high power radio frequency (RF) transistors over a range of discrete non-uniformly distributed frequencies. This proposed TD-MTD model uses a single expression rather than multiple distinct frequency specific behavioral models to describe the underlying behavior of the high power RF transistor at multiple fundamental frequencies. Furthermore its extraction is carried out using a time-domain representation of the travelling waves that can be acquired using a generic vector load-pull characterization system and without imposing additional requirements. The proposed model is extracted as an artificial neural network (ANN) and is implemented as a Netlist to serve in a harmonic balance simulator based power amplifier design process. The proposed model is validated in two phases. First, its ability to reproduce the large-signal behavior of a high power RF LDMOS transistor was demonstrated in simulation. Then, the TD-MTD model was used to validate the design of a high power two-way asymmetric Doherty power amplifier and the simulated output-power-dependent power efficiency, AM/AM, AM/PM and input return loss characteristics were compared to those obtained in measurement. The excellent agreement between the simulation and measurement results confirms the usefulness of the proposed model despite the simplicity of its extraction routine and measurement data.

In this article, we propose a matching network design algorithm based on the segmentation of the real and imaginary part of optimum source impedance curve with respect to space variable x and frequency ω, respectively. The impedance curve (comprising of real and imaginary parts) is approximated as a collection of n linear segments, represented by the weighted sum of n semi‐infinite linear functions. Using the numerical method, optimum weight vectors that maximize transducer power gain are obtained to model the real and imaginary parts of the source impedance curve. We get the values of optimum weight vectors and the rational input impedance function for the matching network, which are then synthesized in the desired topology by a continued partial fraction. Experimentally, we validate the novelty of the proposed method by designing matching networks of a wideband custom monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) in 1.3–2.3 GHz frequency band. The measured results of the designed LNA are significantly close to the simulated results. We bias our LNA at (5 V, 150 mA) and achieve a maximum noise figure of 1.25 dB, OP1dB of 26 dBm, and an average TOI of 38 dBm. Moreover, our design of custom LNA MMIC has an integrated ESD structure while occupying only 0.32 mm2 of chip area. [ABSTRACT FROM AUTHOR]

A broadband GaN MMIC power amplifier (PA) with compact dimensions of 1.94 × 0.83 mm2 is presented for 5G millimeter-wave communication. To guarantee output capability at the operating band edges where serious performance degradation is likely to occur, the appropriate large-signal matching model and optimal impedance domain need to be carefully determined through load-pull analysis. Broadband matching networks (MNs) in the lowpass form are thereafter developed based on the Chebyshev filter synthesis theory. Using high-pass interstage MN in conjunction with parallel RC lossy circuits to compensate for the transistor's negative gain roll-off slope ensures a flat frequency response. The input MN is designed as a band-pass filter due to the reactance extracted from the input side of the stabilized device exhibiting series LC resonance characteristics. Measured on-wafer pulsed results for the proposed three-stage PA demonstrate up to 30.9 dBm of output power, more than 28.6 dB of small-signal gain, and a peak power-added efficiency (PAE) of 35.6% at 27 GHz. Both uniform gain and saturated output power (Psat) are achieved across 24–30 GHz with fluctuations of less than 0.8 dB. [ABSTRACT FROM AUTHOR]

A new mathematical formulation for the Cardiff nonlinear behavioral model is presented in this work which includes the dc bias voltages (drain and gate) into the model. It has been verified by modeling a GaN on SiC high electron mobility transistor (HEMT) at 3.5 GHz. For the case presented, interpolation of load–pull data has resulted in a more than 90% reduction in the density of the load–pull data required to generate a nonlinear behavioral model over a wide range of dc bias points. [ABSTRACT FROM AUTHOR]

This letter presents a novel design of a Class‐F monolithic microwave integrated circuit (MMIC) power amplifier (PA) operating at L‐band with a power‐added‐efficiency (PAE) better than 70%. The MMIC PA is designed via load/source‐pull techniques to locate the optimal impedances at fundamental and harmonic frequencies on not only output but also input terminations. Moreover, rather than quarter wavelength stubs used in conventional designs, several parallel/series LC resonators are utilized to behave open/short at certain harmonics and to reform the drain waveform, yielding highly efficient performance of the PA MMIC. A prototype PA MMIC validating the proposed method is designed, fabricated and measured, which implemented on a 0.25 μm gallium nitride high electron mobility transistor technology. The measurement results of the PA under a drain voltage of 28 V at 1 ms pulse width with 30% duty cycle demonstrated a PAE better than 70% over 1.2–1.4 GHz with an output power greater than 40 dBm (10 W). The chip size is 2.5 mm × 3.5 mm (8.75 mm2). [ABSTRACT FROM AUTHOR]

The AlN/GaN/AlN heterostructure is attractive for microwave and millimeter-wave power devices due to its thin top barrier, tight carrier confinement, and improved breakdown voltage. This work explores the large-signal RF performance of high-electron-mobility transistors on this heterostructure. Results are highlighted by record high on-current of 3.6 A/mm, and record maximum oscillation frequency ( $f_{max}$ ) of 233 GHz. The load-pull power sweep at 10 GHz demonstrate a peak power added efficiency (PAE) of 22.7% with an associated gain ( $G_{T}$ ) of 8.7 dB and output power ( $P_{out}$ ) of 3 W/mm. When optimized for power, the peak $P_{out}$ of 3.3 W/mm has an associated PAE of 14.7% and $G_{T}$ of 3.2 dB. This first demonstration is encouraging for the mm-wave power potential of the AlN/GaN/AlN HEMT.

Reconfigurable Matching Networks (RMN) have found a wide range of applications, such as antenna impedance matching (Antenna Tuning Units -ATU-), the design of reconfigurable power amplifiers, applications in Magnetic Resonance Imaging (MRI), adjustable low noise amplifier design, etc. In this paper, we propose the experimental design and verification of a reconfigurable impedance synthesis network that can simultaneously work in three different bands and is completely independent so that the impedance variations in a frequency band are approximately transparent to the rest. The variable elements used in this paper are varactors. To verify its operation, it is applied to a process of matching a laser modulator in three different frequency bands for C-RAN (Cloud Radio Access Networks) applications. Experimental results demonstrate, as expected, that losses may depend on the state in which they are driven. Consequently, a state that can guarantee a good match could also imply greater losses, leading to a certain trade-off. The application of genetic algorithms in this context points out that it may be convenient to optimize the insertion losses of the complete chain instead of the return losses.

Based on the dynamic load-line GaN HEMT large signal model and load-pull technology, a high efficiency harmonic tuned power amplifier operating at 2 GHz is designed and implemented. Under the condition that the parasitic parameters and package parameters of the transistor are unknown, the optimal fundamental and harmonic impedance values that meet the performance requirements are initially determined by the load-pull technology, and tuning and optimizing the overall circuit of the power amplifier based on the drain current and voltage waveforms obtained from the dynamic load-line large signal model. The measured results show that, when the input power is 27 dBm, the drain efficiency reaches 81.53%, the power added efficiency is 76%, the output power is 38.69 dBm, and the gain is 11.69 dB. The high-efficiency harmonic tuned power designed by this method has the advantages of simple structure and convenient tuning, while satisfying high performance.

In this paper, we report on an enhancement of mm-wave power performances with a vertically scaled AlN/GaN heterostructure. An AlGaN back barrier is introduced underneath a non-intentionally doped GaN channel layer, enabling the prevention of punch-through effects and related drain leakage current under a high electric field while using a moderate carbon concentration into the buffer. By carefully tuning the Al concentration into the back barrier layer, the optimized heterostructure offers a unique combination of electron confinement and low trapping effects up to high drain bias for a gate length as short as 100 nm. Consequently, pulsed (CW) Load-Pull measurements at 40 GHz revealed outstanding performances with a record power-added efficiency of 70% (66%) under high output power density at VDS = 20 V. These results demonstrate the interest of this approach for future millimeter-wave applications.

This paper presents a broadband GaN microwave monolithic integrated circuit driver amplifier (MMIC DA) with compact dimensions of 1.65 mm × 0.78 mm for 5G millimeter-wave communication. The optimal impedance domain satisfying the preset goals was first acquired using the simplified load-pull procedure and small-signal simulations, followed by a weighted average method to determine the reference center matching point from which the optimal intrinsic load can be deduced. By means of de-embedding load-pull contours, modeling based on theoretical analysis, and simulation fitting for parameter identification, the nonlinear output capacitance and a series RLC model circuit approximating the input impedance response of the stabilized transistor were extracted. Under the design principle of fully absorbing the parasitic parameters of the device, explicit formulas and tabulated methods related to the Chebyshev impedance transformer were applied to construct filter-based synthesized matching networks at each stage and finally convert them into an implementable mixed-element form via the single-frequency equivalence technique. Measured on-wafer pulsed results for the proposed two-stage DA across 24–30 GHz demonstrated up to 31.1 dBm of saturated output power (Psat) with less than 1 dB total fluctuation, 19.3 ± 1 dB of small-signal gain, and 39.8% of peak power-added efficiency (PAE) at the mid-frequency.

In this article, we report on the high dc and RF performance of AlGaN/GaN high electron mobility transistors that employ Ti/Au/Al/Ni/Au metallization stack with shallow trench etching ohmic contact (STEOC). An excellent ohmic contact performance including low contact resistance (${R}_{C}$) of $0.28~\Omega \cdot $ mm and smooth surface morphology have been achieved simultaneously. Atomic force microscope (AFM) reveals a highly smooth surface morphology with a root mean square (rms) roughness of 6.3 nm even after 810 °C high-temperature annealing (HTA), achieving an improvement of 79% as compared to the conventional Ti/Al/Ni/Au ohmic contact (COC). A high-resolution transmission electron microscope (HRTEM) showed a glossy morphology with a continuous and uniform TiN layer formed in the interface for the STEOC sample, while a bumpy morphology caused from the Ni-Al complexes balling up and TiN island penetrating into the AlGaN/GaN heterostructure were observed for the conventional sample. Consequently, the fabricated transistors with the STEOC process show a high output current of 1.52 A/mm and low ON-resistance (${R}_{ \mathrm{ ON}}$) of $2.09~\Omega $ mm. In addition, a high current cutoff frequency (${f}_{T}$) of 60 GHz and maximum oscillation frequency (${f}_{\text {max}}$) of 150 GHz were obtained for the STEOC HEMT with a gate length (${L}_{\text {g}}$) of 150 nm. Sub-6 GHz continuous-wave mode power sweep measurements deliver a high power-added-efficiency (PAE) of 67%. These results show the significant potential of the STEOC process to facilitate the development of GaN-based power amplifier (PA) applied for 5G. [ABSTRACT FROM AUTHOR]

This article describes a methodology for designing broadband high‐efficiency GaN HEMT power amplifier (PA) which is suitable for base stations and modern wireless communication based on the Class‐EF mode. To achieve both efficiency enhancement and bandwidth extension for the PA, the load‐pull technique is employed to acquire the optimum impedance regions of the second harmonic. Especially, considering the influences of the harmonic control network on the accuracy of obtaining the fundamental impedance, the load‐pull technique is performed to obtain the optimal fundamental impedance again after the harmonic control circuit is determined. In addition, the theory of multiple frequencies matching is also employed to manipulate six desired fundamental frequency points concurrently. Based on the proposed theory, the Class‐EF PA prototype is designed and fabricated. The measurement results exhibits a drain efficiency (DE) of 60%–75% in the range of 2.1–3.6 GHz while having an output power of 38–40.5 dBm and gain of larger than 8 dB. [ABSTRACT FROM AUTHOR]

In system‐level design, microwave amplifier needs to be cascaded with other components. In this scenario, the input and output of amplifier model have cascade capability to sense the variation of source and load impedance, and thus can accurately predict the forward and reverse propagating waves. In this letter, the principle and an extraction flow for a simplified polynomial behavioral model are introduced, and the cascade capability of the model is verified by experimental source‐pull and load‐pull results. By simulations, a subcircuit with a low noise amplifier and a power amplifier, which are cascaded, is used to establish behavioral models using the proposed method. It shows that the proposed model results have good agreement with circuits using both continuous wave and modulated signal excitation. Finally, by measurements, the cascaded results of two amplifiers models are compared with the overall results. The results of output waves and magnitude/phase up to third harmonics are consistent with each other. These results verify that the proposed behavioral model has the capability of cascade simulation. [ABSTRACT FROM AUTHOR]

A wideband and highly efficient power amplifier (PA) is designed using a simple and systematic approach. This method employs an optimization process to set the input impedance of the matching networks in optimal regions on the Smith chart, obtained using conventional load-pull/source-pull simulations, in both the fundamental and second harmonics. The developed design method led to a GaN PA whose measurements showed an output power of 46.8–48.1 dBm and a drain efficiency of 57%–71% in a two-octave bandwidth from 0.8 to 3.2 GHz. [ABSTRACT FROM AUTHOR]

We investigate the uncertainty of large-signal measurements of a microwave transistor due to variation in the load conditions at the fundamental frequency. In particular, we evaluate uncertainties in the complex frequency-domain traveling voltage waves. In our analysis, uncertainty sources typical for large-signal measurements are considered. Then, we discuss how the resultant uncertainty in the waves is dependent on a varying load reflection coefficient. For this investigation, we consider the total uncertainty of the waves and their magnitude and phase. We also show that these errors unavoidably affect the uncertainty of performance quantities, such as output power. [ABSTRACT FROM AUTHOR]

The opening of spectral bands in the millimeter-wave (mm-Wave) spectrum from 26 GHz and extending up to the E-band poses new challenges to the power amplifier (PA) design for spectrally agile radios. They are expected to operate with high energy efficiency at peak and back-off levels to process signals with high peak-to-average power ratio (~10 dB), while being able to maintain their performance across a wide range of 5G bands. In addition, the PAs can experience strong load impedance mismatch conditions in a user equipment (UE) that pose additional challenges in handling strong voltage-standing-wave-ratio (VSWR) events. In this article, we present a systematic approach to exploit active load pulling in a multi-port network that synthesizes optimal impedance conditions for 1) broadband peak and back-off operation and 2) mitigating VSWR events at peak power. As proofs of concept, we present two PAs in 65-nm bulk CMOS process. The first chip demonstrates $P_{\text {sat}}$ between 16.3 and 19.3 dBm across 37–73 GHz, with an improvement in the output drain efficiency ($\eta _{\text {out}}$) of up to $3.2\times \!\!/5.8\times $ at 6-/9.6-dB power back-off (PBO) across the frequency range compared to class-A operation. The second chip achieves 26–42-GHz $P_{\text {sat},\, -1 \, {\text{dB}}}$ bandwidth with $P_{\text {sat}} > 19$ dBm and PAE $_{\text {peak}}> 20$ % across all 28–40-GHz bands and with up to $3.35\times $ and $4.84\times $ enhancement in PAE at the PBO levels of 6 and 9.6 dB over class-A operation, respectively. The PA also demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle at a frequency of 33 GHz. [ABSTRACT FROM AUTHOR]

Though GaN HEMTs have primarily been used for power amplification, they are also well suited for receiver applications. In the front-end of receivers, non-linearities, in particular third-order intermodulation products lead to in-band signal distortion. The intermodulation distortion is primarily dominated by transconductance and its derivatives. In this paper, we report on N-polar GaN MIS-HEMTs able to simultaneously achieve high gain (12.7 dB) and excellent linearity performance (OIP3/PDC of 15 dB) for low-power receiver application at 30 GHz. With a two-tone load-pull input-bias sweep, we demonstrate that the linearity of high performance HEMTs is sensitive to bias, and we present our measurement methodology to accommodate this. [ABSTRACT FROM AUTHOR]

In this paper, a consistent DC to RF modeling solution for Al gallium nitride (GaN)/GaN high electron mobility transistors is demonstrated that is constructed around a surface-potential-based core. Expressions for drain current and intrinsic terminal charges in the form of surface-potential are used to simultaneously model the DC characteristics and the intrinsic capacitances of a commercial GaN device. Self-heating and trapping effects are incorporated to account for the non-linear nature of the device. We discuss the parameter extraction flow for some of the key model parameters that are instrumental in fitting the DC characteristics, which simultaneously determines the bias-dependent intrinsic capacitances and conductances that significantly eases the RF parameter extraction. Parasitic capacitances, gate finger resistance, and extrinsic bus-inductances are extracted, from a single set of measured non-cold-FET S-parameters, using the model process design kit. The extraction procedure is validated through overlays of broadband (0.5-50 GHz) S-parameters, load-pull and harmonic-balance (10 GHz) simulations against measured data, under multiple bias conditions to successfully demonstrate the model performance at large-signal RF excitations.

The effects of the nonlinear drain-to-source capacitance ($C_{\mathrm {DS}}$), or the varactor effect, on the operation of continuous-mode class-B/J power amplifiers (PAs) are described in terms of the mathematical analysis as well as experimental validation. The nonlinear $C_{\mathrm {DS}}$ generates harmonic current when the class-B/J drain voltage is applied across it, modifying the theoretical load trajectories on the Smith chart. This is shown to significantly deviate from the continuous-mode assertion of constant power and efficiency. A novel measurement approach called voltage–pull is used to investigate the effects of the second harmonic generation by the varactor in a class-B/J PA mode. Theoretical and experimental results showed the nonlinear $C_{\mathrm {DS}}$ degrades the drain efficiency compared to class-B on one half of the class-B/J design space while improving the other half due to the energy upconversion and downconversion, respectively. This paper provides an approach for die nonlinear characteristic optimizations for transistor manufacturers. [ABSTRACT FROM AUTHOR]

Measurement-based black box behavioral models are widely used nowadays. To handle nonlinear effects efficiently, such models often rely on approximation techniques. Polyharmonic distortion (PHD) modeling emerged as a viable approach for describing a nonlinear mapping. Typical PHD-based models, such as the well-known $X$ -parameter model, are gained from linearization while operating on a certain large signal (LS) operational point. This limits the accuracy, especially for hard nonlinearities. However, quadratic terms can be added, which result in the quadratic PHD (QPHD) model. This enables highly accurate models for devices in strongly nonlinear operation, even in highly mismatched environments. In this paper, the accuracy of such models is investigated by predicting typical nonlinear measures, such as load–pull contours and intermodulation distortion, to assess the model accuracy for both static and dynamic stimulus. Furthermore, the LS matching problem is solved for both the $X$ -parameter and the QPHD model. This allows to predict the optimum matching analytically, without performing load–pull analysis. To verify the accuracy of the model, the results are presented by comparing the model prediction with verification measurements for a commercially available GaN HEMT. [ABSTRACT FROM AUTHOR]

Future radar transmitters must be adaptive and reconfigurable in real time to be able to share spectrum dynamically with wireless communications. We demonstrate the joint, back-and-forth optimization of the radar transmitter waveform and circuitry in a combined algorithm that can be used for real-time reconfiguration. While previously developed methods consider the waveform and circuit separately, resulting in emphasis on one of the criteria [ambiguity function (AF) or power efficiency], we show that the joint optimization of the circuit and waveform allows both the radar AF and circuit power-added efficiency (PAE) criteria to be gradually improved during the optimization. Measurement results are presented and analyzed to assess the convergence of the PAE and AF least-squares error, as compared to the AF template during an optimization under spectral mask and peak-to-average power ratio constraints. [ABSTRACT FROM AUTHOR]

Future radar transmitters will need to be able to quickly reconfigure their radio-frequency circuitry to change operating frequency and spectral output while maintaining high power-added efficiency (PAE). In this paper, fast tuning of a tunable-varactor matching network is demonstrated to optimize the PAE while meeting requirements on the adjacent-channel power ratio. The tunable varactor network, a first-level prototype of a tunable radar amplifier matching network, incurs nonlinear performance, providing possible challenges to measurement accuracy. To address the issue of nonlinearities while maintaining ability to quickly reconfigure, the tunable-varactor network is characterized at different input power levels to allow useful performance in its nonlinear regime. The power-dependent characterization is used in an algorithm for optimization of an amplifier's PAE, by looking up the matching network characterization performed at the power estimated to be output by the amplifier. Measurement results show that this characterization enhances the consistency of the optimized PAE. Using the tunable varactor network reduces the optimization time to one-fourth of the time required when using the algorithm with a traditional mechanical load-pull tuner. [ABSTRACT FROM AUTHOR]

Class-E RF power amplifiers (PAs) are very power efficient under nominal operating conditions. Due to incorporating two tuned tanks, the dependence on the load impedance is, however, relatively large, resulting in, e.g., load-dependent output power, power efficiency, peak voltages, and peak (and average) currents which can lead to reliability issues. This paper presents load–pull analyses for class-E RF PAs from a mathematical perspective, with analyses and discussions of the effects of the most common nonidealities of class-E PAs: the limited loaded quality factor ($Q_{\mathrm {loaded}}$) of the series filter, switch ON-resistance, the limited quality factor of the dc-feed inductor, load mismatch-dependent switch conduction loss, and the limited negative voltage excursions (due to, e.g., the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and load–pull measurements of a class-E PA implemented in 65-nm CMOS technology. The PA provides 18.1-dBm output power and 72% efficiency at 1.4 GHz under nominal operating condition employing an off-chip matching network. [ABSTRACT FROM AUTHOR]

This letter deals with the load-pull measurements at 94 GHz of 450 GHz Si/SiGe fT HBTs. On the one hand the technological modifications performed to improve large signal performances are presented and on the other hand, load-pull measurements are presented after having describing the measurement setup. A state-of-the-art 30.1 mW / μm2 Si/SiGe HBT is demonstrated thanks to a layout optimization. [ABSTRACT FROM AUTHOR]

This paper presents the characterization of a GFET transistor using a source-pull/load-pull test set. The characterization shows that despite the good fT and fMAX, it is hard to achieve power gain using the GFET device within a circuit configuration. This is due to the very high impedance at the gate making impedance matching at the input extremely difficult. S-parameter characterization is performed and the associated small signal model is developed in order to further analyse and extrapolate the source-pull and load-pull measurement results. A good agreement is observed between small signal model simulation results and source-pull/load-pull measurements. Finally, the model is used to evaluate the optimum power gain of the transistor in a circuit configuration under matched conditions.

Benefiting from advantageous features of fast tuning, small size, and easy integration, the electronic impedance synthesizer (EIS) has been developed for on-wafer load–pull characterization systems, tunable matching networks, reconfigurable devices and systems, and so on. The previous designs of the EIS were mostly based on the empirical data instead of a closed-form design. Moreover, incomplete figures of merit (FOM) were chosen to optimize and evaluate the EIS. In this paper, we propose and present, first of all, a semiclosed-form design procedure for the distributed EIS. Then, a particle swarm optimization method is introduced to optimize the proposed nonuniformly distributed EIS, which comprises an adjusting circuit and a nonuniformly distributed circuit. Experimental results demonstrate that the proposed nonuniformly distributed structure can not only improve the Smith chart coverage but also reduce the size, compared to the uniform counterpart. The fabricated nonuniform EIS operating from 0.8 to 2.5 GHz, exhibits a good agreement between theory and measurement. Furthermore, the most comprehensive FOM are presented to evaluate the fabricated EIS. [ABSTRACT FROM AUTHOR]

A high power gain magnetron amplifier with output phase control based on load–pull characterization has been developed. The equivalent resonant cavity method was first introduced to facilitate the proposed magnetron amplifier system as a basic injection model, and the system behavior was qualitatively evaluated based on Alder’s equation. It is the first time that a magnetron has been locked at a 58-dB gain. The magnetron amplifier shows an enhanced power-added efficiency of 72.0%, wide output phase control range, and 18.5-MHz bandwidth at a ratio of the output to the input power of 45 dB. This is the first time a successful magnetron output phase control based on load–pull at a power gain of 45 dB has been demonstrated. The magnetron output spectra were fully synchronized with a reference signal and the phase noise of the magnetron amplifier reached −106.3 dBc/Hz at an offset of 1 kHz. An output amplitude stability of 0.01 dB (peak to peak), a phase stability of 0.5° (peak to peak), and a high-efficiency dual 1-kW magnetron amplifier coherent-power combination based on the load–pull characterization was achieved. To the best of the authors’ knowledge, this is one of the highest power gains and phase noise performances ever reported for an S-band injection-locked magnetron with a power output of over 1 kW. [ABSTRACT FROM AUTHOR]

A frequency reconfigurable millimeter-wave (mm-wave) power amplifier (PA), which can be programmed to operate efficiently for a wide swathe of the spectrum, approaching an universal transmitter, can enable a wide range of novel applications in high-speed communication, sensing, and imaging. Classical techniques to allow large operating range either rely on broadband higher order output combining networks or tunable passives, both of which tradeoff directly with output power and efficiency. In this paper, we present an active impedance synthesis methodology that exploits the interaction of multiple unit PA cells in an asymmetrical non-isolated combiner to synthesize complex mm-wave impedances in a programmable fashion. This allows the interacting power cells to see their optimal load-pull impedances for high-efficiency frequency-reconfigurable operation in an efficient combiner network with no lossy variable passives. Compared to a symmetrical combiner, this enables the network to break the strong tradeoffs between output power, efficiency, and frequency reconfigurability, allowing it to achieve N times the Bode–Fano bound compared with an N-way symmetrical architecture. As a proof of concept, an integrated PA, which is in a 0.13- \mu \textm SiGe process, is demonstrated to achieve $P_{{{\text {sat}}}}$ of 23.6 dBm at a power-added efficiency (PAE) of 27.7% at 55 GHz with a frequency reconfigurable $P_{{\text {sat}},-1}$ sat 1 dB bandwidth of 25 GHz (40–65 GHz) and a PAE,−1 dB bandwidth of 20 GHz (40–60 GHz). Multi-Gbps data rates are demonstrated with non-constant envelope modulations across the frequencies 40–60 GHz. [ABSTRACT FROM PUBLISHER]

An improvement to the load-pull technique for a large-signal design of a transistor amplifier is proposed. On the contrary to the current load-pull technique – a small-signal pre-matching on the output of the transistor is applied which results in reduced demands on a maximum VSWR of the tuner. This minimizes the launcher radiation in the K band and reduce measurement uncertainty. The proposed method has been verified on a design of 22 GHz large-signal amplifier using a Excelics EPA018A-70 transistor.

This paper reports an advanced time-domain methodology to investigate the device reliability and determine its safe operating area of AlGaN/GaN HEMTs. The presented technique is based on the continued monitoring of the RF waveforms and DC parameters in order to assess the degradation of transistor characteristics in RF power amplifiers. The reliability study is carried out in class AB operation, under RF operating excitation at high drain voltages and overdrive conditions (12 dB compression). The analysis is carried out with two different output load impedances: optimum of PAE and mismatched impedance. The results show a drift of RF performances due to a variation of electrical parameters. In particular, the operation with optimum PAE load impedance induces slight positive threshold voltage shift. The operation with mismatched load shows a stronger degradation, with a positive threshold voltage shift and a drop in saturation drain current, due principally to the high temperature reached by the devices during RF stress. [ABSTRACT FROM AUTHOR]

Impedance tuners are key instruments used for load- and source-pull measurements. They are crucial for any active microwave components, circuits, and systems characterization and optimization. This paper reports theoretical, simulated, and experimental results related to the development of a novel programmable impedance tuner offering high-voltage standing wave ratio (VSWR). After presenting the proposed tuner principle, a fabricated prototype operating at microwave frequencies and based on a 3.5 mm coaxial line is introduced with experimental results. Depending on the targeted frequency band, different pairs of slugs, with optimized length and characteristic impedance, can be used to obtain an optimal VSWR. This first prototype allowed us to demonstrate the interest of the proposed impedance synthesis principle and to identify ways forward to further improve its performances and push forward this promising technology. [ABSTRACT FROM AUTHOR]

In this paper, a new characterization method, which allows the determination of the time constants of traps in AlGaN/GaN high electron-mobility transistors is proposed. The approach is based on the current transient method for assessing the time constants that are involved in real working conditions. To do that the dc filling pulses, which are classically used in this method, are replaced by RF filling pulses, which reproduce the real large-signal conditions. To investigate the impact of large-signal working conditions on the trapping phenomena, on-wafer single-pulse load–pull characterizations are carried out at different temperatures and for two different output load impedances: maximum of power-added efficiency and mismatched impedance. The results obtained show the deep impact of the load-line excursion on the current collapse of the detrapping drain current. A comparison between the single-pulse RF load–pull characterization and single-pulse dc measurement is finally presented. [ABSTRACT FROM PUBLISHER]

We report on AlN/GaN double heterostructures for high frequency applications. 600 h preliminary reliability assessment has been performed on these emerging RF devices, showing promising millimeter-wave 100 nm gate length GaN-on-Si device stability for the first time. A 150 nm AlN/GaN double heterostructure has been developed and evaluated on SiC substrate. State-of-the-art CW power-added-efficiencies (PAE) up to 40 GHz have been achieved on ultrathin barrier (6 nm) GaN devices while operating at a drain bias exceeding 30 V. [ABSTRACT FROM AUTHOR]

Until recently, power amplifiers using LDMOS were Class-AB and Doherty type, and showed 55 % efficiency for narrowband of 60 MHz bandwidth. However, owing to the RRH application of base stations power amplifier module, a bandwidth expansion of at least 100 MHz and high efficiency power amplifiers of at least 60 % power efficiency are required. In this study, a Class-J power amplifier was designed by optimizing an output matching circuit so that the second harmonic load will contain a pure reactance element only and have broadband characteristics by using GaN HEMT. The measurements showed that a 45 W Class-J power amplifier with a power added efficiency of 60~75 % was achieved when continuous wave signals were input at 1.6~2.3 GHz, including W-CDMA application. [ABSTRACT FROM AUTHOR]