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n the rapidly evolving landscape of digital communication, ensuring data security remains a paramount concern. This research proposes a hybrid encryption technique that combines the strengths of Elliptic Curve Cryptography (ECC) and the Data Encryption Standard (DES) to enhance the security of data transmission. The hybrid model leverages the efficiency of DES for symmetric encryption and the robust security features of ECC for asymmetric encryption. The methodology involves first encrypting data using DES and subsequently applying ECC to the DES-encrypted output, thus providing a dual-layer encryption mechanism. The system was implemented using C# on Visual Studio and tested across five plaintext files ranging from 319 MB to 10,127 MB in size. The findings demonstrate that while the hybrid system slightly reduces throughput compared to using DES or ECC alone, it significantly enhances data security. Specifically, encryption throughput for DES was recorded at 64.53%, with ECC at 34.67%. Decryption throughput was 66.87% for DES and 67.86% for ECC, while the hybrid approach showed a balanced yet secure performance. The memory usage of the hybrid system, although higher, offers an acceptable trade-off for enhanced security, growing from 21.34 MB to 73.87 MB depending on the file size. The proposed hybrid approach provides a crucial balance between performance and security, offering a robust solution for secure data communication. It contributes significantly to the field by addressing the limitations of individual encryption algorithms, ensuring higher security at the cost of minimal performance reduction.

In order to meet the requirements of heterogeneous protocol integration and interconnection in software-defined interconnection systems, a two-stage multi-protocol switching circuit was proposed. This circuit accommodated the forwarding needs of various heterogeneous protocols by integrating shared memory and Crossbar architectures. In addition, a multi-stage arbitrary scheduling scheme based on time slot was introduced to decouple time and space during the scheduling. Simulation results demonstrate that this switching circuit can dynamically adapt to changes in switching scale, port memory, and port bandwidth requirements resulting from binding mode changes. Compared to traditional combined input and output queued (CIOQ) architecture, the utilization of memory is increased by up to 87.5%, and the forwarding delay is as low as tens of nanoseconds, making it suitable for RapidIO, fibre channel (FC), Ethernet, peripheral component interconnect express (PCIe) single protocol switching as well as hybrid protocol switching combining these protocols.

In cloud environments, optimization of resource utilizations is one among the predominant challenges. The two sub-research topics are cloud resource prediction and allocation. A few contributions to virtual machine (VM) placement techniques have been identified in the literature. In order to efficiently put up the virtual machine (VM) on the physical machine (PM), a Self Adaptive Immigrants with Genetic Algorithm (SAI-GA) is presented in this study. Based on CPU and memory usage, the proposed technique would forecast the best PM for each VM. The algorithm will adjust itself with the appropriate immigrant based on the history of past VM placement to find the best VM placement. In this paper, the VM live dataset from the CSAP lab at SNU in Korea has been used. For the purpose of demonstrating the significance of the findings, a number of non-parametric tests were used to evaluate how well the proposed SAI-GA performed. The outcomes demonstrate that the suggested approach makes a considerable contribution to the placement of VMs in cloud environments. [ABSTRACT FROM AUTHOR]

Robot perception heavily relies on camera-based visual input for navigating and interacting in its environment. As robots become integral parts of various applications, the need to efficiently compute their visibility regions in complex environments has grown. The key challenge addressed in this paper is to devise an innovative solution that not only accurately computes the visibility region V of a robot operating in a polynomial environment but also optimizes memory utilization to ensure real-time performance and scalability. The main objective of this research is to propose an algorithm that achieves optimal-time complexity and significantly reduces memory requirements for visibility region computation. By focusing on sub-linear memory utilization, the aim is to enhance the robot's ability to perceive its surroundings effectively and efficiently. Previous approaches have provided solutions for visibility region computation in non-spiral environments, but most were not tailored to memory limitations. In contrast, the proposed algorithm is designed to achieve optimal time complexity that is O(n) while reducing memory usage to O(c/ log n) variables, where c < n represents the number of pivot corners in the environment. Leveraging the near-constant-memory model and memory-constrained algorithm, the goal is to strike a balance between computational efficiency and memory usage. The algorithm's performance is rigorously evaluated through extensive simulations and practical experiments. The results demonstrate its linear-time complexity and substantial reduction in memory usage without compromising the accuracy of the visibility region computation. By efficiently handling memory constraints, the robot gains a cost-effective and reliable perception mechanism, making it well-suited for a wide range of real-world applications. The paper introduces a memory-efficient algorithm that boosts robot perception. By enhancing visibility computation in complex settings, our approach optimizes robot operation, promising progress in robotics, computer vision, and related domains. [ABSTRACT FROM AUTHOR]

Grid is the collection of geographically distributed computing resources. For efficient management of these resources, the manager must maximize its utilization, which can be achieved by efficient load balancing with Job Migration techniques.Job Migration from overloaded resources to underloaded is an attempt to load balancing across all processors, thus reduce average response time. The decision of migration is based on the information exchange between resources.In this paper, the authors propose a novel Job Migration Algorithm for Dynamic Load Balancing (JMADLB), in which parameters such as CPU load and queue length have been considered and have been used for the selection of overloaded resources (or underloaded ones) in Grid. Here, the overloaded resources do not accept any new job; but, the new jobs are migrated to underloaded resources, even though this mechanism migrate extra jobs to obtain load balancing. The performances of the proposed algorithms were tested in Alea 2 simulator by using different parameters like response time, resources utilization and waiting time in the global queue. In addition, they were compared with other scheduling algorithms such as First Come First Served (FCFS) and Earliest Deadline First (EDF).

FTL (Flash Translation Layer) is a memory block controller that manages the challenges of a data storage system based on flash memory technology. The design of internal parallelism in MLC-based SSDs with virtual blocks resulted in various challenges and due to the physical structure of flash memory cells based on MLC technology, it is possible to write a new page in a data block at the address after the last page is written. In parallel-based SSD design based on virtual blocks, some writes create unusable pages at the memory space, and these created holes reduce memory efficiency; consequently, it reduces the life-time of memory blocks by creating more operations, and accelerates garbage collection and merging operations. The proposed FTL offers three steps to address this constraint. Firstly, an idea was proposed to prevent costly transitions and to distribute data more evenly at memory blocks (wear leveling). Secondly, the unused holes created in virtual blocks became much fewer resulting in increased utilization of memory space. At last, a policy was proposed to prevent update blocks (log blocks) from being blocked and to postpone the merging and garbage collection by which the memory lifetime increases significantly. Simulation results showed that the number of unused erased pages and the number of extra write operations decreased up to 23% and 17%, respectively. In addition, the number of invalid released pages increased up to 21% in the proposed FTL, and the speed of I/O executions to 3%.

Summary: Data Deduplication is the foremost technique used for data compression by removing redundant data. It is broadly utilized for cloud storage server, which reduces the un‐utilized memory space and optimized bandwidth. The confidentiality of sensitive information maintains during Deduplication detection. The Efficient Hash Function–based Duplication Detection (EHFDD) algorithm is proposed to encrypt the content before outsourcing in cloud environment. This paper is an attempt to enhance the data security and notify the issues of approved data Deduplication detections. Furthermore, it also presents several novel Deduplication improvisations for helping certified duplicate verification in hybrid cloud. The EHFDD method enables duplicate detection scheme with minimal overhead compared to existing functions. Based on experimental evaluations, proposed EHFDD algorithm reduces the average delay in 28.7 milliseconds, memory utilization in 8%, computation time in 457 milliseconds, communications overhead in 900 milliseconds, and improves the success rate in 3.13%. [ABSTRACT FROM AUTHOR]

The increasing importance of inference algorithms, such as neural networks (NNs), principle component analysis (PCA), and singular value decomposition (SVD), etc., has led to the emergence of hardware accelerators to address power-performance tradeoffs in their implementation. Their large data sets make DRAM access the bottleneck for power and performance. Private SRAM scratch-pad memory is used to mitigate the DRAM access penalty but it is a limited resource in size and bandwidth. Thus, accelerator design is not just about computation, but also how data flow is scheduled across the memory hierarchy, including DRAM, scratch-pad SRAM, and datapath registers. Current accelerator design tools automate the generation of customized datapaths to improve performance, but have limited support for reducing DRAM/SRAM accesses during the computation. In this paper, we propose a memory-driven accelerator design methodology for large-scale inference applications, to maximize data access in the datapath and SRAM. We demonstrate its efficacy using several key kernels from large-scale inference applications. [ABSTRACT FROM AUTHOR]

Virtual Machine (VM) consolidation is a crucial process in improving the utilization of the resource in cloud computing services. As the cloud data centers consume high electrical power, the operational costs and carbon dioxide releases increases. The inefficient usage of the resources is the main reason for these problems and VM consolidation is a viable solution. VM consolidation includes host overload/under-load detection, VM selection and VM placement processes. Most existing host overload/under-load detection approaches of VM consolidation uses CPU utilization only for the determining host load. In this paper, three resources namely CPU utilization, memory utilization and bandwidth utilization are used for host overload detection and an adaptive regression based model called Multiple Regression Multi-Objective Seven-Spot Ladybird Optimization (MR-MOSLO) is proposed. This model is based on combining the benefits of adaptive threshold based and regression based host overload detection algorithms. This approach of combining these features provide more advantages for threshold setting in dynamic environments with accurate prediction of host overloading. For this purpose, initially, Multiple Regression (MR) algorithm is used which relay on CPU utilization, memory utilization and bandwidth utilization for estimation of the host load conditions. Then a Multi-Objective Seven-Spot Ladybird Optimization (MOSLO) algorithm is introduced to select the upper and lower threshold limits for host utilization. Based on these algorithms, the host overload/underload is detected with high accuracy and less power consumption. The simulations are conducted in CloudSim tool and the empirical results shows that the proposed MR-MOSLO algorithm detects the host overload efficiently. The results obtained for 25 hosts, 30 VMs and 500 tasks, are: SLATAH is 20.0434, PDM is 8.7E-4, SLAV is 3.7E-5 and ESV is 10.962 which are lesser than the other methods. Though the energy of 15.4 kWh and SLA of 0.00757 are negligibly higher than some of the existing methods, the proposed approach provided comparatively better performance. [ABSTRACT FROM AUTHOR]

Detection of malware has become more challenging today because of the advancements and technologies adapted to corrupt the network or the devices. Static, dynamic and hybrid malware detection analysis methods have failed to provide complete malware detection. Hence in this work, a bio inspired sequence alignment method used in bioinformatics to compare the similarity between amino acid sequences in protein structures has been adapted to give the best similarity score to detect malwares. The state of art sequence alignment methods like Smith Water Man Algorithm (SWMA) used in bio informatics suffers from the problem of more memory utilization and computation time which is in the order of n2 ie., (O(n2)) and hence in this work an efficient sequence alignment algorithm (ESSA) has been proposed to address the problem of memory utilization thereby making the memory utilization and computation time to the order of n ie., (O(n)) there by making the detection rate higher. It is also clear from the results that the similarity score is high when the sequence length is small. The accuracy of the prediction rate of malware and benign increases. [ABSTRACT FROM AUTHOR]

Security is one of the major concerns in generic computing system which is used in our day to day life to deal with various aspects like education, banking, communication, entertainment etc. Security is obtained to prevent threats that usually affect the end users of other areas as well (like grid computing, cloud computing etc.). Malicious code deployment is the main cause of threat. This paper mainly proposes a novel malicious code detection technique (Rule based probabilistic malware detection (RBPMD)) which provides security in the traditional computing system. In this paper, RBPMD technique follows a rule based probabilistic technique to detect the malicious codes among several codes and warn the other non-infected guest machines about it. A prototype of RBPMD is designed and implemented in this paper. It creates less overhead as well as occupies less storage space compare to other well-known anti-viruses. Its implementation cost is also low compare to others. At last, a comparison analysis of this proposed technique is given with other popular malware detection techniques. [ABSTRACT FROM AUTHOR]

-A code smell is a hint or the description of a symptom that something has gone wrong somewhere in your code. These are commonly occurring patterns in source code that indicate poor programming practice or code decay. The presence of code smells can have a severe impact on the quality of a program, i.e. making system more complex, less understandable and cause maintainability problem. Herein, an automated tool have been developed that can rectify code smells present in the source code written in java, C# and C++ to support quality assurance of software. Also, it computes complexity, total memory utilized/wastage, maintainability index of software. In this research paper an approach used for the design and implementation of testing tool for code smell rectification is discussed and is validated on three different projects. [ABSTRACT FROM AUTHOR]

It is known that the locality of reference of a program can be improved by restructuring it. One approach for program restructuring is to rearrange the order of relocatable program sectors and to repackage those sectors of a program, that are needed within a relatively short time of one another, into the same virtual page. This approach needs no reprogramming of the source program. However, microscopic analysis of the internal structure of repackaged sectors often shows the existence of sectors only few portions of which are actually referenced while the sectors are in use. In this paper we propose to measure the efficiency of sector usage by a measurable index called the sector utilization ratio. This is roughly defined to be the ratio of the size of the memory space referenced within a sector to the sector's size while the sector is in use. We calculate the sector utilization ratio for more than 600 relocatable program sectors, which are taken from the virtual memory operating system of HITAC 8700/8800 and its Fortran compiler. The relationships between a sector utilization ratio and the sector size, and those between the sector utilization ratio and the sector structure are analyzed. From this analysis, structures for sectors with a high ratio of memory utilization are clarified. Moreover, we conclude that improving the memory utilization of each sector appears to have a significant effect on the total program's locality. [ABSTRACT FROM AUTHOR]

Overflow of data streams are gathered and manipulated in sensor networks, communication networks, Internet traffic, and online transaction in financial market, power grids, and industry production processes, scientific and engineering experiments to yield better analysis. In contrast to conventional data sets, stream data have infiltrated from systems temporally ordered, rapidly fluctuated, massive and potentially infinite. It would be potentially cumbersome and very exponential to store the entire data streams or scan through it multiple times due to its tremendous volume. This paper proposes the strategies to mine maximal data items and its data itemsets in single scan. Besides it generates association rules based on top maximal itemsets and data itemsets, which contain current and useful information for effective data analysis. [ABSTRACT FROM AUTHOR]

Summary: As parallel applications running on large‐scale computing systems become increasingly memory constrained, the ability to attribute memory usage to the various components of the application is becoming increasingly important. We present the design and implementation of memnesia, a novel memory usage profiler for parallel and distributed message‐passing applications. Our approach captures both application– and message‐passing library–specific memory usage statistics from unmodified binaries dynamically linked to a message‐passing communication library. Using microbenchmarks and proxy applications, we evaluated our profiler across three Message Passing Interface (MPI) implementations and two hardware platforms. The results show that our approach and the corresponding implementation can accurately quantify memory resource usage as a function of time, scale, communication workload, and software or hardware system architecture, clearly distinguishing between application and MPI library memory usage at a per‐process level. With this new capability, we show that job size, communication workload, and hardware/software architecture influence peak runtime memory usage. In practice, this tool provides a potentially valuable source of information for application developers seeking to measure and optimize memory usage. [ABSTRACT FROM AUTHOR]