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Hydraulic solenoid valves (HSVs) are widely used for fluid control in industrial applications. Like other mechanical parts, HSVs deteriorate and faults occur during their use in industrial settings. Although several prior fault-diagnosis methods have been proposed to detect these faults, previous studies have not considered the actual implementation of the methods on the controller. Thus, to ensure reliable operation of HSVs in the field, this research paper presents an innovative HSV controller design that is able to process the proposed fault-diagnosis algorithm. In the proposed work, the hardware is designed to transmit and receive signals and data for the valve-diagnosis algorithm. For the software, an architecture is proposed to enable the fault-diagnosis algorithm to be processed in a conventional microprocessor. In this research, the proposed controller design was built and tested on an actual hydraulic system. The results show that the proposed fault-diagnosis algorithm has been successfully embedded in the microcontroller. [ABSTRACT FROM AUTHOR]

The work presented in this paper regards the improvement of a housekeeping system for data acquisition of a suborbital vehicle (VIRIATO rocket or launcher). The specifications regarding the vehicle are presented and hardware is chosen accordingly, considering commercial off-the-shelf components. Mechanical and thermal simulations are performed regarding the designed system and a physical prototype is manufactured, assembled and programmed. Functional and field test results resorting to unmanned aerial vehicles, as well as the system's integration within VIRIATO project's mock-up vehicle, are presented. These tests demonstrate the viability of this system as an independent data acquisition system, and simulation results show that commercial off-the-shelf components have the capability of surviving expected launch environments. [ABSTRACT FROM AUTHOR]

In mammalian cells, primary miRNAs are cleaved at their hairpin structures by the Microprocessor complex, whose core is composed of DROSHA and DGCR8. Here, we show that 5′ flanking regions, resulting from Microprocessor cleavage, are targeted by the RNA exosome in mouse embryonic stem cells (mESCs). This is facilitated by a physical link between DGCR8 and the nuclear exosome targeting (NEXT) component ZCCHC8. Surprisingly, however, both biochemical and mutagenesis studies demonstrate that a variant NEXT complex, containing the RNA helicase MTR4 but devoid of the RNA-binding protein RBM7, is the active entity. This Microprocessor-NEXT variant also targets stem-loop-containing RNAs expressed from other genomic regions, such as enhancers. By contrast, Microprocessor does not contribute to the turnover of less structured NEXT substrates. Our results therefore demonstrate that MTR4-ZCCHC8 can link to either RBM7 or DGCR8/DROSHA to target different RNA substrates depending on their structural context. [Display omitted] • A variant NEXT complex of MTR4 and ZCCHC8 interacts with the Microprocessor complex • RBM7 is absent from the variant NEXT (vNEXT) complex • vNEXT-Microprocessor targets 5' flanks of pre-miRNAs • Structured RNAs, independent of miRNAs, are targeted by vNEXT-Microprocessor Imamura et al. reveal a physical and functional link between the Microprocessor complex, responsible for pre-miRNA processing, and a variant NEXT complex, involved in RNA decay. Together, these complexes degrade the 5' flanks of pre-miRNAs and other stem-loop-containing RNAs. [ABSTRACT FROM AUTHOR]

MicroRNA (miRNA) biogenesis is initiated upon cleavage of a primary miRNA (pri-miRNA) hairpin by the Microprocessor (MP), composed of the Drosha RNase III enzyme and its partner DGCR8. Multiple pri-miRNA sequence motifs affect MP recognition, fidelity, and efficiency. Here, we performed cryoelectron microscopy (cryo-EM) and biochemical studies of several let-7 family pri-miRNAs in complex with human MP. We show that MP has the structural plasticity to accommodate a range of pri-miRNAs. These structures revealed key features of the 5′ UG sequence motif, more comprehensively represented as the "flipped U with paired N" (fUN) motif. Our analysis explains how cleavage of class-II pri-let-7 members harboring a bulged nucleotide generates a non-canonical precursor with a 1-nt 3′ overhang. Finally, the MP-SRSF3-pri-let-7f1 structure reveals how SRSF3 contributes to MP fidelity by interacting with the CNNC motif and Drosha's Piwi/Argonaute/Zwille (PAZ)-like domain. Overall, this study sheds light on the mechanisms for flexible recognition, accurate cleavage, and regulated processing of different pri-miRNAs by MP. [Display omitted] • The Microprocessor has the plasticity for accommodating a diversity of pri-miRNAs • RNA drives Microprocessor domain repositioning for pri-let-7 cleavage • The UG motif is redefined as a fUN motif for a comprehensive pri-miRNA classification • SRSF3 assists Drosha by positioning it at the basal junction of the pri-miRNA Garg et al. used cryo-EM to determine several structures of different pri-let-7 pri-miRNAs in complex with the Microprocessor, highlighting structural features important for flexible recognition, pri-miRNA cleavage, and cleavage regulation. The fUN structural motif and CNNC-SRSF3-assisted Drosha loading present insights applicable to the processing of hundreds of pri-miRNAs. [ABSTRACT FROM AUTHOR]

This study examines the efficiency of a microprocessor's cooling system and maintaining the optimal temperature of electronic components. To do this, experiments are carried out on the existing cooling system of the microprocessor with control of all main parameters, primarily such as the temperature and coolant flow, as well as the performance and temperature of the processor. Based on the data obtained, a mathematical model is built that describes the change in the microprocessor's power and allows us to calculate the temperatures and speeds of coolants, as well as obtain the most effective modes for the operation of the cooling system. The obtained experimental data and mathematical model make it possible to predict the required power of the cooling system and the operating parameters of microelectronic components, which is especially important when new generations of microprocessors with the highest performance appear. The data obtained also makes it possible to calculate parameters for existing processors in order to maximize the efficiency and reliability of their operation, which is also relevant for other electronic devices, in particular microcontrollers. [ABSTRACT FROM AUTHOR]

Electricity demand is rapidly increasing in many countries especially because of the increase in smart appliances, smart cities, and communities. The use of electricity ranges from agricultural load, to commercial and industrial load, and also residential load which account for the largest contributor to the increase in peak demand. Thus, residential consumers play a massive role in the national demand for electrical energy and power. The increased demand puts increasing pressure on the energy suppliers who force consumers to cope with short peaks. The need arises for an energy management technique to reduce energy consumption by allowing for consumer load control. The method explores using a Raspberry Pi to collect and evaluate the energy consumed over time and allow consumers access to directly control their home appliances. A more accurate load curve is deduced using the new readings gotten from the end-users. The data obtained from the proposed system is sent to a progressive web application that allows users manage their energy consumption. [ABSTRACT FROM AUTHOR]

A digitizer is considered one of the fundamental components of an earthquake monitoring system. In this paper, we design and implement a high accuracy seismic digitizer. The implemented digitizer consists of several blocks, i.e., the analog-to-digital converter (ADC), GPS receiver, and microprocessor. Three finite impulse response (FIR) filters are used to decimate the sampling rate of the input seismic data according to user needs. A graphical user interface (GUI) has been designed for enabling the user to monitor the seismic waveform in real time, and process and adjust the parameters of the acquisition unit. The system casing is designed to resist harsh conditions of the environment. The prototype can represent the three component sensors data in the standard MiniSEED format. The digitizer stream seismic data from the remote station to the main center is based on TCP/IP connection. This protocol ensures data transmission without any losses as long as the data still exist in the ring buffer. The prototype was calibrated by real field testing. The prototype digitizer is integrated with the Egyptian National Seismic Network (ENSN), where a commercial instrument is already installed. Case studies shows that, for the same event, the prototype station improves the solution of the ENSN by giving accurate timing and seismic event parameters. Field test results shows that the event arrival time and the amplitude are approximately the same between the prototype digitizer and the calibrated digitizer. Furthermore, the frequency contents are similar between the two digitizers. Therefore, the prototype digitizer captures the main seismic parameters accurately, irrespective of noise existence. [ABSTRACT FROM AUTHOR]

According to the World Health Organization, 430 million individuals, or more than 5% of the world's population, need hearing loss rehabilitation. They also estimate that by 2050, one in ten individuals, or over 700 million people, would suffer hearing loss, that is incapacitating. Despite these difficulties, technological developments have made it feasible to enhance these people's quality of life. The Real-time Smart Auditory Assistive Wearable (RESAAW), is a revolutionary gadget that aids people with hearing problems by employing omnidirectional microphones to record real-time surrounding noises. In the case of abrupt or harmful noises, the gadget gives the user tactile input while employing advanced digital signal processing and machine learning models to distinguish vital sounds from background noise. The goal of RESAAW is to use 4 omnidirectional microphones that constantly pick up noises in the vicinity of the individual wearing it and filter the noises using digital signal processing techniques ML models. There are people with different degrees of hearing loss. This system would be a boon to them in their work places. [ABSTRACT FROM AUTHOR]

This paper focuses on designing a 32-bit Reduced Instruction Set Computer (RISC) Scalable Processor Architecture (SPArc) subset gener al purposes processor. The design process covers instructions selection, Register Transfer Notation (RTN) design, Datapath Design, and Control Unit Design. Basic integer instruction was selected. Datapath was designed along with the RTN with a five-stage pipeline with direct connection between stages. This design was then validated using functionality simulation test and implemented in Field Programmable Gate Array (FPGA). The performance of the processor was measured using thermal report, power report, and time report. Functional test shows that the Processor can execute instructions as designed, which are Arithmetic/Shift/Logic, Control Transfers, and Memory access instructions. It was validated with the register content and signal generated in each stage. The design was also successfully implemented in FPGA with the maximum clock of 58 MHz as the synthesis report shows. Thermal report shows the thermal properties of the design, which shown the acceptable thermal margin of 56.9 ⁰C and junction temperature of 28.1 ⁰C. The power report shows the low power consumption of 0.266 W, which consists of dynamic power of 0.173 W and static power of 0.093 W. This work enables further development and to be used as master processor in System on Chip design of special purpose processors like cognitive processors. [ABSTRACT FROM AUTHOR]

One of the main difficulties in designing high-performance microprocessors is power consumption. Each CPU generation's tremendous increase in complexity and speed is beyond the advantages of feature size and voltage reduction scaling. Therefore, it's constantly a challenge for designers to come up Utilizing novel power-saving techniques while attempting to meet all the additional restrictions placed on the design. Power dense ties in electronic devices, and particularly in microprocessor chips, have increased during the last few decades. The heat problems within electronic circuits have dramatically increased as a result of the ongoing trend of decreasing device size. So, efforts to create materials and techniques to address thermal concerns within the processing unit began. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The display of the future is multimodal, integrating optical sensors, RFID antennas, ultrasound transducers, etc. The sensors produce a large amount of redundant data, which should be preprocessed on the substrate, ideally on the backpanel. Control gates and select and data drivers need to be more configurable and partitionable to create operational flexibility. This paper presents various circuit blocks for processing and control, including operational amplifiers, high‐resolution analog‐to‐digital converters, a microprocessor, DC‐DC converters, and high resolution sensor pixel array architectures. Moreover, the performance of the basic building blocks is compared in LTPS and IGZO technology. [ABSTRACT FROM AUTHOR]