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Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

In this article, we propose a novel chaotic neuron circuit with memristive neural synapses, construct an architecture of memristive chaotic neural network (MCNN) and implement associative memory application of bipolar images. The proposed neuron circuit mainly consists of synapse module and neuron module with chaotic dynamics characteristics. The synapse module is composed of memristors which represent synaptic weights. The neuron module employs voltage feedback operational amplifiers to accomplish integral operation and output function. MCNN utilizes a memristor crossbar array to perform matrix operations and can process the information in parallel. In addition, the proposed circuit of MCNN can accomplish continuous recursive operations and meet different applications due to the programmability of the memristor. The ex-situ method is utilized to train the memristor crossbar array. Furthermore, the associative memory applications of bipolar images are carried out based on the constructed circuits of MCNN with three and nine neurons. The simulation results in PSPICE software testify the functions of the MCNN circuit.

The most important aspect of an artificial neuron circuit is energy consumption. An analog neuron circuit has a critical problem in that the energy consumption in the steady-state due to a short-circuit current in the first inverter is quite large. In this study, we first demonstrated an adaptive neuron circuit with a dual-gate positive feedback field-effect transistor (FBFET) and fabricated a neuron circuit by co-integrating the FBFET and a complementary metal-oxide semiconductor (CMOS) in a chip. The fabricated FBFET has an extremely low sub-threshold slope of less than 0.5 mV/dec and a low off current. The threshold voltage of the FBFET can be precisely controlled by the second gate bias. By adjusting the second gate bias, it is possible to implement spike-frequency adaptive characteristics in the neuron circuit. Moreover, the proposed neuron circuit with the FBFET can significantly reduce the power dissipation. In the neuron circuit, a short-circuit current is suppressed by adopting the FBFET in the first inverter. In a modified inverter with the FBFET, more than 50% total energy consumption was reduced by the FBFET. We implemented the modified inverter in which the FBFET is connected in parallel with an N-channel metal-oxide semiconductor. Moreover, we utilized the neural frequency adaptation characteristics in the neuron circuit by adjusting the threshold voltage of the FBFET. Finally, we analyzed the fabricated FBFET neuron circuit operation and power consumption compared to a conventional CMOS neuron circuit.

Spike-timing-dependent plasticity (STDP) is a fundamental synaptic learning rule observed in biology that leads to numerous behavioral and cognitive outcomes. Emulating STDP in electronic spiking neural networks with high-density memristive synapses is, therefore, of significant interest. While one popular method involves pulse-shaping the spiking neuron output voltages, an alternative approach is outlined in this article. The proposed STDP implementation uses time-varying dynamic resistance [ ${R}$ ( ${t}$ )] elements to achieve local synaptic learning from spike-pair STDP, spike triplet STDP, and firing rates. The ${R}$ ( ${t}$ ) elements are connected to each neuron circuit, thereby maintaining synaptic density and leveraging voltage division as a means of altering synaptic weight (memristor voltage). Example ${R}$ ( ${t}$ ) elements with their corresponding behaviors are demonstrated through simulation. A three-input-two-output network using single-memristor synaptic connections and ${R}$ ( ${t}$ ) elements is also simulated. Network-level effects, such as nonspecific synaptic plasticity, are discussed. Finally, spatiotemporal pattern recognition (STPR) using ${R}$ ( ${t}$ ) elements is demonstrated in simulation.

Purpose The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model. Design/methodology/approach Numerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board. Findings With the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit. Originality/value Without any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.

Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network’s performance realized with the nonideal memristor crossbar. To avoid performance degradation due to the parasitic-resistance-related nonideal effects, adaptive training methods were proposed previously. However, the complicated training algorithm could add a heavy computational burden to the neural network hardware. Especially, the hardware and algorithmic burden can be more serious for edge intelligence applications such as Internet of Things (IoT) sensors. In this paper, a memristor-CMOS hybrid neuron circuit is proposed for compensating the parasitic-resistance-related nonideal effects during not the training phase but the inference one, where the complicated adaptive training is not needed. Moreover, unlike the previous linear correction method performed by the external hardware, the proposed correction circuit can be included in the memristor crossbar to minimize the power and hardware overheads for compensating the nonideal effects. The proposed correction circuit has been verified to be able to restore the degradation of source and output voltages in the nonideal crossbar. For the source voltage, the average percentage error of the uncompensated crossbar is as large as 36.7%. If the correction circuit is used, the percentage error in the source voltage can be reduced from 36.7% to 7.5%. For the output voltage, the average percentage error of the uncompensated crossbar is as large as 65.2%. The correction circuit can improve the percentage error in the output voltage from 65.2% to 8.6%. Almost the percentage error can be reduced to ~1/7 if the correction circuit is used. The nonideal memristor crossbar with the correction circuit has been tested for MNIST and CIFAR-10 datasets in this paper. For MNIST, the uncompensated and compensated crossbars indicate the recognition rate of 90.4% and 95.1%, respectively, compared to 95.5% of the ideal crossbar. For CIFAR-10, the nonideal crossbars without and with the nonideal-effect correction show the rate of 85.3% and 88.1%, respectively, compared to the ideal crossbar achieving the rate as large as 88.9%.

International audience; Aerospace applications are attractive candidates to embed Artificial Neural Networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing the radiation hardening characteristics of a neural circuit before operating in harsh environments. A possible solution to substantially reduce long-term spurious effects caused by ionizing radiation (referred to as Total Ionizing Dose-TID) is to change the conventional rectangular MOS gate geometry to a non-standard topology referred to as Enclosed Layout Transistor (ELT). In the context of hardening a complete neuron circuit against TID effects, together with the well-established ELT paradigm, it is possible to exploit the inclusion of other hardened devices, for instance, the memory element. In this sense, the Oxide-based Resistive Random Access Memory (OxRAM) can be used as the memory element, which is inherently tolerant against ionizing radiation, and, hence, better suited for a fully hardened circuit. In this work, we propose to harden the design of an existing OxRAMbased neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180 nm technology, have been carried out to validate our proposed design. Additionally, we exploit two simulation setups. First, the OxRAM's behavior in a simple circuit configuration, to provide a better understanding of the OxRAM device. Second, the OxRAM-based neuron circuit, to evaluate the behavior of the proposed neuron circuit hardened with ELTs. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

Low-power neuromorphic hardware is indispensable for edge computing. In this study, we report the simulation results of a spiking neuron circuit. The circuit based on the Izhikevich neuron model is designed to reproduce various types of spikes and is optimized for low-voltage operation. Simulation results indicate that the proposed circuit successfully operates in the subthreshold region and can be utilized for reservoir computing.

Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.

Hybrid memristor-CMOS techniques have been recently proposed to build large-scale neural networks with learning capabilities. The intrinsic characteristics of memristors make them specially suited to implement synaptic connections between layers of spiking neurons, undergoing STDP learning (Spike-Timing-Dependent Plasticity) mechanisms when processing spikes with particular shapes. In a previous work, we proposed a tunable spiking neuron circuit which can generate spikes with controllable shape. In this work, the spike generator circuit has been implemented in FDSOI 28nm technology, and it has demonstrated its capability to produce spikes with pulse widths in the range between $8\mu {s}$ and 100ms.

International audience; Brain-inspired computing architectures, brought by Artificial Neural Networks (ANNs), are an attractive solution to reduce the energy consumption of the conventional von Neumann's computation, with an excellent parallel processing capability. Therefore, critical applications, such as Space & Satellite, which impose severe constraints in terms of power consumption and computing efficiency, are excellent candidates to embed such networks. Nonetheless, integrated circuits operating during long-term and cumulative exposure to incidence levels of ionizing radiation may have their physical components degraded, thus drastically reducing their reliability and expected lifetime. A possible solution to enhance the radiation hardening characteristics of a conventional bulk CMOS device is to use the non-standard gate geometry referred to as Enclosed Layout Transistor (ELT). In this work, we propose to harden the design of an existing OxRAM-based neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180 nm technology, have been carried out to validate our proposed design. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

To address the ever-increasing computational demands of machine learning applications, neuromorphic computing has emerged as a possible solution. The goal is to design a platform able to mimic the processing strategies of the brain. A neuromorphic system is composed by artificial neurons and synapses implemented in hardware with high level of integration. Such implementations entail challenges including power-efficiency, compactness and biophysical resemblance. This work proposes a new implementation of a neuron circuit, initially introduced by Wijekoon and Dudek. We show that the proposed neuron, designed in a standard 0.18µm CMOS process, consumes 58.5fJ/spike at 0.2V supply voltage. The area covered by the circuit is 16.8% of the area of the state-of-the-art implementation. This result was achieved by lowering the membrane capacitance and the number of transistors. In addition, spiking activity unfolds on a biological time scale - rather than accelerated. The circuit preserves the possibility of being adjusted by external biases to attain different firing patterns.

A perpendicular spin transfer torque (p-STT)-based neuron was developed for a spiking neural network (SNN). It demonstrated the integration behavior of a typical neuron in an SNN; in particular, the integration behavior corresponding to magnetic resistance change gradually increased with the input spike number. This behavior occurred when the spin electron directions between double Co2Fe6B2 free and pinned layers in the p-STT-based neuron were switched from parallel to antiparallel states. In addition, a neuron circuit for integrate-and-fire operation was proposed. Finally, pattern-recognition simulation was performed for a single-layer SNN.

In this paper, we proposed the current mirror based neuron circuit with the cascode structure added. Adding a cascode structure reduces the current fluctuation due to the membrane potential. And we compared two type of the neuron circuit in comparative operation, using inverters and a comparator. And we proposed the more efficient type of neuron circuit in terms of power consumption.

Neuromorphic circuits are becoming quite popular due to their ability to mimic the structure and behavior of human brain. Current research focuses on approximating spiking biological neuron behavior. Various neuron models have been proposed in the past that aid in investigating the behavior of neuronal systems mathematically. Mihalas–Niebur (MN) neuron model is one among them. In this paper log-domain based MN neuron model is implemented at 45 nm technology node. The paper studies the effects of process-temperature variations and also investigates the impact of Hot Carrier Injection (HCI), Bias Temperature Instability (BTI) on the performance of MN circuit. Average power consumption and spiking frequency are chosen as key performance measures to analyze the circuit performance before and after degradation.

Spiking neural networks (SNNs) are widely used in many fields because they work closer to biological neurons. However, due to its computational complexity, many SNNs implementations are limited to computer programs. First, this paper proposes a multi-synaptic circuit (MSC) based on memristor, which realizes the multi-synapse connection between neurons and the multi-delay transmission of pulse signals. The synapse circuit participates in the calculation of the network while transmitting the pulse signal, and completes the complex calculations on the software with hardware. Secondly, a new spiking neuron circuit based on the leaky integrate-and-fire (LIF) model is designed in this paper. The amplitude and width of the pulse emitted by the spiking neuron circuit can be adjusted as required. The combination of spiking neuron circuit and MSC forms the multi-synaptic spiking neuron (MSSN). The MSSN was simulated in PSPICE and the expected result was obtained, which verified the feasibility of the circuit. Finally, a small SNN was designed based on the mathematical model of MSSN. After the SNN is trained and optimized, it obtains a good accuracy in the classification of the IRIS-dataset, which verifies the practicability of the design in the network.

The pure circuit implementation of STDP is a worthwhile work. In this study, a novel spiking neuron circuit and STDP learning circuit based on memristors are designed. The proposed spiking neuron circuit, which is based on conventional leaky integrate-and-fire neuron and utilizes the nonlinear variation of memristance, is served to generate spikes. Different release thresholds and amplitudes of the spikes can be obtained through tuning circuit parameters. Extending on the spiking neuron circuit, a STDP learning circuit is built to perform unsupervised learning behaviors. Furthermore, a crossbar array architecture is finally considered to fabricate multi-input multi-output spiking neural network which also perform STDP learning effectively. Circuit simulation results in PSPICE prove the availability of the two proposed circuits.

Adaptive response to timely constant stimuli is a common feature of biological neurons. Implementation of neurons with such features is important for achieving biologically plausible networks using electronic systems. Emerging memristor devices open new horizons in electronically implementation of neural networks with high integration density and low power consumption. Promising potential applications can be considered for mem-elements (memristor, memcapacitor, and meminductor) with their built-in memory-properties. Since the dynamics of mem-elements makes them suitable for direct emulation of biological features of real neurons, it is expected that implementation of real neurons with complicated behavior to be straightforward using mem-element without complicating the implementation of the whole neuron circuit. Mem-elements are still unavailable commercially, so we utilize the mem-elements emulators to evaluate the feasibility of using these elements in the implementation of adaptive neurons. To ensure that there is the possibility of practical implementation of our neuron circuit, we used mem-elements emulators in SPICE simulations instead of mem-elements behavioral models. This work is among the first papers in the implementation of adaptive neurons using mem-elements. Here, using memristor and memcapacitor emulators the neuristor with adaptive behavior is implemented in SPICE environment. We use two different methods for induction of adaptive behavior to the neuristor response. In the first method, the capacitor in the primary circuit of neuristor is replaced with memcapacitor. Alternatively, the coupling resistor in the primary circuit of neuristor is replaced with the memristor in the second method. Results show that, the feature of memristor/memcapacitor in changing its resistance/capacitance during time upon excitation with current or voltage, makes the neuristor behavior to be adaptive in both methods, i.e. the neuristor shows the spike-frequency adaptation behavior in response to the continuous external stimulus, where the frequency of generated spikes depends on the duration of the external input stimulus.

The nonvolatility and resistance variability of memristor make it a candidate for emulating complex dynamic behaviors in the neural system. In this paper, the memristive neuron with homeostatic plasticity is implemented. The memristor is applied to the neuron circuit, and its memristance represents the membrane sensibility of neurons. Composed of a trigger module, a pulse generation module and a feedback module, the memristor-based neuron can adaptively adjust the firing rate of neuron and maintain it in the inherent firing rate range, which shows similarities to its biological counterpart. The proposed design can mimic firing rate behaviors of the electrophysiological experiment performed in rodent, where the homeostatic plasticity of neuron is inhibited by sleep signal and promoted by wake signal. Furthermore, all the simulations are conducted in Cadence PSPICE, and the functionality of the design is proved with the simulation.

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

We have developed a cellular neural network formed by simplified processing elements composed of thin-film transistors. First, we simplified the neuron circuit into a two-inverter two-switch circuit and the synapse device into only a transistor. Next, we composed the processing elements of thin-film transistors, which are promising for giant microelectronics applications, and formed a cellular neural network by the processing elements. Finally, we confirmed that the cellular neural network can learn multiple logics even in a small-scale neural network. Moreover, we verified that the cellular neural network can simultaneously recognize multiple simple alphabet letters. These results should serve as the theoretical bases to realize ultra-large scale integration for brain-type integrated circuits.

We present a low-power compact circuit for the event-driven readout of tactile sensors. The taxel is based on the POSFET device, a sensotronic unit where a piezo-electric material is deposited on the gate of a transistor, integrated with a Leaky-Integrate and Fire neuron circuit. This device encodes the applied force with trains of digital pulses, using the asynchronous Address Event Representation protocol. The instantaneous output spiking frequency is directly proportional to the force applied to the taxel. We show a full characterization of the device as well as quantitative measurements from a prototype fabricated on AMS CMOS 350-nm process. The taxel can reliably distinguish applied forces from 0.1 N up to 1.5 N.

The authors present a spike-triggered adaptive neuron circuit with input current modulation. Unlike adaptive neuron circuits where adaptation is realised by leakage modulation, the circuit presented in this Letter modulates the input current to membrane capacitor. Therefore, it is possible to reduce extra power consumption originating from increased leakage. Threshold voltage modulation of silicon on insulator (SOI) MOSFET by back gate effect is used to change the amount of injected current for the same input voltage. Through this method, the circuit in this work consumed 25.9% less power than the one modulating leakage.