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Copyright of Journal of Southeast University / Dongnan Daxue Xuebao is the property of Journal of Southeast University Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The parallel simulation of Spiking Neural P systems is mainly based on a matrix representation, where the graph inherent to the neural model is encoded in an adjacency matrix. The simulation algorithm is based on a matrix-vector multiplication, which is an operation efficiently implemented on parallel devices. However, when the graph of a Spiking Neural P system is not fully connected, the adjacency matrix is sparse and hence, lots of computing resources are wasted in both time and memory domains. For this reason, two compression methods for the matrix representation were proposed in a previous work, but they were not implemented nor parallelized on a simulator. In this paper, they are implemented and parallelized on GPUs as part of a new Spiking Neural P system with delays simulator. Extensive experiments are conducted on high-end GPUs (RTX2080 and A100 80GB), and it is concluded that they outperform other solutions based on state-of-the-art GPU libraries when simulating Spiking Neural P systems. [ABSTRACT FROM AUTHOR]

Traditionally, parallel discrete-event simulations of agent-based models in continuous time are organized around logical processes exchanging time-stamped events, which clashes with the properties of models in which tightly coupled agents frequently and instantaneously access each other's states. To illustrate the challenges of such models and to derive a solution, we consider the domain-specific modeling language ML3, which allows modelers to succinctly express transitions and interactions of linked agents based on a continuous-time Markov chain (CTMC) semantics. We propose synchronous optimistic synchronization algorithms tailored toward simulations of fine-grained interactions among tightly coupled agents in highly dynamic topologies and present implementations targeting multicore central processing units (CPUs) as well as many-core graphics processing units (GPUs). By dynamically restricting the temporal progress per round to ensure that at most one transition or state access per agent, the synchronization algorithms enable efficient direct agent interaction and limit the required agent state history to only a single current and projected state. To maintain concurrency given actions that depend on dynamically updated macro-level properties, we introduce a simple relaxation scheme with guaranteed error bounds. Using an extended variant of the classical susceptible-infected-recovered network model, we benchmark and profile the performance of the different algorithms running on CPUs and on a data center GPU. [ABSTRACT FROM AUTHOR]

Objective Groundwater flow in fractured rocks has strong heterogeneity and anisotropy. The discrete fracture network (DFN) method has been internationally considered as one of the most reasonable and effective methods to describe the fracture water transport. Methods In this work, we focused on granite rock from an underground research laboratory site for the geological disposal of high-level radioactive waste. In addition, a high-performance numerical computing system and parallel codes were employed to develop a groundwater flow simulation method in fractured rocks based on the DFN model. Results The results indicated that the proposed method could conduct the groundwater flow simulation of DFN with thousands of mesh elements. This improved the computational efficiency and ability of the parallel codes to deal with complex models. We established the DFN model structure optimization and parameter setting methods of boundary conditions in a complex condition. This could ensure that the hydraulic heads were continuous at different scale models. Furthermore, in the model area, the hydraulic head is distributed as a network structure along fractures. For the connected fractures, the water level was continuous and changed from high to low. However, the water level in the nonconnected fractures was discontinuous. Groundwater flows along the fracture from the high water level area to the low water level area. The connectivity and permeability of the fracture network have an obvious influence on the groundwater flow characteristics. Conclusion Therefore, we could conclude that the parallel groundwater flow simulation method based on the DFN model could more reasonably reflect the groundwater flow in a fractured rock mass. It was of great significance to further improve the simulated prediction ability and deepen the understanding of groundwater flow characteristics in a fractured medium.

Copyright of Systems Engineering & Electronics is the property of Journal of Systems Engineering & Electronics Editorial Department and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Recently, high‐performance computing strategies have been implemented to improve performance analysis and reduce the development time of new solutions in robotic applications, such as path planning, machine learning, and vision, which require massive matrix computations. In this sense, this work aims to study the aerial robots' behavior during their mission execution. Due to the large search space in the set of parameter combinations and the high computational cost required to perform such an analysis after sequentially executing thousands of simulations, this work proposes an open‐source graphics processing unit (GPU)‐based implementation to simulate the robot behavior. A GPU‐accelerated flight route analysis for multi‐unmanned aerial vehicle (UAV) systems is proposed for the tuning control problem in the parameters' space considering the problem of delay in sending information to a ground control station. Considering our implementation, the experimental results show a speedup up to 325×$$ \times $$, 629×$$ \times $$, and 5959×$$ \times $$ in comparison to the parallel version with 16 threads, C coder converter, and native Matlab code, respectively. The implementation is available in the Colab Google platform and it can easily be expanded for analyses involving larger amounts of different parameters, robot models, strategies, and controllers. [ABSTRACT FROM AUTHOR]

Facing the requirements of dynamic planning for aviation communication under the multi-domain cooperative system-level war in the future, according to the objectives of virtual-real mapping, real-time synchronization, symbiotic evolution and closed-loop optimization between the simulation system and the actual system, the paper proposes some application cases that parallel simulation works on improving the combat effectiveness of aviation communication equipment, in-field incremental integration and verification, intelligent health management, virtual and real combined flight training etc. Establish a parallel simulation system architecture for aviation communication and put forward the system composition, then analyze the key technologies such as real-time data acquisition, multi-branch parallel simulation deduction and artificial intelligence-based situation prediction and intelligent decision-making. Lay the theoretical foundation for the application of parallel simulation technology in aviation communication field.

In the parallel simulation deducing based on real-time situation, the uncertainty of battlefield requires the ability of multi-branch simulation. In the process of multi-branch extension, the generation of related branches is realized by the traction of decision points. The traditional decision point selection depends on expert system, which is difficult to meet the requirement of parallel simulation on the efficiency of decision point generation. This paper analyzes the difference between off-line multi-branch inference and real-time multi-branch inference, and proposes a parallel simulation-oriented decision point generation strategy. Based on case-based reasoning, decision points are quickly determined and generated to realize real-time multi-branch inference, which reduces the generation of some invalid branches and guarantees the credibility and effectiveness of multi-branch generation under parallel simulation.

Copyright of Journal of National University of Defense Technology / Guofang Keji Daxue Xuebao is the property of NUDT Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Facing the requirements of dynamic planning for aviation communication under the multi-domain cooperative system-level war in the future, according to the objectives of virtual-real mapping, real-time synchronization, symbiotic evolution and closed-loop optimization between the simulation system and the actual system, the paper proposes some application cases that parallel simulation works on improving the combat effectiveness of aviation communication equipment, in-field incremental integration and verification, intelligent health management, virtual and real combined flight training etc. Establish a parallel simulation system architecture for aviation communication and put forward the system composition, then analyze the key technologies such as real-time data acquisition, multi-branch parallel simulation deduction and artificial intelligence-based situation prediction and intelligent decision-making. Lay the theoretical foundation for the application of parallel simulation technology in aviation communication field. [ABSTRACT FROM AUTHOR]

In the parallel simulation deducing based on real-time situation, the uncertainty of battlefield requires the ability of multi-branch simulation. In the process of multi-branch extension, the generation of related branches is realized by the traction of decision points. The traditional decision point selection depends on expert system, which is difficult to meet the requirement of parallel simulation on the efficiency of decision point generation. This paper analyzes the difference between off-line multi-branch inference and real-time multi-branch inference, and proposes a parallel simulation-oriented decision point generation strategy. Based on case-based reasoning, decision points are quickly determined and generated to realize real-time multi-branch inference, which reduces the generation of some invalid branches and guarantees the credibility and effectiveness of multi-branch generation under parallel simulation. [ABSTRACT FROM AUTHOR]

When parallel algorithms for simulation were introduced in the 1970s, their development and use interested only experts in parallel computation. This circumstance changed as multi-core processors became commonplace, putting a parallel computer into the hands of every modeler. A natural outcome is growing interest in parallel simulation among persons not intimately familiar with parallel computing. At the same time, parallel simulation tools continue to be developed with the implicit assumption that the modeler is knowledgeable about parallel programming. The unintended consequence is a rapidly growing number of users of parallel simulation tools that are unlikely to recognize when the interaction of race conditions, partitioning strategies, and simultaneous action in their simulation models make results non-reproducible, thereby calling into question the validity of conclusions drawn from the simulation data. We illustrate the potential dangers of exposing parallel algorithms to users who are not experts in parallel computation with example models constructed using existing parallel simulation tools. By doing so, we hope to refocus tool developers on usability, even if this new focus incurs loss of some performance. [ABSTRACT FROM AUTHOR]

In this article, we present experiences implementing a general Parallel Discrete Event Simulation (PDES) accelerator on a Field Programmable Gate Array (FPGA). The accelerator can be specialized to any particular simulation model by defining the object states and the event handling code, which are then synthesized into a custom accelerator for the given model. The accelerator consists of several event processors that can process events in parallel while maintaining the dependencies between them. Events are automatically sorted by a self-sorting event queue. The accelerator supports optimistic simulation by automatically keeping track of event history and supporting rollbacks. The architecture is limited in scalability locally by the communication and port bandwidth of the different structures. However, it is designed to allow multiple accelerators to be connected to scale up the simulation. We evaluate the design and explore several design trade-offs and optimizations. We show that the accelerator can scale to 64 concurrent event processors relative to the performance of a single event processor. At this point, the scalability becomes limited by contention on the shared structures within the datapath. To alleviate this bottleneck, we also develop a new version of the datapath that partitions the state and event space of the simulation but allows these partitions to share the use of the event processors. The new design substantially reduces contention and improves the performance with 64 processors from 49x to 62x relative to a single processor design. We went through two iterations of the design of PDES-A, first using Verilog and then using Chisel (for the partitioned version of the design). We report in this article on some observations in the differences in prototyping accelerators using these two different languages. PDES-A outperforms the ROSS simulator running on a 12-core Intel Xeon machine by a factor of 3.2x with less than 15% of the power consumption. Our future work includes building multiple interconnected PDES-A cores.

In this article, we present experiences implementing a general Parallel Discrete Event Simulation (PDES) accelerator on a Field Programmable Gate Array (FPGA). The accelerator can be specialized to any particular simulation model by defining the object states and the event handling code, which are then synthesized into a custom accelerator for the given model. The accelerator consists of several event processors that can process events in parallel while maintaining the dependencies between them. Events are automatically sorted by a self-sorting event queue. The accelerator supports optimistic simulation by automatically keeping track of event history and supporting rollbacks. The architecture is limited in scalability locally by the communication and port bandwidth of the different structures. However, it is designed to allow multiple accelerators to be connected to scale up the simulation. We evaluate the design and explore several design trade-offs and optimizations. We show that the accelerator can scale to 64 concurrent event processors relative to the performance of a single event processor. At this point, the scalability becomes limited by contention on the shared structures within the datapath. To alleviate this bottleneck, we also develop a new version of the datapath that partitions the state and event space of the simulation but allows these partitions to share the use of the event processors. The new design substantially reduces contention and improves the performance with 64 processors from 49x to 62x relative to a single processor design. We went through two iterations of the design of PDES-A, first using Verilog and then using Chisel (for the partitioned version of the design). We report in this article on some observations in the differences in prototyping accelerators using these two different languages. PDES-A outperforms the ROSS simulator running on a 12-core Intel Xeon machine by a factor of 3.2x with less than 15% of the power consumption. Our future work includes building multiple interconnected PDES-A cores.

Employing Modeling and Simulation (M&S) extensively to analyze and develop complex systems is the norm today. The use of robust M&S formalisms and rigorous methodologies is essential to deal with complexity. Among them, the Discrete Event System Specification (DEVS) provides a solid framework for modeling structural, behavior and information aspects of any complex system. This gives several advantages to analyze and design complex systems: completeness, verifiability, extensibility, and maintainability. DEVS formalism has been implemented in many programming languages and executable on multiple platforms. In this paper, we describe the features of an M&S framework called xDEVS that builds upon the prevalent DEVS Application Programming Interface (API) for both modeling and simulation layers, promoting interoperability between the existing platform‐specific (C++, Java, Python) DEVS implementations. Additionally, the framework can simulate the same model using sequential, parallel, or distributed architectures. The M&S engine has been reinforced with several strategies to improve performance, as well as tools to perform model analysis and verification. Finally, xDEVS also facilitates systems engineers to apply the vision of model‐based systems engineering (MBSE), model‐driven engineering (MDE), and model‐driven systems engineering (MDSE) paradigms. We highlight the features of the proposed xDEVS framework with multiple examples and case studies illustrating the rigor and diversity of application domains it can support. [ABSTRACT FROM AUTHOR]

Sparse LU factorization is a key tool in the solution of large linear set of algebraic equations encompassing a wide range of computing applications. Recent advances in this field exploit the massively parallel architecture of the GPUs via left-looking algorithm (LLA) and right-looking algorithm (RLA). In this paper, adaptive cluster mode is proposed to improve the state-of-the-art in LLA for GPU platforms. The proposed method takes into consideration of varying sparsity at different levels during cluster mode execution, to adaptively configure the GPU block size and the number of parallel columns. The new refinements for LLA are also integrated with the dynamic parallelism that is available in modern GPU architectures. The paper also provides a comprehensive performance comparison of the LLA and hybrid RLA along with state-of-the-art advances on the same GPU platform. The results indicate that, when implemented with similar refinements and on a same platform, LLA provides better performance compared to the hybrid-RLA. The results would be useful to the scientific community while making decision on adopting LLA or RLA algorithms for sparse LU factorization.

Hardware-in-the-loop systems are a type of Hard real-time system that require a faster than real-time simulation. A method of running hard real-time systems with slower than real-time simulations is devised. Instead of waiting for the real-time subsystem output to a simulation, multiple simulation input predictions are generated and used to run several parallel simulation paths independent of the real-time subsystem. The simulation path results are stored until needed by the real-time subsystem at which time one is selected and returned to it to continue the execution of the system. A test case using a small modular reactor nuclear power plant hardware-in-the-loop system was used to demonstrate the effects of slower than real-time simulations on a hard real-time system and to show that this method allows such a simulation to be used. [ABSTRACT FROM AUTHOR]

The trend toward higher switching frequency and larger scale of power electronic systems poses challenges for real-time simulation. This article presents an event-driven hardware-in-the-loop (ED-HIL) simulation framework that does not rely on the small fixed simulation step-size related to the switching frequency. ED-HIL framework can improve the calculation efficiency by positioning switch events and using variable simulation step-size. Further, a parallel acceleration and circuit partitioning (PACP) solver is proposed based on this framework. The PACP solver partitions the circuit with energy storage elements and ensures that the partitioning does not introduce simulation distortion by using the higher order derivatives of the energy storage elements. Meanwhile, it achieves a process-level paralleling through a shared memory architecture in order to accelerate the simulation. As a result, the proposed PACP solver based on the ED-HIL framework can achieve about three times the simulation scale of a commercial FPGA-based real-time simulator at 1/16 the hardware cost under the same conditions. An accurate real-time HIL example of a power electronic transformer with 32 switches at a switching frequency of 20 kHz has been implemented on a personal computer. The simulation results are analyzed by comparing with experiment, offline software, and commercial real-time simulator. [ABSTRACT FROM AUTHOR]

In this paper, we present initial experiences implementing a general Parallel Discrete Event Simulation (PDES) accelerator on a Field Programmable Gate Array (FPGA). The accelerator can be specialized to any particular simulation model by defining the object states and the event handling logic, which are then synthesized into a custom accelerator for the given model. The accelerator consists of several event processors that can process events in parallel while maintaining the dependencies between them. Events are automatically sorted by a self-sorting event queue. The accelerator supports optimistic simulation by automatically keeping track of event history and supporting rollbacks. The architecture is limited in scalability locally by the communication and port bandwidth of the different structures. However, it is designed to allow multiple accelerators to be connected together to scale up the simulation. We evaluate the design and explore several design tradeoffs and optimizations. We show the accelerator can scale to 64 concurrent event processors relative to the performance of a single event processor.

In this paper, we present initial experiences implementing a general Parallel Discrete Event Simulation (PDES) accelerator on a Field Programmable Gate Array (FPGA). The accelerator can be specialized to any particular simulation model by defining the object states and the event handling logic, which are then synthesized into a custom accelerator for the given model. The accelerator consists of several event processors that can process events in parallel while maintaining the dependencies between them. Events are automatically sorted by a self-sorting event queue. The accelerator supports optimistic simulation by automatically keeping track of event history and supporting rollbacks. The architecture is limited in scalability locally by the communication and port bandwidth of the different structures. However, it is designed to allow multiple accelerators to be connected together to scale up the simulation. We evaluate the design and explore several design tradeoffs and optimizations. We show the accelerator can scale to 64 concurrent event processors relative to the performance of a single event processor.

When performing modeling routines with iterative simulations, a research gap exists in developing the parallelizing frameworks that are adaptable to the increasing complexities of the hydrologic models. This study addresses this gap by proposing a parallel simulation stack for SWAT (PASS4SWAT) that leverages the power of cloud-native infrastructure. Cloud-native applications are designed to be scalable, agile, and resilient, making them ideal for computationally intensive tasks such as hydrologic modeling. To achieve this goal, PASS4SWAT was created by integrating a message broker, a container runtime and orchestration tool, and certain components from SWAT-CUP. We evaluated PASS4SWAT using the Jinjiang watershed model and a synthetic model with high input/output demands to demonstrate its effectiveness. The results show that PASS4SWAT can consistently replicate the results obtained with SWAT-CUP and significantly reduce the runtime, achieving 91.5% and 93.2% reductions in single-node and multinode Kubernetes clusters, respectively. Therefore, in this paper, we conclude that PASS4SWAT can effectively address the high computational demands of the SWAT model by scaling out parallel tasks on a cluster, and can adapt flexibly to diverse environments, including single-node clusters, multinode clusters, and potential cloud platforms. [Display omitted] • PASS4SWAT significantly reduces the runtime needed for calibration and uncertainty analysis. • PASS4SWAT can adapt to diverse environments, including single-node and multinode clusters. • PASS4SWAT can autonomously manage subtasks and obviate the need for explicit failover and load balancing. • PASS4SWAT has great potential for application in other models and can be linked with other calibration tools. [ABSTRACT FROM AUTHOR]

The definition of protein structures is an important research topic in molecular biology currently, since there is a direct relationship between the function of the protein in the organism and the 3D geometric configuration it adopts. The transformations that occur in the protein structure from the 1D configuration to the 3D form are called protein folding. Ab initio protein folding methods use physical forces to model the interactions among the atoms that compose the protein. In order to accelerate those methods, parallel tools such as NAMD were proposed. In this paper, we propose two contributions for parallel protein folding simulations: (a) adaptive patch grid (APG) and (b) the addition of atomic burials (AB) to the traditional forces used in the simulation. With APG, we are able to adapt the simulation box (patch grid) to the current shape of the protein during the folding process. AB forces relate the 3D protein structure to its geometric center and are adequate for modeling globular proteins. Thus, adding AB to the forces used in parallel protein folding potentially increases the quality of the result for this class of proteins. APG and AB were implemented in NAMD and tested in supercomputer environments. Our results show that, with APG, we are able to reduce the execution time of the folding simulation of protein 4LNZ (5,714 atoms, 15 million time steps) from 12 hours and 36 minutes to 11 hours and 8 minutes, using 16 nodes (256 CPU cores). We also show that our APG+AB strategy was successfully used in a realistic protein folding simulation (1.7 billion time steps). • We propose an adaptive strategy to better adapt the protein folding simulation box. • We include atomic burial forces to enhance parallel protein folding simulation. • We show that our techniques are able to reduce the simulation time. • We present a realistic protein folding case study. [ABSTRACT FROM AUTHOR]

The Carbon Capture Simulation Initiative (CCSI) project has developed and deployed scientific infrastructure called the CCSI Toolset. The CCSI Toolset provides state-of-the-art computational modeling and simulation tools to accelerate the commercialization of carbon capture technologies from discovery to development, demonstration, and ultimately the widespread deployment to hundreds of power plants. Carbon capture technologies have the potential to dramatically reduce the carbon emissions from power plants. The CCSI Toolset provides end users in industry with a comprehensive, integrated suite of leading-edge, scientifically validated models with simulation, uncertainty quantification, optimization, risk analysis and decision making support. The CCSI Toolset has at its core an integrated framework that enables execution of simulations and workflows including optimization and uncertainty parameter sweeps using a wide variety of computing platforms including desktops, clusters, Clouds, and HPC systems. The integration framework enables the running of a variety of commercial process simulation packages as well as custom simulators. Moreover, the framework enables scientists to run and manage thousands of concurrent simulations to perform optimizations and uncertainty quantification. Components of the CCSI Toolset are connected through the use of a data management system that stores data to a repository and enables the tracking of provenance for each simulation as well as its associated components. The data management system tracks all the configurations, models, simulations, and results created during the design of a carbon capture system and supports the design life-cycle as well as decision making. The primary contribution of this paper is thus the design and implementation of the integration framework within the CCSI Toolset, which provides both data management and simulation support for CCSI. This integration framework has been deployed and is in use by several groups of researchers and commercial entities.

Abstract This research proposes a system based on a combination of various components for parallel modelling and forecasting the processes in networks with data assimilation from the real network. The main novelty of this work consists of the assimilation of data for forecasting the processes in social networks which allows improving the quality of the forecast. The social network VK was considered as a source of information for determining types of entities and the parameters of the model. The main component is the model based on a combination of internal sub-models for more realistic reproduction of processes on micro (for single information message) and meso (for series of messages) levels. Moreover, the results of the forecast must not lose their relevance during the calculations. In order to get the result of the forecast for networks with millions of nodes in reasonable time, the process of simulation has been parallelized. The accuracy of the forecast is estimated by MAPE, MAE metrics for micro-scale, the Kolmogorov–Smirnov criterion for aggregated dynamics. The quality in the operational regime is also estimated by the number of batches with assimilated data to achieve the required accuracy and the ratio of calculation time in the frames of the forecasting period. In addition, the results include experimental studies of functional characteristics, scalability, as well as the performance of the system.

Parallel algorithms are problematic to develop because of the negative influence of synchronisation, complicated behaviour of threads' capturing computing resources. Experimental results show performance time's strong dependence on algorithm parameters, such as the number of subtasks and the complexity of each task. The optimal value of subtask complexity is revealed for the particular algorithm. It is the same for different complexity of the parallelised task (with the same computing resource). To guarantee algorithm speed-up it is important to have a method for investigating the efficiency of parallel algorithm before its implementation on specified computing resources. Stochastic Petri net potentially could be a high accuracy tool for investigating the efficiency of a parallel algorithm. However, a huge number of elements are needed to compose a model of non-trivial algorithm that limits the application of this tool in practice. Petri-object simulation method allows replication of Petri nets with specified parameters and model creation of a list of linked Petri-objects. Basic templates for the model creation of a multithreaded algorithm are developed. Applying these templates, the model of the parallel discrete event simulation algorithm is developed and investigated. By the model results, the algorithm parameters providing the least performance time can be determined. [ABSTRACT FROM AUTHOR]

LU factorization is extensively used in engineering and scientific computations for solution of large set of linear equations. Particularly, circuit simulators rely heavily on sparse version of LU factorization for solution involving circuit matrices. One of the recent advances in this field is exploiting the emerging computing platform of graphics processing units (GPUs) for parallel and sparse LU factorization. In this article, following contributions are made to advance the state of the art in hybrid right-looking algorithm (RLA): 1) a novel GPU kernel based on parallel column and block size optimization (PCBSO) is developed for adaptively allocating the block size while optimizing the number of columns for parallel execution based on the size of their associated submatrices at every level. The proposed approach helps to minimize the resource contention and to improve the computational performance and 2) an algorithm is developed to enable the execution of the new adaptive mode with dynamic parallelism. Also, a comprehensive performance comparison using a set of benchmark circuit examples is presented. The results indicate that, the proposed advancements can improve the results of state-of-the-art right looking sparse LU factorization in GPU by $1.54\times $ (Arithmetic Mean). [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM2.0 must get faster while maintaining accuracy. However, the ASI SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present SCale 2.0, a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented simulation speeds. By coupling a parallel SystemC kernel with shared resources access monitoring and process-level rollback, we can preserve SystemC atomic thread evaluation while leveraging the available host cores. We also generate process interaction traces that can be used to replay any simulation deterministically for debug purpose. Evaluation on baremetal applications shows × 15 speedup compared to the ASI SystemC kernel using 33 host cores reaching speeds above 2300 Million simulated Instructions Per Second (MIPS). Challenges related to parallel simulation of full software stack with modern operating systems are also addressed with speedup reaching × 13 during recording run and × 24 during the replay run. • SystemC Standard parallel simulation can be achieved with interactions monitoring. • Process atomicity violation can be avoided most of the time with proper heuristic. • Rollback mechanism can recover from semantics violations when the heuristic fails. • Full software stack simulation in modern OS exhibits more atomicity violation risks. • Additional monitoring of the Virtual Prototype privileged state mitigates the risk. [ABSTRACT FROM AUTHOR]

Discrete Event Simulation (DES) frameworks gained significant popularity to support and evaluate cloud computing environments. They support decision-making for complex scenarios, saving time and effort. The majority of these frameworks lack parallel execution. In spite being a sequential framework, DISSECT-CF introduced significant performance improvements when simulating Infrastructure as a Service (IaaS) clouds. Even with these improvements over the state of the art sequential simulators, there are several scenarios (e.g., large scale Internet of Things or serverless computing systems), which DISSECT-CF would not simulate in a timely fashion. To remedy such scenarios this paper introduces parallel execution to its most abstract subsystem: the event system. The new event subsystem detects when multiple events occur at a specific time instance of the simulation and decides to execute them either on a parallel or a sequential fashion. This decision is mainly based on the number of independent events and the expected workload of a particular event. In our evaluation, we focused exclusively on time management scenarios. While we did so, we ensured that the behaviour of the events should be equivalent to realistic, larger-scale simulation scenarios. This allowed us to understand the effects of parallelism on the whole framework, while we also shown the gains of the new system compared to the old sequential one. With regards to scaling, we observed it to be proportional to the number of cores in the utilised SMP host. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive Particle Swarm Optimization(APSO) global search algorithm and Spiking Neural Network(SNN) surrogate model-based optimization design method for analog integrated circuits performance enhancement. The initial design parameters are calculated by numerical computation. The global design space is extended and explored using APSO in the main loop, with constraint testing ensuring the transistor works in the right conditions. A Spiking Neural Network (SNN) model aids in predicting circuit performance during local searches, in which training data for the local design space is generated through parallel SPICE simulations. The optimization framework is applied to rail-to-rail amplifiers of two topologies. The results show that the proposed method accelerates the optimization process, achieving up to a 35.4x speed enhancement compared to Particle Swarm Optimization(PSO) based on the SPICE simulation. Moreover, Compared with traditional approaches based on multiobjective optimization, the proposed method provides an advantage in performance improvement and is valid for different CMOS processes. [ABSTRACT FROM AUTHOR]

Abstract Background In recent years, the study of immune response behaviour using bottom up approach, Agent Based Modeling (ABM), has attracted considerable efforts. The ABM approach is a very common technique in the biological domain due to high demand for a large scale analysis tools for the collection and interpretation of information to solve biological problems. Simulating massive multi-agent systems (i.e. simulations containing a large number of agents/entities) requires major computational effort which is only achievable through the use of parallel computing approaches. Results This paper explores different approaches to parallelising the key component of biological and immune system models within an ABM model: pairwise interactions. The focus of this paper is on the performance and algorithmic design choices of cell interactions in continuous and discrete space where agents/entities are competing to interact with one another within a parallel environment. Conclusions Our performance results demonstrate the applicability of these methods to a broader class of biological systems exhibiting typical cell to cell interactions. The advantage and disadvantage of each implementation is discussed showing each can be used as the basis for developing complete immune system models on parallel hardware.

In general, a detailed modeling and evaluation of computer architectures make a cycle-accurate simulator necessary. As the architectures become increasingly complex for parallel, cloud, and neural computing, nowadays, the complexity of the simulator grows rapidly, and thus its execution is too slow or infeasible for practical use. In order to alleviate the problem, many previous studies have focused on reducing the simulation time in a variety of ways such as using sampling methods, adding hardware accelerators, and so on. In this paper, we propose a new parallel simulation framework, called Epoch-based Parallel SIMulator, to obtain scalable speedup with large number of cores. The framework is based on a well-known cycle-accurate full-system simulator, MARSSx86. From the simulator, we build an epoch, that is an execution interval, where the architectural simulation by PTLSim does not involve any interaction with QEMU. Therefore, we can simulate epochs independently, i.e., execute multiple epochs completely in parallel by PTLSim with their live-in data. Our performance evaluation shows that we achieve $12.8\times $ speed on average with 16-core parallel simulation from the SPEC CPU2006 benchmarks and the PARSEC benchmarks, providing the performance scalability.