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Fault injection technologies can be utilized to steal secret information inside integrated circuits (ICs), and thus cause serious information security threats. Parity check has been adopted as an efficient method against fault injection attacks. However, the contradiction between security and overhead restricts the further development and applications of parity check in fault injection detection. This paper proposes two methods, mixed-grained parity check and word recombination parity check, based on parity check for the trade-off between security and overhead. The efficiency of the proposed approaches is verified on RC5, AES, and DES encryption implementations by clock glitch attack. Compared with the traditional parity check, the fault coverage rate of the mixed-grained approach can be increased by up to 53.69% by consuming 13.2% registers more. Against the traditional parity check, the fault coverage rate of the word recombination approach can be increased by up to 47.16% by using only 2.35% register more. The proposed approaches provide IC designers with countermeasure options targeting different design skills and design specifications. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10 - 3 . [ABSTRACT FROM AUTHOR]

Protecting cache memories against radiation-induced soft errors is critical in designing highly reliable processors. Dirty lines in write-back data caches are more critical, since the dirty lines have no backups in lower-level memory (LLM). This paper provides a write-buffer scheme for backing up dirty lines to protect cache memories based on the replication mechanism combined with interleaving parity check against multiple-bit errors. The write-buffer contains two same replication caches to replicate the dirty data from the original cache, and the two replication caches take turns to write the replicated data back to LLM during the free time when there is no access in LLM. In this way, the dirty data in original cache is backed up to LLM that can be used for error recovery, and meanwhile, spaces of the replication caches are released to replicate new dirty data; moreover, the writebacks of the replicated data can be performed in the background without extra clocks. Simulation results show that the proposed write-buffer scheme can provide a full protection for caches without degrading system performance, while it can improve the system performance by an average of 1.4% due to the background writebacks, and compared with state-of-the-art replication-based technique, it can increase the replication capability by 11.6% and save 6.2% energy consumption in case of the optimal configuration. It is superior to the existing techniques in terms of protection capability and system performance overhead.

Entanglement purification and concentration are effective means to deal with the influence of noise on the coherence of entangled quantum systems, which enable us to carry out secure and efficient quantum communications. However, the reliability of parity check in parity-check-based entanglement purification and concentration schemes will inevitably affect the performance of the schemes. In this paper, we propose faithful entanglement purification and concentration schemes for polarization-entangled photon pairs, using heralded high-fidelity parity-check detectors (PCDs) constructed by double-sided quantum-dot-microcavity (QD-microcavity) systems and linear-optical elements. The PCD is based on the general interaction rule between the input photon and the QD-microcavity system, without the requirement of the system to strictly satisfy the specifically ideal conditions for giant circular birefringence, which makes it more realizable in practice. Moreover, the PCD can work in a failure-heralded and fidelity-robust fashion, so it can make a correct judgement on the parity mode of a two-photon system and has no destruction on the entangled state. Our schemes can therefore realize faithful entanglement purification and concentration by utilizing the PCD, without reducing the fidelity and entanglement degree of the obtained entangled-state ensemble. These features make our schemes more feasible and useful in quantum repeaters and quantum networks. [ABSTRACT FROM AUTHOR]

When polar codes are decoded by the successive cancellation (SC) decoding algorithm, erroneously decoded non-frozen bits are caused by either channel noise or error propagation. SC-Flip algorithms aim to improve error performance by first identifying erroneous hard decisions due to channel noise and then flipping them during the decoding process to reduce error propagation. In existing SC-Flip algorithms, cyclic redundancy check (CRC) is used to check the decoded codeword to detect incorrect hard decisions. Differing from this detection approach based on CRC, we propose new SC-Flip decoders that take advantage of both the CRC and distributed parity checks (PCs) to detect, identify and flip erroneously decoded non-frozen bits. The proposed decoders terminate SC decoding early when a distributed PC is not satisfied. In addition, we propose a new metric to help locate the incorrect hard decisions. Finally, simulation results demonstrate that our SC-Flip decoders achieve better performance complexity tradeoffs than prior flipping algorithms, and approach the performance and complexity of the SC-Oracle algorithms. [ABSTRACT FROM AUTHOR]

As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R+1 defects. Moreover, by using G groups, it can localize up to GxR and detect up to G x (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

Filling techniques are often used in the restoration of images. Yet the existing filling technique approaches either have high computational costs or present problems such as filling holes redundantly. This paper proposes a novel algorithm for filling holes and regions of the images. The proposed algorithm combines the advantages of both the paritycheck filling approach and the region-growing inpainting technique. Pairing points of the region's boundary are used to search and to fill the region. The scanning range of the filling method is within the target regions. The proposed method does not require additional working memory or assistant colors, and it can correctly fill any complex contours. Experimental results show that, compared to other approaches, the proposed algorithm fills regions faster and with lower computational cost. [ABSTRACT FROM AUTHOR]

We investigate the effect of inserting extra linearity in the Data Encryption Standard (DES) through appropriate nonsingular linear encodings of the output of the individual S-boxes. More specifically, we examine the general situation when the output of each S-box of the DESis precoded separately intoaproperly constructed copy of the inherent even-weight code of length 4. The study is focused on finding multi-round linear characteristics for thus modified DESciphers having maximal effectiveness. Depending on the particular encodings, it turns out that the effectiveness of interest may be larger but in most cases is smaller than that one for the original DESwith the same number of rounds. The latter means that the complexity of successful linear cryptanalysis against these ciphers will mainly increase comparing to the DESitself. The present research extends inanatural way our previous work[Linear Cryptanalysis and Modified DESwith Parity Check in the S-boxes, LNCS 9540 (2016), pp. 60-78].

In the process of quantum key distribution (QKD), error correction algorithm is used to correct the error bits of the key at both ends. The existing applied QKD system has a low key rate and is generally Kbps of magnitude. Therefore, the performance requirement of data processing such as error correction is not high. In order to cope with the development demand of high-speed QKD system in the future, this paper introduces the Winnow algorithm to realize high-speed parity and hamming error correction based on Field Programmable Gate Array (FPGA), and explores the performance limit of this algorithm. FPGA hardware implementation can achieve the scale of Mbps bandwidth, with choosing different group length of sifted key by different error rate, and can achieve higher error correction efficiency by reducing the information leakage in the process of error correction, and improves the QKD system's secure key rate, thus helping the future high-speed QKD system. [ABSTRACT FROM AUTHOR]

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Traditional digital image authentication is usually based on signature or fragile watermarks. This performs authentication without any secret hidden data. Until now, many image authentication schemes with error detection based on watermarks or signatures have been proposed. Tampering attack can be detected but the areas tampered with cannot be determined for these schemes. In order to improve this shortcoming, a verifiable data hiding scheme is proposed for digital images in this paper. The main idea of the proposed scheme is combining multi-bit encoding function and multi-group data hiding scheme to increase embedding capacity and strengthen security with parity check to verify the tampering of digital images having embedded secret messages. Therefore, there are three major contributions in our proposed scheme. First, it can achieve image tamper detection and find what has been modified. Second, it resists collage attack. Third, it can increase the embedding capacity. These contributions are discussed according to experimental results. The proposed scheme includes a high security to reduce detection of hidden data and the MSE analysis also proves this scheme has good image quality. [ABSTRACT FROM AUTHOR]

In this paper, the uplink information-coupled polar-coded sparse code multiple access (PC-SCMA) system is proposed. For this system, we first design the encoding method of systematic joint parity check and CRC-aided (PCCA) polar code. Using the systematic PCCA-polar code as base code, the partially information-coupled (PIC) polar code is constructed. Then, a joint iterative detection and successive cancellation list (SCL)-decoding receiver is proposed for the PC-SCMA system. For the receiver, the coupled polar decoder’s extrinsic messages are calculated by the Bayes rule and soft cancellation (SCAN) algorithm. Based on the extrinsic information transfer (EXIT) idea, the PIC PCCA-polar code is optimized. Simulation results demonstrate that the PIC PCCA-PC-SCMA system outperforms the other polar (or LDPC) coded SCMA systems at various code rates and channel configurations. Additionally, compared with an uncoupled PC-SCMA system with SCL decoder, the complexity of PIC PCCA-PC-SCMA is reduced at a high Eb/N0