1. Performance exploration of partially connected 3D NoCs under manufacturing variability
- Author
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Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Vianney Lapotre, Fernanda Lima Kastensmidt, Anelise Kologeski, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT), Smart Integrated Electronic Systems (SmartIES), Conception et Test de Systèmes MICroélectroniques ( SysMIC ), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier ( LIRMM ), Université de Montpellier ( UM ) -Centre National de la Recherche Scientifique ( CNRS ) -Université de Montpellier ( UM ) -Centre National de la Recherche Scientifique ( CNRS ), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lorient] ( Lab-STICC ), and Université européenne de Bretagne ( UEB ) -École Nationale d'Ingénieurs de Brest ( ENIB ) -Université de Bretagne Sud ( UBS ) -Université de Brest ( UBO ) -Télécom Bretagne-ENSTA Bretagne-Institut Mines-Télécom [Paris]-Centre National de la Recherche Scientifique ( CNRS )
- Subjects
Engineering ,integrated circuit manufacture ,Elevator ,Serial communication ,02 engineering and technology ,Hardware_PERFORMANCEANDRELIABILITY ,network routing ,three-dimensional integrated circuits ,01 natural sciences ,partially asynchronous 3D NoCs ,manufacturing variability ,0202 electrical engineering, electronic engineering, information engineering ,asynchronous communication interfaces ,network-on-chip ,TSVs ,partially connected 3D NoC ,Clocks ,010302 applied physics ,Resistive touchscreen ,TSV propagation delays ,delay distribution ,delay variation ,020202 computer hardware & architecture ,Telecommunication traffic ,Network on a chip ,Three-dimensional displays ,Serialization ,0103 physical sciences ,Electronic engineering ,Hardware_INTEGRATEDCIRCUITS ,Through-silicon vias ,Delays ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Elevators ,Routing ,business.industry ,through silicon vias ,Fault tolerance ,3D network-on-chip ,yield ,open defective TSV ,resistive defective TSV ,Asynchronous communication ,Embedded system ,adaptive routing ,serial communication ,serialization ,[ SPI.NANO ] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,fault tolerance ,Routing (electronic design automation) ,3D manufacture variability ,business - Abstract
International audience; Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.
- Published
- 2014
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