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Settling time is an important performance metric in digital-to-analog converters (DACs) that are used for dynamic calibration applications. To obtain an area efficient DAC design, periodic sequences are generated from sigma-delta modulators (ΣΔMs) using software, stores the sequence in memory and then passes it to a low-pass filter (LPF). In this brief, the sigma-delta (ΣΔ) bitstream generated in software will be optimized such that it yields a system that settles faster and is more area efficient. Two optimization routines are used, namely, serial method and random method algorithms. The random method is chosen to optimize the ΣΔ bitstreams for its computational simplicity. It will be shown, that using the random method routine provides at least 46% improvement in settling time performance of a 12-bit DAC, used in the paper as a design example. Moreover, it offers silicon area savings by at least 10% for resistor components and 35% for capacitor components. Similar results were obtained for 8 to 11 bits of resolution.