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Abstract An improved 4H‐SiC SBD‐wall‐integrated trench metal‐oxide‐semiconductor (SWITCH‐MOS) with n‐bury and split‐gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n‐bury layer can smooth the path to current conduction, which reduces the specific on‐resistance (RON, SP) and improves static characteristics. Besides, the split‐gate is able to transform the gate‐drain capacitance (CGD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH‐MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH‐MOS with almost the same BV, the proposed one reduces the RON, SP by 57% and the CGD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only −1.78 V, but its figure of merit reaches 1.67 GW/cm2 and 65 mΩ·nC, which is attractive for the application in power inverters.

Abstract Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages.

Abstract Series connection of Silicon Carbide (SiC) Metal‐Oxide‐Semiconductor Field‐Effect Transistors (MOSFETs) is an interesting solution to design switches for voltages that are not yet commercially available or limited for single‐die devices. However, inherent static and dynamic voltage balancing must be achieved. Voltage imbalance is caused by the device parameters spread, whose impact is pronounced in low‐inductive circuit layouts. This study investigates the optimal design and tuning limits of resistor‐capacitor (RC)‐snubber circuits and non‐adaptive, standard, voltage‐source gate drivers for achieving the best balancing in transient and steady‐state voltage distributions among series‐connected discrete SiC MOSFETs operating at speeds up to 90kV/μs. It has been shown that a larger parameter mismatch will lead to uneven switching energy losses and larger voltage imbalances. It was also experimentally shown that increasing the gate resistor to slow down the devices will not always improve balancing when their parameter spread is large. Thus, tuning recommendations for the RC‐snubber circuit and gate driver were developed based on these findings.

Abstract Different methods have been developed to predict power devices' remaining useful life (RUL). The existing methods need to specify the failure thresholds corresponding to failure precursors of power devices based on historical data. However, there might be heterogeneity in failure threshold between different devices despite being from the same batch, which can severely affect the RUL prediction performance. Aiming at this problem, this article proposes an RUL prediction method based on the non‐linear Wiener process considering the failure threshold uncertainty. To incorporate the failure threshold uncertainty into the RUL prediction, the truncated normal distribution is employed to characterize this uncertainty. The maximum‐likelihood estimation method is used to estimate the model parameters based on the historical degradation data. Then, the parameters can be dynamically updated by the Bayesian paradigm each time a new piece of condition monitoring (CM) data of the interested device in service is observed. This makes the predicted RUL dependent on the real‐time health conditions of the interested device in service. The effectiveness of the proposed method is validated with the power cycling testing results of SiC MOSFETs. Experimental results reveal that the proposed method can reduce the prediction error by 10.273%.

Abstract Silicon carbide (SiC) MOSFETs are garnering widespread attention due to their superior performance in high‐temperature, high‐frequency, and high‐voltage applications, emerging as the preferred power semiconductor devices in converters for photovoltaic power generation and new energy vehicles. However, SiC MOSFETs are prone to gate drive and drain‐source voltage oscillations during high‐speed switching events, resulting in diminished system efficiency, increased electromagnetic interference, reduced device safety, and even compromising the overall reliability of the converter. This paper introduces an oscillation suppression method based on a gate LCR parallel branch, aimed at optimizing the switching performance of SiC MOSFETs. A half‐bridge circuit model based on SiC MOSFET is established, and the mechanism of gate and drain‐source oscillation is meticulously analysed using the transfer function expression. Building upon this, the LCR parallel branch parameters are meticulously designed to introduce appropriate damping in the gate drive path, effectively mitigating oscillations. Experimental results demonstrate that the proposed design not only significantly reduces the amplitude of oscillations but also shortens the switch‐transition time. This enhancement effectively increases the switching frequency and reduces switching losses.

An improved 4H‐SiC SBD‐wall‐integrated trench metal‐oxide‐semiconductor (SWITCH‐MOS) with n‐bury and split‐gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n‐bury layer can smooth the path to current conduction, which reduces the specific on‐resistance (RON, SP) and improves static characteristics. Besides, the split‐gate is able to transform the gate‐drain capacitance (CGD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH‐MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH‐MOS with almost the same BV, the proposed one reduces the RON, SP by 57% and the CGD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only −1.78 V, but its figure of merit reaches 1.67 GW/cm2 and 65 mΩ·nC, which is attractive for the application in power inverters. [ABSTRACT FROM AUTHOR]

Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages. [ABSTRACT FROM AUTHOR]

Series connection of Silicon Carbide (SiC) Metal‐Oxide‐Semiconductor Field‐Effect Transistors (MOSFETs) is an interesting solution to design switches for voltages that are not yet commercially available or limited for single‐die devices. However, inherent static and dynamic voltage balancing must be achieved. Voltage imbalance is caused by the device parameters spread, whose impact is pronounced in low‐inductive circuit layouts. This study investigates the optimal design and tuning limits of resistor‐capacitor (RC)‐snubber circuits and non‐adaptive, standard, voltage‐source gate drivers for achieving the best balancing in transient and steady‐state voltage distributions among series‐connected discrete SiC MOSFETs operating at speeds up to 90kV/μs$90 \,\mathrm{k}\mathrm{V}/{\umu }\mathrm{s}$. It has been shown that a larger parameter mismatch will lead to uneven switching energy losses and larger voltage imbalances. It was also experimentally shown that increasing the gate resistor to slow down the devices will not always improve balancing when their parameter spread is large. Thus, tuning recommendations for the RC‐snubber circuit and gate driver were developed based on these findings. [ABSTRACT FROM AUTHOR]

For single-event radiation damage of power MOSFET devices, this paper aims to establish a statistical analysis method based on external observation (gate/drain current characteristics in irradiation environment) to recognize and evaluate the radiation evolution process and damage mechanism of microscopic physical quantities inside the devices, namely current-carrier (CC) mapping. Firstly, a special data fluctuate–collapse transform analysis method is proposed according to the temporal characteristics of the gate/drain current. Secondly, a carrier dynamic balance ratio based on current data is defined to evaluate the radiation damage degree of the device. TCAD is used to deeply study the relationship between the external current characteristics and the evolution process of internal physical quantities and the damage mechanism. The results show that the current data timing analysis based on fluctuate–collapse transformation can better peer into the evolution process of irradiation events inside the device, and the statistical analysis based on the dynamic balance ratio of carriers can evaluate the severity of irradiation damage to a certain extent. [ABSTRACT FROM AUTHOR]

This work aims to estimate the Metal-Oxide-Semiconductor Field-Effect Transistor's (MOSFET) junction temperature, guessing in real time the dynamic drain-source resistance during MOSFET operation in LLC (Inductor-Inductor-Capacitor) converters usually adopted in Switched-Mode Power Supplies. The task is accomplished using an on-state voltage measurement circuit that allows clamping of the high-voltage drain-source voltage during the off-state. The results of this method have been compared with the temperature accurately measured using a co-packed die as a thermal sensor. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFETs are garnering widespread attention due to their superior performance in high‐temperature, high‐frequency, and high‐voltage applications, emerging as the preferred power semiconductor devices in converters for photovoltaic power generation and new energy vehicles. However, SiC MOSFETs are prone to gate drive and drain‐source voltage oscillations during high‐speed switching events, resulting in diminished system efficiency, increased electromagnetic interference, reduced device safety, and even compromising the overall reliability of the converter. This paper introduces an oscillation suppression method based on a gate LCR parallel branch, aimed at optimizing the switching performance of SiC MOSFETs. A half‐bridge circuit model based on SiC MOSFET is established, and the mechanism of gate and drain‐source oscillation is meticulously analysed using the transfer function expression. Building upon this, the LCR parallel branch parameters are meticulously designed to introduce appropriate damping in the gate drive path, effectively mitigating oscillations. Experimental results demonstrate that the proposed design not only significantly reduces the amplitude of oscillations but also shortens the switch‐transition time. This enhancement effectively increases the switching frequency and reduces switching losses. [ABSTRACT FROM AUTHOR]

Different methods have been developed to predict power devices' remaining useful life (RUL). The existing methods need to specify the failure thresholds corresponding to failure precursors of power devices based on historical data. However, there might be heterogeneity in failure threshold between different devices despite being from the same batch, which can severely affect the RUL prediction performance. Aiming at this problem, this article proposes an RUL prediction method based on the non‐linear Wiener process considering the failure threshold uncertainty. To incorporate the failure threshold uncertainty into the RUL prediction, the truncated normal distribution is employed to characterize this uncertainty. The maximum‐likelihood estimation method is used to estimate the model parameters based on the historical degradation data. Then, the parameters can be dynamically updated by the Bayesian paradigm each time a new piece of condition monitoring (CM) data of the interested device in service is observed. This makes the predicted RUL dependent on the real‐time health conditions of the interested device in service. The effectiveness of the proposed method is validated with the power cycling testing results of SiC MOSFETs. Experimental results reveal that the proposed method can reduce the prediction error by 10.273%. [ABSTRACT FROM AUTHOR]

Superjunction MOSFETs have been one of the promising switching components for realizing resonant converters. In spite of the numerous studies about the resonant converters in power electronics, the detailed current flow in the device has been still unclear, especially for the inner-current circulation between the body diode and the MOSFET. By employing five-terminals on the superjunction MOSFET, mixed-mode half-bridge resonant converter is simulated. During the turn-on of the MOSFET, the gate charging current flows into the drain-to-source capacitance to form a built-in depletion of the pillars. In the case of the turn-off, the source current reversely flows across the channel with a slightly negative drain-to-source bias and diverts to the gate discharging current.

Abstract In order for full utilization of the switching devices and safe continued operation of the power converter at the same time, the junction temperature of the switching devices needs to be accurately monitored without shutting down the motor drive. This paper derives an analytical junction temperature calculation method by using Laplace transformation and thermal network theory. Based on an actual motor drive, a simulation model is established using platform for power electronic systems (PLECS). Through comparison, the derived method is proven to be able to calculate junction temperature accurately.

In order for full utilization of the switching devices and safe continued operation of the power converter at the same time, the junction temperature of the switching devices needs to be accurately monitored without shutting down the motor drive. This paper derives an analytical junction temperature calculation method by using Laplace transformation and thermal network theory. Based on an actual motor drive, a simulation model is established using platform for power electronic systems (PLECS). Through comparison, the derived method is proven to be able to calculate junction temperature accurately. [ABSTRACT FROM AUTHOR]

In this work, we design and simulate a high performance electrostatically doped dual buried gates power MOSFET (EDDBGP-MOS) structure. The novelty of the proposed device is three folds. Firstly, the n + source and P + body regions of the device are realized using induced charge plasma by employing metal electrodes on the silicon film. The device thus reduces the risk of random doping fluctuations and the formation of highly abrupt junctions during fabrication. The high temperature processes involved in defining the doped regions are not required, thus providing low thermal budget. Secondly, the Gaussian hole plasma profile in the p body region allows increase in drift doping concentration from 5 × 1015/cm3 to 7 × 1015/cm3 resulting in Ron reduction to almost 24% of its uniformly doped counterpart structure, with only a slight reduction in breakdown voltage of the device. The proposed device thus provides 10% increase in the Baliga's figure of merit (FOM1 = BV2/Rsp). Further, the linearly graded Gaussian profile at the source side reduces the source coupling with gate. The gate charge together with the reduced specific ON resistance value provides as good as 19% reduction in Baliga's high frequency figure of merit FOM2 = Rsp.Qsp). As compared to the conventional trench MOSFET structure, the two buried gates in the proposed structure provides low gate drain coupling along with the suppression in parasitic BJT effect. A two-dimensional simulation study of the proposed EDDBGP-MOS device reveals that it outperforms the conventional trench MOSFET device in terms of the performance parameters of power devices, along with the reduced fabrication complexity. [ABSTRACT FROM AUTHOR]

Three‐phase ac choppers feature output voltage amplitude controllability and enable more compact system realizations compared to autotransformers. For the practical realization advantageously standard power transistor with unipolar voltage blocking capability such as MOSFETs can be employed as a naturally resulting offset voltage between the grid and the input‐stage starpoint ensures purely positive power transistor voltages. This offset voltage is, however, not strictly defined and may drift to higher voltage values, resulting in high power transistor voltage stresses and finally a potential overvoltage breakdown. Traditionally, the offset voltage drift is prevented by introducing discharge resistors across the input‐stage capacitors which, however, results in substantial ohmic losses. This paper analyzes the offset voltage formation in ac choppers and proposes a novel clamping modulation scheme which ensures a strictly defined and minimum time‐varying offset voltage without need for discharge resistors. Theoretical analyses and circuit simulations are finally experimentally verified with a 400 V (rms, line‐to‐line) 50 Hz grid connected three‐phase buck‐boost ac chopper with 3 kW rated power. [ABSTRACT FROM AUTHOR]

Abstract Silicon carbide (SiC) power metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) switch at an unprecedented speed, even at high currents. For accurate dynamic characterization, current sensors must measure high currents at a high bandwidth. Moreover, at high switching speeds, parasitic impedances in the commutation loop become critical. To ensure high‐accuracy measurements, the current sensor insertion impedance must be minimal. Here, a two‐step current sensor evaluation method is proposed. This method serves the characterization and suitability assessment of high‐power, high‐bandwidth current sensors for fast‐switching applications using SiC power MOSFETs. Conducting a small‐ and a large‐signal transmission behaviour analysis separately results in holistic information about the current sensor behaviour in both time and frequency domain. The proposed method is validated using four commercially available current sensors that are widely used for SiC power MOSFET characterization. The work concludes transferring the knowledge derived in the conducted experiments to a practical, application‐oriented sensor selection guide.

Silicon carbide (SiC) power metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) switch at an unprecedented speed, even at high currents. For accurate dynamic characterization, current sensors must measure high currents at a high bandwidth. Moreover, at high switching speeds, parasitic impedances in the commutation loop become critical. To ensure high‐accuracy measurements, the current sensor insertion impedance must be minimal. Here, a two‐step current sensor evaluation method is proposed. This method serves the characterization and suitability assessment of high‐power, high‐bandwidth current sensors for fast‐switching applications using SiC power MOSFETs. Conducting a small‐ and a large‐signal transmission behaviour analysis separately results in holistic information about the current sensor behaviour in both time and frequency domain. The proposed method is validated using four commercially available current sensors that are widely used for SiC power MOSFET characterization. The work concludes transferring the knowledge derived in the conducted experiments to a practical, application‐oriented sensor selection guide. [ABSTRACT FROM AUTHOR]

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications. [ABSTRACT FROM AUTHOR]

Flyback converters with synchronous rectifiers are an important topic in power electronics, given their widespread use in various applications and the focus on efficiency improvement. However, flyback converters suffer from a high overvoltage across the synchronous rectifier on their secondary side. This overshoot voltage is a result of resonance between the flyback transformer stray inductance and the output capacitance of the rectifier. This paper presents an in-depth experimental study on the optimization of dead time and Active Gate Driving in flyback converters employing synchronous rectifiers, i.e. Silicon Carbide Power MOSFETs in place of the secondary rectifier driven synchronously with the primary switch. The focus is the influence of symmetrical dead time variation between the primary and secondary switches on switching losses and overshoot voltage. In addition, the influence of a three voltage level active gate driver on the overshoot voltage and switching losses is examined, finding no significant influence. The findings from this study contribute to the existing body of knowledge by providing a nuanced understanding of dead time optimization in flyback converters with synchronous rectifiers, as well as the utilization of Active Gate Drivers in such systems. The results have implications for the design and operation of these converters, potentially leading to more efficient and reliable systems.

For single-event radiation damage of power MOSFET devices, this paper aims to establish a statistical analysis method based on external observation (gate/drain current characteristics in irradiation environment) to recognize and evaluate the radiation evolution process and damage mechanism of microscopic physical quantities inside the devices, namely current-carrier (CC) mapping. Firstly, a special data fluctuate–collapse transform analysis method is proposed according to the temporal characteristics of the gate/drain current. Secondly, a carrier dynamic balance ratio based on current data is defined to evaluate the radiation damage degree of the device. TCAD is used to deeply study the relationship between the external current characteristics and the evolution process of internal physical quantities and the damage mechanism. The results show that the current data timing analysis based on fluctuate–collapse transformation can better peer into the evolution process of irradiation events inside the device, and the statistical analysis based on the dynamic balance ratio of carriers can evaluate the severity of irradiation damage to a certain extent.

Abstract Due to the higher switching speed and lower threshold voltage of SiC MOSFET, its crosstalk issue is more serious than that of Si devices. Firstly, the mechanism and process of crosstalk under resistive load and inductive load are compared and analyzed. Then, a parameter decoupling method based on energy conservation is proposed, and an analytical model of the crosstalk voltage under resistive load is established. Moreover, an analytical model of the crosstalk voltage under inductive load with only device and circuit parameters is introduced. Furthermore, the influence of the drive resistance and the common source inductance on the crosstalk voltage under different loads is evaluated through the analytical model. Finally, a double pulse test is carried out to verify the validity of the analysis. The results presented here can provide guidance for the design of gate circuit parameters to regulate the crosstalk issue of SiC MOSFETs under different loads.

Abstract A novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device.

Abstract SiC MOSFET modules are widely used for bidirectional wireless charging of electric vehicles. However, prolonged use can result in bond wire faults, leading to reliability issues. To address this problem, a non‐contact bond wire monitoring method that can be carried out using the charging coil of the wireless charging device is proposed. Here, two monitoring loops are constructed based on the circuit topology, and their impedance magnitudes are measured on the charging coil to avoid the influence of battery voltage on monitoring results. To detect the bond wire condition, the impedance magnitude difference of the two monitoring loops is chosen as an indicator, which is very sensitive to the bond wire lift‐off. However, the monitoring results may be influenced by the aging of resonant capacitors and the offset of the charging coil. In particular, the influence of the coil offset is significant. To mitigate this effect, a prognostic parameter calibration method is proposed. Experimental results confirm the effectiveness of the proposed method, which provides a promising solution for the reliable and safe operation of SiC MOSFET modules in wireless charging devices.

Abstract This paper presents a method that improves the reliability of half‐bridge (HB) series resonant inverters (SRI) for high‐frequency induction heating applications. Many industrial processes, like induction heat treatments, are very repetitive. This cyclical operation represents a strong limitation of the inverter's reliability, mainly due to the accelerated stress of the power semiconductors. This method consists in an enhanced asymmetrical pulse width modulation (EAPWM) that allows distributing the losses across the components, thereby reducing the cyclic increase in junction temperature of the power devices, and thus achieves a reliability that is more than twice as high as that achieved using traditional modulation methods. The work methodology includes a theoretical study of the HB inverter and a complete analysis of losses. The presented design rules have been used to implement a 25 kW, 100 kHz inverter. The use of silicon carbide (SiC) MOSFET transistors allows reaching an efficiency greater than 99%. The analytical results obtained have been experimentally validated by testing the inverter on an induction heating test bench.

Abstract This letter, proposes and experimentally demonstrates a simple and efficient estimating method for high‐voltage floating field ring (FFR). Four rings in FFR are used to determine the influence of rings’ distance (d) on the voltage drops of the highest voltage to the third ring (Vn+1) and the third to the second ring (Vn). Then, two voltage curves (curves for Vn+1 and Vn) based on d are drawn. For a target breakdown voltage, by iterating between the curves for Vn+1 and Vn, the number of FFRs and corresponding distances can be found. Based on this method, an 8.0 kV PN diode with 111 FFRs is designed and fabricated. The measured breakdown voltage is 7840 V, which reaches 98% of the designed value. This method provides a simple and efficient design for high‐voltage SiC devices, especially for ultra‐high voltage applications where the number of rings exceeds dozens.

Herein, vertical double‐diffused metal‐oxide‐semiconductor field‐effect transistor(VDMOS) with improved device structure is proposed. Gate engineering is applied in the proposed device and two devices namely dual‐stepped gate technology (DSGT) and modified dual‐stepped gate technology (m‐DSGT) are proposed here. Due to the effect of gate engineering, switching ability is improved and area specific on‐resistance is reduced. Devices are simulated using Silvaco Atlas software. Breakdown voltages for conventional and m‐DSGT are 278.63 and 280.02 V, respectively, for VGS$V_{\text{GS}}$ = 0 V. The current density of conventional and m‐DSGT devices is 49.2$49.2$ and 178.5 A cm−2$178.5 \textrm{ } \text{A} \textrm{ } \left(\text{cm}\right)^{- 2}$ under the conditions on gate‐driven voltage of 1 V for VDS$V_{\text{DS}}$ = 10 V. Using 2D numerical simulations, the electrical performance of both DSGT and m‐DSGT devices is examined. The results demonstrate 76.6% decrease in specific on‐resistance, 4.22 times increase in current density, and 26.67% faster switching speed compared to conventional VDMOS, thus, improving the device performance. [ABSTRACT FROM AUTHOR]

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements. [ABSTRACT FROM AUTHOR]

Abstract This work presents a comparative analysis and design procedure of a converter based on an LLC resonant inverter used for induction heating applications depending on the transistor technology used and the selected operating frequency. A major objective of the work is to determinate the inverter design requirements leading to the optimal sizing of the components, improving its operation and minimizing power losses. Additionally, it proposes a design to obtain a great insensitivity of the inverter operation against large variations of load impedance. This article analyzes the operation of the inverter where the power regulation is carried out by phase‐shift (PS) modulation. Simple rules are formulated for the design of the resonant circuit components. The design has been verified testing a 25‐kW inverter in an industrial application of induction hardening operating at 500 kHz. Inverter efficiency is around 98.5% when using Silicon Carbide (SiC) MOSFETs.

This letter, proposes and experimentally demonstrates a simple and efficient estimating method for high‐voltage floating field ring (FFR). Four rings in FFR are used to determine the influence of rings' distance (d) on the voltage drops of the highest voltage to the third ring (Vn+1) and the third to the second ring (Vn). Then, two voltage curves (curves for Vn+1 and Vn) based on d are drawn. For a target breakdown voltage, by iterating between the curves for Vn+1 and Vn, the number of FFRs and corresponding distances can be found. Based on this method, an 8.0 kV PN diode with 111 FFRs is designed and fabricated. The measured breakdown voltage is 7840 V, which reaches 98% of the designed value. This method provides a simple and efficient design for high‐voltage SiC devices, especially for ultra‐high voltage applications where the number of rings exceeds dozens. [ABSTRACT FROM AUTHOR]

A novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device. [ABSTRACT FROM AUTHOR]

Due to the higher switching speed and lower threshold voltage of SiC MOSFET, its crosstalk issue is more serious than that of Si devices. Firstly, the mechanism and process of crosstalk under resistive load and inductive load are compared and analyzed. Then, a parameter decoupling method based on energy conservation is proposed, and an analytical model of the crosstalk voltage under resistive load is established. Moreover, an analytical model of the crosstalk voltage under inductive load with only device and circuit parameters is introduced. Furthermore, the influence of the drive resistance and the common source inductance on the crosstalk voltage under different loads is evaluated through the analytical model. Finally, a double pulse test is carried out to verify the validity of the analysis. The results presented here can provide guidance for the design of gate circuit parameters to regulate the crosstalk issue of SiC MOSFETs under different loads. [ABSTRACT FROM AUTHOR]

Abstract A 100‐V Taper‐Shielded trench Gate (TSG) power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with superior figure‐of‐merit (FOM) is proposed and investigated in this paper. The gate of the proposed TSG‐MOSFET has a tapered shape to reduce the gate‐to‐drain overlap capacitance (CGD) and the gate charge (QG). The vertical drift region doping profile of the proposed TSG‐MOSFET is enhanced in two ways. First is to use a multi‐step epitaxial growth to produce a non‐uniform doping profile. Second is to place a lightly doped n‐region at the trench bottom. The bulk electric field in the blocking state can be more evenly distributed, allowing a shorter drift region and lower specific ON‐resistance (RON,sp). Both technology computer‐aided design (TCAD) simulations and experiments were performed to evaluate the proposed device. The proposed device exhibits an improved RON,sp of 27 mΩ·mm2 with a breakdown voltage (BV) of 105 V. The third quadrant performance and the reverse recovery characteristics are also greatly improved. During reverse conduction, the amount of the excessive carriers stored in the drift region is reduced due to the shortened drift region and optimized drift region doping profile. The reverse recovery charge (Qrr) is decreased from 70 to 49 nC. When compared to its state‐of‐the‐art counterparts, the measured [RON × QG] FOM and the Qrr showed a reduction of 23% and 28%, respectively.

Accelerated neutron tests on silicon (Si) and silicon carbide (SiC) power MOSFETs at different temperatures and drain bias voltages were performed at the ChipIr facility (Didcot, UK). A super-junction silicon MOSFET and planar SiC MOSFETs with different technologies made by STMicroelectronics were used. Different test methods were employed to investigate the effects of temperature on neutron susceptibility in power MOSFETs. The destructive tests showed that all investigated devices failed via a single-event burnout (SEB) mechanism. Non-destructive tests conducted by using the power MOSFET as a neutron detector allowed measuring the temperature trend of the deposited charge due to neutron interactions. The results of the destructive tests, in the −50 °C–180 °C temperature range, revealed the lack of a common trend concerning the FIT temperature dependence among the investigated SiC power MOSFETs. Moreover, for some test vehicles, the FIT-temperature curves were dependent on the bias condition. The temperature dependence of the FIT values, observed in some SiC devices, is weaker with respect to that measured in the Si MOSFET. The results of the non-destructive tests showed a good correlation between the temperature trends of the deposited charge with those of FIT data, for both Si and SiC devices.

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga’s Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp).

We investigate the impact of power MOSFET channel width on the power efficiency of a switch-mode power supply. With this analysis, we derive a circuit-specific criterion that minimizes the power dissipated by a power MOSFET, which is based on the ratio between on resistance and output capacitance of the MOSFET and is independent of its technological parameters. The effect of channel width on the power dissipation is illustrated by simulation-based analysis, which also provide an example of a published non-optimum selection of a power MOSFET and demonstrate the advantage of the newly proposed method for MOSFET selection.

This work presents a comparative analysis and design procedure of a converter based on an LLC resonant inverter used for induction heating applications depending on the transistor technology used and the selected operating frequency. A major objective of the work is to determinate the inverter design requirements leading to the optimal sizing of the components, improving its operation and minimizing power losses. Additionally, it proposes a design to obtain a great insensitivity of the inverter operation against large variations of load impedance. This article analyzes the operation of the inverter where the power regulation is carried out by phase‐shift (PS) modulation. Simple rules are formulated for the design of the resonant circuit components. The design has been verified testing a 25‐kW inverter in an industrial application of induction hardening operating at 500 kHz. Inverter efficiency is around 98.5% when using Silicon Carbide (SiC) MOSFETs. [ABSTRACT FROM AUTHOR]

Severe switching oscillations of SiC MOSFET seriously affect its efficient and reliable application. Herein, a novel inductively coupled RLC damping scheme is proposed to eliminate switching oscillations. Distinctive from existing RLC resonators, the setting that the resonant frequency of the secondary RLC damping is equal to that of the power loop is abandoned. Additionally, prior‐art analytical techniques of RLC resonators are based on seeking the peak impedance, which considerably undermines its suppression effect. First, a two‐port network is linearized from switching oscillations, where the characteristic equations are deduced. Then, parametric regions where the switching oscillations can be eliminated are determined by actively assigning poles via the root locus method. Consequently, the damping effect of the proposed scheme, as well as the resulted switching losses, shows its superiority over the state‐of‐the‐art snubbers. The proposed scheme is favourable in practical applications since it is less insensitive to parasitics enabling selection of snubber resistors with higher power ratings. It also avoids unusual temperature rise resulted by snubber losses due to oscillation suppression in the power loop as snubber losses are transferred to the secondary circuit. Theoretical analysis and experimental comparisons are conducted to verify the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

As one of the core power electronic devices that undertake power conversion and control tasks in electrical systems, power MOSFETs are widely used in key fields such as transportation, industrial drives, and aerospace. At present, the traditional method improves the reliability of power electronic devices by new material/ structure/ process, redundancy, and derating operation, which is becoming increasingly difficult to meet the requirements of rapidly developing power conversion. Based on the needs of reliability research, a data-driven lifetime prediction method for thermal stress fatigue failure of power MOSFETs is proposed. The main work is reflected in two aspects: (1) The thermal stress fatigue failure mechanism of the power MOSFETs is analyzed. On-state resistance is selected as the failure precursor parameter for evaluating the health status of power MOSFETs. (2) Autoregressive Integrated Moving Average (ARIMA) model of Time-Series Analysis is applied to realize data-driven lifetime prediction. Compared with the model-based lifetime prediction method using nonlinear regression algorithm, The data-driven method has higher prediction accuracy and better prediction stability.

A 100‐V Taper‐Shielded trench Gate (TSG) power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with superior figure‐of‐merit (FOM) is proposed and investigated in this paper. The gate of the proposed TSG‐MOSFET has a tapered shape to reduce the gate‐to‐drain overlap capacitance (CGD) and the gate charge (QG). The vertical drift region doping profile of the proposed TSG‐MOSFET is enhanced in two ways. First is to use a multi‐step epitaxial growth to produce a non‐uniform doping profile. Second is to place a lightly doped n‐region at the trench bottom. The bulk electric field in the blocking state can be more evenly distributed, allowing a shorter drift region and lower specific ON‐resistance (RON,sp). Both technology computer‐aided design (TCAD) simulations and experiments were performed to evaluate the proposed device. The proposed device exhibits an improved RON,sp of 27 mΩ·mm2 with a breakdown voltage (BV) of 105 V. The third quadrant performance and the reverse recovery characteristics are also greatly improved. During reverse conduction, the amount of the excessive carriers stored in the drift region is reduced due to the shortened drift region and optimized drift region doping profile. The reverse recovery charge (Qrr) is decreased from 70 to 49 nC. When compared to its state‐of‐the‐art counterparts, the measured [RON × QG] FOM and the Qrr showed a reduction of 23% and 28%, respectively. [ABSTRACT FROM AUTHOR]

At present, in several European railway networks using traditional DC electrification systems, it is not possible to increase traffic nor to operate locomotives at their nominal power ratings. Trackside energy storage systems (TESSs) can be an alternative solution for the creation of new substations. A TESS limits contact line voltage drops and smooths the power absorbed during peak traffic. Thus, the efficiency of the power system can be increased while limiting costs and the environmental impact. This paper proposes a new topology of a TESS based on full-SiC isolated DC/DC converters associated with lithium-ion batteries and galvanic isolation, offering major advantages for operational safety. In the event of a fault, the input and output terminals of the converters are electrically separated, and the contact line voltage can never be directly applied to the batteries. In addition, the use of SiC MOSFETs makes it possible to obtain excellent efficiency with a high switching frequency. The first part of this paper presents the main characteristics of an elementary TESS module, while the second part proposes a sizing methodology for the typical case of a 1.5 kV DC line, which shows the limits of using TESSs to reinforce a power supply. Finally, the experimental results of an elementary module prototype are presented. [ABSTRACT FROM AUTHOR]

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga's Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp). [ABSTRACT FROM AUTHOR]

Based on the measured and the TCAD simulation results, this paper provides a detailed description of the third quadrant characteristics of the Schottky barrier diode (SBD) embedded MOSFETs with different Schottky area ratios of 2.6 %, 5.3 %, and 14.7 %. As the Schottky area ratio increases, the shift of the third quadrant turn-on voltages of the MOSFETs influenced by the gate voltage decreases. The shift rates in the conventional MOSFET and SBD-embedded MOSFETs are from 57.2 % to 0 % when V gs changes from 0 V to −4 V. The shift rate becomes 0 % when the Schottky area ratio is larger than 5.3 %. Simultaneously, the TCAD simulation results and the measured results indicate that the SBD-embedded MOSFETs can effectively suppress the conduction of the low barrier diode and the body diode. Furthermore, the SPICE models were built to explain the physics mechanisms. The fitting error between the measured and fitting results is as low as 1.3 % among the models with the different Schottky area ratios. [ABSTRACT FROM AUTHOR]

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

Multilevel Inverters have been gaining increased utilization for their applications with PV generation and other renewable resources in smart grid. The main aim of this work is to develop a Seven Level Multi-Level Inverter circuit with reduced switches. Lesser number of power switches will reduce the switching losses and complexity of the system. Power Mosfets are used for the switches as they have better commutation speed and switching efficiency at lower voltage levels. Pulse Width Modulation technique is used to provide the gating signals for the mosfets and a microcontroller is used to generate these pwm signals. LC filters are used to obtain pure sinusoidal output. The proposed inverter focuses on reducing the number of switches used to obtain seven level output which in turn will reduce the number of gate driver circuits required for driving the mosfets. Simulation of the inverter is carried out in MATLAB Simulink. Hardware Model of this inverter circuit is been designed for 24V and the output of the inverter is used to run motor load. [ABSTRACT FROM AUTHOR]

In this article, series connection of SiC MOSFETs has been attempted with the help of an active gate driving (AGD) technique. The gate currents of SiC MOSFETs are actively controlled in such a way that several devices can switch fast (within 50 ns) even in the presence of a moderate amount of gate pulse delay mismatch and jitter in the gate pulse. This enables the AGD’s to share the gate pulse signal information among each other. Such a feature can reduce the cost of the net solution by reducing the number of optical cables required for the gate pulse transmission. In addition to this, the AGD is designed in such a way that fast switching can be achieved even in the presence of moderate parasitic inductance in the layout. The proposed AGD technique is experimentally verified in a double pulse test setup with two and four switching devices in series using 32 A, 1 kV CREE SiC MOSFETs. The experimental results show turn-on and turn-off switching times of 45 and 34 ns, respectively, at 35 A load current. The AGD has also shown 47% reduction in the turn-off switching losses compared to the passive gate driving technique. [ABSTRACT FROM AUTHOR]